diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear320.h')
| -rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear320.h | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h deleted file mode 100644 index 8cfa83fa1296..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/spear320.h | ||
| 3 | * | ||
| 4 | * SPEAr320 Machine specific definition | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar<viresh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifdef CONFIG_MACH_SPEAR320 | ||
| 15 | |||
| 16 | #ifndef __MACH_SPEAR320_H | ||
| 17 | #define __MACH_SPEAR320_H | ||
| 18 | |||
| 19 | #define SPEAR320_EMI_CTRL_BASE UL(0x40000000) | ||
| 20 | #define SPEAR320_FSMC_BASE UL(0x4C000000) | ||
| 21 | #define SPEAR320_NAND_BASE UL(0x50000000) | ||
| 22 | #define SPEAR320_I2S_BASE UL(0x60000000) | ||
| 23 | #define SPEAR320_SDHCI_BASE UL(0x70000000) | ||
| 24 | #define SPEAR320_CLCD_BASE UL(0x90000000) | ||
| 25 | #define SPEAR320_PAR_PORT_BASE UL(0xA0000000) | ||
| 26 | #define SPEAR320_CAN0_BASE UL(0xA1000000) | ||
| 27 | #define SPEAR320_CAN1_BASE UL(0xA2000000) | ||
| 28 | #define SPEAR320_UART1_BASE UL(0xA3000000) | ||
| 29 | #define SPEAR320_UART2_BASE UL(0xA4000000) | ||
| 30 | #define SPEAR320_SSP0_BASE UL(0xA5000000) | ||
| 31 | #define SPEAR320_SSP1_BASE UL(0xA6000000) | ||
| 32 | #define SPEAR320_I2C_BASE UL(0xA7000000) | ||
| 33 | #define SPEAR320_PWM_BASE UL(0xA8000000) | ||
| 34 | #define SPEAR320_SMII0_BASE UL(0xAA000000) | ||
| 35 | #define SPEAR320_SMII1_BASE UL(0xAB000000) | ||
| 36 | #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) | ||
| 37 | |||
| 38 | /* Interrupt registers offsets and masks */ | ||
| 39 | #define SPEAR320_INT_STS_MASK_REG 0x04 | ||
| 40 | #define SPEAR320_INT_CLR_MASK_REG 0x04 | ||
| 41 | #define SPEAR320_INT_ENB_MASK_REG 0x08 | ||
| 42 | #define SPEAR320_GPIO_IRQ_MASK (1 << 0) | ||
| 43 | #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) | ||
| 44 | #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) | ||
| 45 | #define SPEAR320_EMI_IRQ_MASK (1 << 7) | ||
| 46 | #define SPEAR320_CLCD_IRQ_MASK (1 << 8) | ||
| 47 | #define SPEAR320_SPP_IRQ_MASK (1 << 9) | ||
| 48 | #define SPEAR320_SDHCI_IRQ_MASK (1 << 10) | ||
| 49 | #define SPEAR320_CAN_U_IRQ_MASK (1 << 11) | ||
| 50 | #define SPEAR320_CAN_L_IRQ_MASK (1 << 12) | ||
| 51 | #define SPEAR320_UART1_IRQ_MASK (1 << 13) | ||
| 52 | #define SPEAR320_UART2_IRQ_MASK (1 << 14) | ||
| 53 | #define SPEAR320_SSP1_IRQ_MASK (1 << 15) | ||
| 54 | #define SPEAR320_SSP2_IRQ_MASK (1 << 16) | ||
| 55 | #define SPEAR320_SMII0_IRQ_MASK (1 << 17) | ||
| 56 | #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) | ||
| 57 | #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) | ||
| 58 | #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) | ||
| 59 | #define SPEAR320_I2C1_IRQ_MASK (1 << 21) | ||
| 60 | |||
| 61 | #define SPEAR320_SHIRQ_RAS1_MASK 0x000380 | ||
| 62 | #define SPEAR320_SHIRQ_RAS3_MASK 0x000007 | ||
| 63 | #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 | ||
| 64 | |||
| 65 | #endif /* __MACH_SPEAR320_H */ | ||
| 66 | |||
| 67 | #endif /* CONFIG_MACH_SPEAR320 */ | ||