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-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
1 files changed, 19 insertions, 48 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958cd..940f0d85d959 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,54 +16,25 @@
16#ifndef __MACH_SPEAR320_H 16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H 17#define __MACH_SPEAR320_H
18 18
19#define SPEAR320_EMI_CTRL_BASE 0x40000000 19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_EMI_CTRL_SIZE 0x08000000 20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
21 37
22#define SPEAR320_FSMC_BASE 0x4C000000
23#define SPEAR320_FSMC_SIZE 0x01000000
24
25#define SPEAR320_I2S_BASE 0x60000000
26#define SPEAR320_I2S_SIZE 0x10000000
27
28#define SPEAR320_SDIO_BASE 0x70000000
29#define SPEAR320_SDIO_SIZE 0x10000000
30
31#define SPEAR320_CLCD_BASE 0x90000000
32#define SPEAR320_CLCD_SIZE 0x10000000
33
34#define SPEAR320_PAR_PORT_BASE 0xA0000000
35#define SPEAR320_PAR_PORT_SIZE 0x01000000
36
37#define SPEAR320_CAN0_BASE 0xA1000000
38#define SPEAR320_CAN0_SIZE 0x01000000
39
40#define SPEAR320_CAN1_BASE 0xA2000000
41#define SPEAR320_CAN1_SIZE 0x01000000
42
43#define SPEAR320_UART1_BASE 0xA3000000
44#define SPEAR320_UART2_BASE 0xA4000000
45#define SPEAR320_UART_SIZE 0x01000000
46
47#define SPEAR320_SSP0_BASE 0xA5000000
48#define SPEAR320_SSP0_SIZE 0x01000000
49
50#define SPEAR320_SSP1_BASE 0xA6000000
51#define SPEAR320_SSP1_SIZE 0x01000000
52
53#define SPEAR320_I2C_BASE 0xA7000000
54#define SPEAR320_I2C_SIZE 0x01000000
55
56#define SPEAR320_PWM_BASE 0xA8000000
57#define SPEAR320_PWM_SIZE 0x01000000
58
59#define SPEAR320_SMII0_BASE 0xAA000000
60#define SPEAR320_SMII0_SIZE 0x01000000
61
62#define SPEAR320_SMII1_BASE 0xAB000000
63#define SPEAR320_SMII1_SIZE 0x01000000
64
65#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
66#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
67/* Interrupt registers offsets and masks */ 38/* Interrupt registers offsets and masks */
68#define INT_STS_MASK_REG 0x04 39#define INT_STS_MASK_REG 0x04
69#define INT_CLR_MASK_REG 0x04 40#define INT_CLR_MASK_REG 0x04
@@ -74,7 +45,7 @@
74#define EMI_IRQ_MASK (1 << 7) 45#define EMI_IRQ_MASK (1 << 7)
75#define CLCD_IRQ_MASK (1 << 8) 46#define CLCD_IRQ_MASK (1 << 8)
76#define SPP_IRQ_MASK (1 << 9) 47#define SPP_IRQ_MASK (1 << 9)
77#define SDIO_IRQ_MASK (1 << 10) 48#define SDHCI_IRQ_MASK (1 << 10)
78#define CAN_U_IRQ_MASK (1 << 11) 49#define CAN_U_IRQ_MASK (1 << 11)
79#define CAN_L_IRQ_MASK (1 << 12) 50#define CAN_L_IRQ_MASK (1 << 12)
80#define UART1_IRQ_MASK (1 << 13) 51#define UART1_IRQ_MASK (1 << 13)