diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear310.h')
| -rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear310.h | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h deleted file mode 100644 index 1567d0da725f..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-spear3xx/include/mach/spear310.h | ||
| 3 | * | ||
| 4 | * SPEAr310 Machine specific definition | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 ST Microelectronics | ||
| 7 | * Viresh Kumar<viresh.kumar@st.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifdef CONFIG_MACH_SPEAR310 | ||
| 15 | |||
| 16 | #ifndef __MACH_SPEAR310_H | ||
| 17 | #define __MACH_SPEAR310_H | ||
| 18 | |||
| 19 | #define SPEAR310_NAND_BASE UL(0x40000000) | ||
| 20 | #define SPEAR310_FSMC_BASE UL(0x44000000) | ||
| 21 | #define SPEAR310_UART1_BASE UL(0xB2000000) | ||
| 22 | #define SPEAR310_UART2_BASE UL(0xB2080000) | ||
| 23 | #define SPEAR310_UART3_BASE UL(0xB2100000) | ||
| 24 | #define SPEAR310_UART4_BASE UL(0xB2180000) | ||
| 25 | #define SPEAR310_UART5_BASE UL(0xB2200000) | ||
| 26 | #define SPEAR310_HDLC_BASE UL(0xB2800000) | ||
| 27 | #define SPEAR310_RS485_0_BASE UL(0xB3000000) | ||
| 28 | #define SPEAR310_RS485_1_BASE UL(0xB3800000) | ||
| 29 | #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) | ||
| 30 | |||
| 31 | /* Interrupt registers offsets and masks */ | ||
| 32 | #define SPEAR310_INT_STS_MASK_REG 0x04 | ||
| 33 | #define SPEAR310_SMII0_IRQ_MASK (1 << 0) | ||
| 34 | #define SPEAR310_SMII1_IRQ_MASK (1 << 1) | ||
| 35 | #define SPEAR310_SMII2_IRQ_MASK (1 << 2) | ||
| 36 | #define SPEAR310_SMII3_IRQ_MASK (1 << 3) | ||
| 37 | #define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) | ||
| 38 | #define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) | ||
| 39 | #define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) | ||
| 40 | #define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) | ||
| 41 | #define SPEAR310_UART1_IRQ_MASK (1 << 8) | ||
| 42 | #define SPEAR310_UART2_IRQ_MASK (1 << 9) | ||
| 43 | #define SPEAR310_UART3_IRQ_MASK (1 << 10) | ||
| 44 | #define SPEAR310_UART4_IRQ_MASK (1 << 11) | ||
| 45 | #define SPEAR310_UART5_IRQ_MASK (1 << 12) | ||
| 46 | #define SPEAR310_EMI_IRQ_MASK (1 << 13) | ||
| 47 | #define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) | ||
| 48 | #define SPEAR310_RS485_0_IRQ_MASK (1 << 15) | ||
| 49 | #define SPEAR310_RS485_1_IRQ_MASK (1 << 16) | ||
| 50 | |||
| 51 | #define SPEAR310_SHIRQ_RAS1_MASK 0x000FF | ||
| 52 | #define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 | ||
| 53 | #define SPEAR310_SHIRQ_RAS3_MASK 0x02000 | ||
| 54 | #define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 | ||
| 55 | |||
| 56 | #endif /* __MACH_SPEAR310_H */ | ||
| 57 | |||
| 58 | #endif /* CONFIG_MACH_SPEAR310 */ | ||