diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear.h')
| -rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear.h | 59 |
1 files changed, 19 insertions, 40 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index 63fd98356919..51eb953148a9 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h | |||
| @@ -15,60 +15,26 @@ | |||
| 15 | #define __MACH_SPEAR3XX_H | 15 | #define __MACH_SPEAR3XX_H |
| 16 | 16 | ||
| 17 | #include <asm/memory.h> | 17 | #include <asm/memory.h> |
| 18 | #include <mach/spear300.h> | ||
| 19 | #include <mach/spear310.h> | ||
| 20 | #include <mach/spear320.h> | ||
| 21 | |||
| 22 | #define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) | ||
| 23 | |||
| 24 | #define SPEAR3XX_ICM9_BASE UL(0xC0000000) | ||
| 25 | 18 | ||
| 26 | /* ICM1 - Low speed connection */ | 19 | /* ICM1 - Low speed connection */ |
| 27 | #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) | 20 | #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) |
| 21 | #define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) | ||
| 28 | #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) | 22 | #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) |
| 29 | #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) | 23 | #define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) |
| 30 | #define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) | ||
| 31 | #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) | 24 | #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) |
| 32 | #define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) | ||
| 33 | #define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) | ||
| 34 | #define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) | ||
| 35 | #define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) | ||
| 36 | |||
| 37 | /* ICM2 - Application Subsystem */ | ||
| 38 | #define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) | ||
| 39 | #define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) | ||
| 40 | |||
| 41 | /* ICM4 - High Speed Connection */ | ||
| 42 | #define SPEAR3XX_ICM4_BASE UL(0xE0000000) | ||
| 43 | #define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) | ||
| 44 | #define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) | ||
| 45 | #define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) | ||
| 46 | #define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) | ||
| 47 | #define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) | ||
| 48 | #define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) | ||
| 49 | #define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) | ||
| 50 | #define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) | ||
| 51 | 25 | ||
| 52 | /* ML1 - Multi Layer CPU Subsystem */ | 26 | /* ML1 - Multi Layer CPU Subsystem */ |
| 53 | #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) | 27 | #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) |
| 54 | #define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) | 28 | #define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) |
| 55 | #define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) | ||
| 56 | #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) | ||
| 57 | 29 | ||
| 58 | /* ICM3 - Basic Subsystem */ | 30 | /* ICM3 - Basic Subsystem */ |
| 59 | #define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) | ||
| 60 | #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | 31 | #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) |
| 32 | #define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) | ||
| 61 | #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) | 33 | #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) |
| 62 | #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) | ||
| 63 | #define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) | ||
| 64 | #define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) | ||
| 65 | #define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) | ||
| 66 | #define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) | ||
| 67 | #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) | 34 | #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) |
| 68 | #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) | 35 | #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) |
| 69 | #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) | 36 | #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) |
| 70 | #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) | 37 | #define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) |
| 71 | #define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) | ||
| 72 | 38 | ||
| 73 | /* Debug uart for linux, will be used for debug and uncompress messages */ | 39 | /* Debug uart for linux, will be used for debug and uncompress messages */ |
| 74 | #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE | 40 | #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE |
| @@ -78,4 +44,17 @@ | |||
| 78 | #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE | 44 | #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE |
| 79 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE | 45 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE |
| 80 | 46 | ||
| 47 | /* SPEAr320 Macros */ | ||
| 48 | #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) | ||
| 49 | #define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) | ||
| 50 | #define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) | ||
| 51 | #define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) | ||
| 52 | #define SPEAR320_UARTX_PCLK_MASK 0x1 | ||
| 53 | #define SPEAR320_UART2_PCLK_SHIFT 8 | ||
| 54 | #define SPEAR320_UART3_PCLK_SHIFT 9 | ||
| 55 | #define SPEAR320_UART4_PCLK_SHIFT 10 | ||
| 56 | #define SPEAR320_UART5_PCLK_SHIFT 11 | ||
| 57 | #define SPEAR320_UART6_PCLK_SHIFT 12 | ||
| 58 | #define SPEAR320_RS485_PCLK_SHIFT 13 | ||
| 59 | |||
| 81 | #endif /* __MACH_SPEAR3XX_H */ | 60 | #endif /* __MACH_SPEAR3XX_H */ |