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-rw-r--r--arch/arm/mach-spear13xx/platsmp.c25
1 files changed, 15 insertions, 10 deletions
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index f5d07f2663d7..2eaa3fa7b432 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -19,18 +19,13 @@
19#include <asm/hardware/gic.h> 19#include <asm/hardware/gic.h>
20#include <asm/smp_scu.h> 20#include <asm/smp_scu.h>
21#include <mach/spear.h> 21#include <mach/spear.h>
22#include <mach/generic.h>
22 23
23/*
24 * control for which core is the next to come out of the secondary
25 * boot "holding pen"
26 */
27volatile int __cpuinitdata pen_release = -1;
28static DEFINE_SPINLOCK(boot_lock); 24static DEFINE_SPINLOCK(boot_lock);
29 25
30static void __iomem *scu_base = IOMEM(VA_SCU_BASE); 26static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
31extern void spear13xx_secondary_startup(void);
32 27
33void __cpuinit platform_secondary_init(unsigned int cpu) 28static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
34{ 29{
35 /* 30 /*
36 * if any interrupts are already enabled for the primary 31 * if any interrupts are already enabled for the primary
@@ -53,7 +48,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
53 spin_unlock(&boot_lock); 48 spin_unlock(&boot_lock);
54} 49}
55 50
56int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 51static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{ 52{
58 unsigned long timeout; 53 unsigned long timeout;
59 54
@@ -97,7 +92,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
97 * Initialise the CPU possible map early - this describes the CPUs 92 * Initialise the CPU possible map early - this describes the CPUs
98 * which may be present or become present in the system. 93 * which may be present or become present in the system.
99 */ 94 */
100void __init smp_init_cpus(void) 95static void __init spear13xx_smp_init_cpus(void)
101{ 96{
102 unsigned int i, ncores = scu_get_core_count(scu_base); 97 unsigned int i, ncores = scu_get_core_count(scu_base);
103 98
@@ -113,7 +108,7 @@ void __init smp_init_cpus(void)
113 set_smp_cross_call(gic_raise_softirq); 108 set_smp_cross_call(gic_raise_softirq);
114} 109}
115 110
116void __init platform_smp_prepare_cpus(unsigned int max_cpus) 111static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
117{ 112{
118 113
119 scu_enable(scu_base); 114 scu_enable(scu_base);
@@ -125,3 +120,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
125 */ 120 */
126 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); 121 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION);
127} 122}
123
124struct smp_operations spear13xx_smp_ops __initdata = {
125 .smp_init_cpus = spear13xx_smp_init_cpus,
126 .smp_prepare_cpus = spear13xx_smp_prepare_cpus,
127 .smp_secondary_init = spear13xx_secondary_init,
128 .smp_boot_secondary = spear13xx_boot_secondary,
129#ifdef CONFIG_HOTPLUG_CPU
130 .cpu_die = spear13xx_cpu_die,
131#endif
132};