diff options
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r-- | arch/arm/mach-socfpga/core.h | 11 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/platsmp.c | 15 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/socfpga.c | 16 |
3 files changed, 26 insertions, 16 deletions
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 315edff610f2..572b8f719ffb 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h | |||
@@ -20,12 +20,23 @@ | |||
20 | #ifndef __MACH_CORE_H | 20 | #ifndef __MACH_CORE_H |
21 | #define __MACH_CORE_H | 21 | #define __MACH_CORE_H |
22 | 22 | ||
23 | #define SOCFPGA_RSTMGR_CTRL 0x04 | ||
24 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 | ||
25 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c | ||
26 | |||
27 | /* System Manager bits */ | ||
28 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ | ||
29 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ | ||
30 | |||
23 | extern void socfpga_secondary_startup(void); | 31 | extern void socfpga_secondary_startup(void); |
24 | extern void __iomem *socfpga_scu_base_addr; | 32 | extern void __iomem *socfpga_scu_base_addr; |
25 | 33 | ||
26 | extern void socfpga_init_clocks(void); | 34 | extern void socfpga_init_clocks(void); |
27 | extern void socfpga_sysmgr_init(void); | 35 | extern void socfpga_sysmgr_init(void); |
28 | 36 | ||
37 | extern void __iomem *sys_manager_base_addr; | ||
38 | extern void __iomem *rst_manager_base_addr; | ||
39 | |||
29 | extern struct smp_operations socfpga_smp_ops; | 40 | extern struct smp_operations socfpga_smp_ops; |
30 | extern char secondary_trampoline, secondary_trampoline_end; | 41 | extern char secondary_trampoline, secondary_trampoline_end; |
31 | 42 | ||
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 84c60fa8daa0..b51ce8c7929d 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/of.h> | 23 | #include <linux/of.h> |
24 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
25 | #include <linux/irqchip/arm-gic.h> | ||
26 | 25 | ||
27 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
28 | #include <asm/smp_scu.h> | 27 | #include <asm/smp_scu.h> |
@@ -30,19 +29,6 @@ | |||
30 | 29 | ||
31 | #include "core.h" | 30 | #include "core.h" |
32 | 31 | ||
33 | extern void __iomem *sys_manager_base_addr; | ||
34 | extern void __iomem *rst_manager_base_addr; | ||
35 | |||
36 | static void __cpuinit socfpga_secondary_init(unsigned int cpu) | ||
37 | { | ||
38 | /* | ||
39 | * if any interrupts are already enabled for the primary | ||
40 | * core (e.g. timer irq), then they will not have been enabled | ||
41 | * for us: do so | ||
42 | */ | ||
43 | gic_secondary_init(0); | ||
44 | } | ||
45 | |||
46 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) | 32 | static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) |
47 | { | 33 | { |
48 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; | 34 | int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; |
@@ -109,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu) | |||
109 | struct smp_operations socfpga_smp_ops __initdata = { | 95 | struct smp_operations socfpga_smp_ops __initdata = { |
110 | .smp_init_cpus = socfpga_smp_init_cpus, | 96 | .smp_init_cpus = socfpga_smp_init_cpus, |
111 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, | 97 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, |
112 | .smp_secondary_init = socfpga_secondary_init, | ||
113 | .smp_boot_secondary = socfpga_boot_secondary, | 98 | .smp_boot_secondary = socfpga_boot_secondary, |
114 | #ifdef CONFIG_HOTPLUG_CPU | 99 | #ifdef CONFIG_HOTPLUG_CPU |
115 | .cpu_die = socfpga_cpu_die, | 100 | .cpu_die = socfpga_cpu_die, |
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 1042c023cf24..46a051359f02 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c | |||
@@ -15,6 +15,7 @@ | |||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
16 | */ | 16 | */ |
17 | #include <linux/dw_apb_timer.h> | 17 | #include <linux/dw_apb_timer.h> |
18 | #include <linux/clk-provider.h> | ||
18 | #include <linux/irqchip.h> | 19 | #include <linux/irqchip.h> |
19 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
20 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
@@ -29,6 +30,7 @@ | |||
29 | void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); | 30 | void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); |
30 | void __iomem *sys_manager_base_addr; | 31 | void __iomem *sys_manager_base_addr; |
31 | void __iomem *rst_manager_base_addr; | 32 | void __iomem *rst_manager_base_addr; |
33 | void __iomem *clk_mgr_base_addr; | ||
32 | unsigned long cpu1start_addr; | 34 | unsigned long cpu1start_addr; |
33 | 35 | ||
34 | static struct map_desc scu_io_desc __initdata = { | 36 | static struct map_desc scu_io_desc __initdata = { |
@@ -77,6 +79,9 @@ void __init socfpga_sysmgr_init(void) | |||
77 | 79 | ||
78 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); | 80 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); |
79 | rst_manager_base_addr = of_iomap(np, 0); | 81 | rst_manager_base_addr = of_iomap(np, 0); |
82 | |||
83 | np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); | ||
84 | clk_mgr_base_addr = of_iomap(np, 0); | ||
80 | } | 85 | } |
81 | 86 | ||
82 | static void __init socfpga_init_irq(void) | 87 | static void __init socfpga_init_irq(void) |
@@ -87,13 +92,22 @@ static void __init socfpga_init_irq(void) | |||
87 | 92 | ||
88 | static void socfpga_cyclone5_restart(char mode, const char *cmd) | 93 | static void socfpga_cyclone5_restart(char mode, const char *cmd) |
89 | { | 94 | { |
90 | /* TODO: */ | 95 | u32 temp; |
96 | |||
97 | temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | ||
98 | |||
99 | if (mode == 'h') | ||
100 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; | ||
101 | else | ||
102 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | ||
103 | writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | ||
91 | } | 104 | } |
92 | 105 | ||
93 | static void __init socfpga_cyclone5_init(void) | 106 | static void __init socfpga_cyclone5_init(void) |
94 | { | 107 | { |
95 | l2x0_of_init(0, ~0UL); | 108 | l2x0_of_init(0, ~0UL); |
96 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 109 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
110 | of_clk_init(NULL); | ||
97 | socfpga_init_clocks(); | 111 | socfpga_init_clocks(); |
98 | } | 112 | } |
99 | 113 | ||