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-rw-r--r--arch/arm/mach-shmobile/Kconfig75
-rw-r--r--arch/arm/mach-shmobile/Makefile8
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c172
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c91
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c94
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c348
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c81
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c52
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c208
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c107
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c238
-rw-r--r--arch/arm/mach-shmobile/board-lager.c46
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c199
-rw-r--r--arch/arm/mach-shmobile/board-marzen-reference.c75
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c119
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c115
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c114
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c107
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c219
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c93
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c50
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c115
-rw-r--r--arch/arm/mach-shmobile/clock.c13
-rw-r--r--arch/arm/mach-shmobile/cpuidle.c23
-rw-r--r--arch/arm/mach-shmobile/include/mach/clock.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h57
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a73a4.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h83
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h32
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h336
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h41
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h378
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c641
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c202
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c192
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c244
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c81
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c150
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c7
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c7
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c15
-rw-r--r--arch/arm/mach-shmobile/suspend.c6
44 files changed, 2934 insertions, 2362 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 75d413c004b6..1a517e2fe449 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -18,11 +18,28 @@ config ARCH_SH73A0
18 select SH_CLK_CPG 18 select SH_CLK_CPG
19 select RENESAS_INTC_IRQPIN 19 select RENESAS_INTC_IRQPIN
20 20
21config ARCH_R8A73A4
22 bool "R-Mobile APE6 (R8A73A40)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC
25 select CPU_V7
26 select ARM_ARCH_TIMER
27 select SH_CLK_CPG
28 select RENESAS_IRQC
29
21config ARCH_R8A7740 30config ARCH_R8A7740
22 bool "R-Mobile A1 (R8A77400)" 31 bool "R-Mobile A1 (R8A77400)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select ARM_GIC
34 select CPU_V7
35 select SH_CLK_CPG
36 select RENESAS_INTC_IRQPIN
37
38config ARCH_R8A7778
39 bool "R-Car M1 (R8A77780)"
24 select CPU_V7 40 select CPU_V7
25 select SH_CLK_CPG 41 select SH_CLK_CPG
42 select ARM_GIC
26 43
27config ARCH_R8A7779 44config ARCH_R8A7779
28 bool "R-Car H1 (R8A77790)" 45 bool "R-Car H1 (R8A77790)"
@@ -34,6 +51,15 @@ config ARCH_R8A7779
34 select USB_ARCH_HAS_OHCI 51 select USB_ARCH_HAS_OHCI
35 select RENESAS_INTC_IRQPIN 52 select RENESAS_INTC_IRQPIN
36 53
54config ARCH_R8A7790
55 bool "R-Car H2 (R8A77900)"
56 select ARCH_WANT_OPTIONAL_GPIOLIB
57 select ARM_GIC
58 select CPU_V7
59 select ARM_ARCH_TIMER
60 select SH_CLK_CPG
61 select RENESAS_IRQC
62
37config ARCH_EMEV2 63config ARCH_EMEV2
38 bool "Emma Mobile EV2" 64 bool "Emma Mobile EV2"
39 select ARCH_WANT_OPTIONAL_GPIOLIB 65 select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -70,6 +96,11 @@ config MACH_AG5EVM
70 select REGULATOR_FIXED_VOLTAGE if REGULATOR 96 select REGULATOR_FIXED_VOLTAGE if REGULATOR
71 select SH_LCD_MIPI_DSI 97 select SH_LCD_MIPI_DSI
72 98
99config MACH_APE6EVM
100 bool "APE6EVM board"
101 depends on ARCH_R8A73A4
102 select USE_OF
103
73config MACH_MACKEREL 104config MACH_MACKEREL
74 bool "mackerel board" 105 bool "mackerel board"
75 depends on ARCH_SH7372 106 depends on ARCH_SH7372
@@ -98,12 +129,37 @@ config MACH_ARMADILLO800EVA
98 select SND_SOC_WM8978 if SND_SIMPLE_CARD 129 select SND_SOC_WM8978 if SND_SIMPLE_CARD
99 select USE_OF 130 select USE_OF
100 131
132config MACH_BOCKW
133 bool "BOCK-W platform"
134 depends on ARCH_R8A7778
135 select ARCH_REQUIRE_GPIOLIB
136 select RENESAS_INTC_IRQPIN
137 select USE_OF
138
101config MACH_MARZEN 139config MACH_MARZEN
102 bool "MARZEN board" 140 bool "MARZEN board"
103 depends on ARCH_R8A7779 141 depends on ARCH_R8A7779
104 select ARCH_REQUIRE_GPIOLIB 142 select ARCH_REQUIRE_GPIOLIB
105 select REGULATOR_FIXED_VOLTAGE if REGULATOR 143 select REGULATOR_FIXED_VOLTAGE if REGULATOR
106 144
145config MACH_MARZEN_REFERENCE
146 bool "MARZEN board - Reference Device Tree Implementation"
147 depends on ARCH_R8A7779
148 select ARCH_REQUIRE_GPIOLIB
149 select REGULATOR_FIXED_VOLTAGE if REGULATOR
150 select USE_OF
151 ---help---
152 Use reference implementation of Marzen board support
153 which makes use of device tree at the expense
154 of not supporting a number of devices.
155
156 This is intended to aid developers
157
158config MACH_LAGER
159 bool "Lager board"
160 depends on ARCH_R8A7790
161 select USE_OF
162
107config MACH_KZM9D 163config MACH_KZM9D
108 bool "KZM9D board" 164 bool "KZM9D board"
109 depends on ARCH_EMEV2 165 depends on ARCH_EMEV2
@@ -118,6 +174,20 @@ config MACH_KZM9G
118 select SND_SOC_AK4642 if SND_SIMPLE_CARD 174 select SND_SOC_AK4642 if SND_SIMPLE_CARD
119 select USE_OF 175 select USE_OF
120 176
177config MACH_KZM9G_REFERENCE
178 bool "KZM-A9-GT board - Reference Device Tree Implementation"
179 depends on ARCH_SH73A0
180 select ARCH_REQUIRE_GPIOLIB
181 select REGULATOR_FIXED_VOLTAGE if REGULATOR
182 select SND_SOC_AK4642 if SND_SIMPLE_CARD
183 select USE_OF
184 ---help---
185 Use reference implementation of KZM-A9-GT board support
186 which makes as greater use of device tree at the expense
187 of not supporting a number of devices.
188
189 This is intended to aid developers
190
121comment "SH-Mobile System Configuration" 191comment "SH-Mobile System Configuration"
122 192
123config CPU_HAS_INTEVT 193config CPU_HAS_INTEVT
@@ -130,7 +200,8 @@ config MEMORY_START
130 hex "Physical memory start address" 200 hex "Physical memory start address"
131 default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ 201 default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
132 MACH_MACKEREL || MACH_BONITO || \ 202 MACH_MACKEREL || MACH_BONITO || \
133 MACH_ARMADILLO800EVA 203 MACH_ARMADILLO800EVA || MACH_APE6EVM || \
204 MACH_LAGER
134 default "0x41000000" if MACH_KOTA2 205 default "0x41000000" if MACH_KOTA2
135 default "0x00000000" 206 default "0x00000000"
136 ---help--- 207 ---help---
@@ -140,6 +211,8 @@ config MEMORY_START
140 211
141config MEMORY_SIZE 212config MEMORY_SIZE
142 hex "Physical memory size" 213 hex "Physical memory size"
214 default "0x80000000" if MACH_LAGER
215 default "0x40000000" if MACH_APE6EVM
143 default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ 216 default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
144 MACH_ARMADILLO800EVA 217 MACH_ARMADILLO800EVA
145 default "0x1e000000" if MACH_KOTA2 218 default "0x1e000000" if MACH_KOTA2
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b646ff4d742a..068f1dadc46b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,8 +8,11 @@ obj-y := timer.o console.o clock.o
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
12obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
13obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
14 17
15# SMP objects 18# SMP objects
@@ -34,13 +37,18 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
34# Board objects 37# Board objects
35obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o 38obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
36obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 39obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
40obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
37obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 41obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
38obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 42obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
39obj-$(CONFIG_MACH_BONITO) += board-bonito.o 43obj-$(CONFIG_MACH_BONITO) += board-bonito.o
44obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
40obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 45obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
46obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
47obj-$(CONFIG_MACH_LAGER) += board-lager.o
41obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 48obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
42obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o 49obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
43obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 50obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
51obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
44 52
45# Framework support 53# Framework support
46obj-$(CONFIG_SMP) += $(smp-y) 54obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a19c48c..c7540710906f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,8 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/platform_device.h> 28#include <linux/platform_device.h>
27#include <linux/delay.h> 29#include <linux/delay.h>
28#include <linux/io.h> 30#include <linux/io.h>
@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
304 306
305 if (brightness == 0) { 307 if (brightness == 0) {
306 /* Reset the chip */ 308 /* Reset the chip */
307 gpio_set_value(GPIO_PORT235, 0); 309 gpio_set_value(235, 0);
308 mdelay(24); 310 mdelay(24);
309 gpio_set_value(GPIO_PORT235, 1); 311 gpio_set_value(235, 1);
310 return 0; 312 return 0;
311 } 313 }
312 314
@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
406 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, 408 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
407 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 409 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
408 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 410 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
409 .cd_gpio = GPIO_PORT251, 411 .cd_gpio = 251,
410}; 412};
411 413
412static struct resource sdhi0_resources[] = { 414static struct resource sdhi0_resources[] = {
@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
461static struct fixed_voltage_config cn4_power_info = { 463static struct fixed_voltage_config cn4_power_info = {
462 .supply_name = "CN4 SD/MMC Vdd", 464 .supply_name = "CN4 SD/MMC Vdd",
463 .microvolts = 3300000, 465 .microvolts = 3300000,
464 .gpio = GPIO_PORT114, 466 .gpio = 114,
465 .enable_high = 1, 467 .enable_high = 1,
466 .init_data = &cn4_power_init_data, 468 .init_data = &cn4_power_init_data,
467}; 469};
@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
479 static int power_gpio = -EINVAL; 481 static int power_gpio = -EINVAL;
480 482
481 if (power_gpio < 0) { 483 if (power_gpio < 0) {
482 int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW, 484 int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
483 "sdhi1_power"); 485 "sdhi1_power");
484 if (!ret) 486 if (!ret)
485 power_gpio = GPIO_PORT114; 487 power_gpio = 114;
486 } 488 }
487 489
488 /* 490 /*
@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
493 * regulator driver. We have to live with the race in case the driver 495 * regulator driver. We have to live with the race in case the driver
494 * gets unloaded and the GPIO freed between these two steps. 496 * gets unloaded and the GPIO freed between these two steps.
495 */ 497 */
496 gpio_set_value(GPIO_PORT114, state); 498 gpio_set_value(114, state);
497} 499}
498 500
499static struct sh_mobile_sdhi_info sh_sdhi1_info = { 501static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
550 &sdhi1_device, 552 &sdhi1_device,
551}; 553};
552 554
555static unsigned long pin_pullup_conf[] = {
556 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
557};
558
559static const struct pinctrl_map ag5evm_pinctrl_map[] = {
560 /* FSIA */
561 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
562 "fsia_mclk_in", "fsia"),
563 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
564 "fsia_sclk_in", "fsia"),
565 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
566 "fsia_data_in", "fsia"),
567 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
568 "fsia_data_out", "fsia"),
569 /* I2C2 & I2C3 */
570 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
571 "i2c2_0", "i2c2"),
572 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
573 "i2c3_0", "i2c3"),
574 /* IrDA */
575 PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
576 "irda_0", "irda"),
577 /* KEYSC */
578 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
579 "keysc_in8", "keysc"),
580 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
581 "keysc_out04", "keysc"),
582 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
583 "keysc_out5", "keysc"),
584 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
585 "keysc_out6_0", "keysc"),
586 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
587 "keysc_out7_0", "keysc"),
588 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
589 "keysc_out8_0", "keysc"),
590 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
591 "keysc_out9_2", "keysc"),
592 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
593 "keysc_in8", pin_pullup_conf),
594 /* MMCIF */
595 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
596 "mmc0_data8_0", "mmc0"),
597 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
598 "mmc0_ctrl_0", "mmc0"),
599 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
600 "PORT279", pin_pullup_conf),
601 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
602 "mmc0_data8_0", pin_pullup_conf),
603 /* SCIFA2 */
604 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
605 "scifa2_data_0", "scifa2"),
606 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
607 "scifa2_ctrl_0", "scifa2"),
608 /* SDHI0 (CN15 [SD I/F]) */
609 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
610 "sdhi0_data4", "sdhi0"),
611 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
612 "sdhi0_ctrl", "sdhi0"),
613 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
614 "sdhi0_wp", "sdhi0"),
615 /* SDHI1 (CN4 [WLAN I/F]) */
616 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
617 "sdhi1_data4", "sdhi1"),
618 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
619 "sdhi1_ctrl", "sdhi1"),
620 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
621 "sdhi1_data4", pin_pullup_conf),
622 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
623 "PORT263", pin_pullup_conf),
624};
625
553static void __init ag5evm_init(void) 626static void __init ag5evm_init(void)
554{ 627{
555 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, 628 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
558 ARRAY_SIZE(fixed2v8_power_consumers), 3300000); 631 ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
559 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 632 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
560 633
634 pinctrl_register_mappings(ag5evm_pinctrl_map,
635 ARRAY_SIZE(ag5evm_pinctrl_map));
561 sh73a0_pinmux_init(); 636 sh73a0_pinmux_init();
562 637
563 /* enable SCIFA2 */
564 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
565 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
566 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
567 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
568
569 /* enable KEYSC */
570 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
571 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
572 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
573 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
574 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
575 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
576 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
577 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
578 gpio_request(GPIO_FN_KEYOUT0, NULL);
579 gpio_request(GPIO_FN_KEYOUT1, NULL);
580 gpio_request(GPIO_FN_KEYOUT2, NULL);
581 gpio_request(GPIO_FN_KEYOUT3, NULL);
582 gpio_request(GPIO_FN_KEYOUT4, NULL);
583 gpio_request(GPIO_FN_KEYOUT5, NULL);
584 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
585 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
586 gpio_request(GPIO_FN_KEYOUT8, NULL);
587 gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
588
589 /* enable I2C channel 2 and 3 */
590 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
591 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
592 gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
593 gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
594
595 /* enable MMCIF */ 638 /* enable MMCIF */
596 gpio_request(GPIO_FN_MMCCLK0, NULL); 639 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
597 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
598 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
599 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
600 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
601 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
602 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
603 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
604 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
605 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
606 gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
607 640
608 /* enable SMSC911X */ 641 /* enable SMSC911X */
609 gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ 642 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
610 gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ 643 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
611
612 /* FSI A */
613 gpio_request(GPIO_FN_FSIACK, NULL);
614 gpio_request(GPIO_FN_FSIAILR, NULL);
615 gpio_request(GPIO_FN_FSIAIBT, NULL);
616 gpio_request(GPIO_FN_FSIAISLD, NULL);
617 gpio_request(GPIO_FN_FSIAOSLD, NULL);
618
619 /* IrDA */
620 gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
621 gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
622 gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
623 644
624 /* LCD panel */ 645 /* LCD panel */
625 gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ 646 gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
626 mdelay(1); 647 mdelay(1);
627 gpio_set_value(GPIO_PORT217, 1); 648 gpio_set_value(217, 1);
628 mdelay(100); 649 mdelay(100);
629 650
630 /* LCD backlight controller */ 651 /* LCD backlight controller */
631 gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ 652 gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
632 lcd_backlight_set_brightness(0); 653 lcd_backlight_set_brightness(0);
633 654
634 /* enable SDHI0 on CN15 [SD I/F] */
635 gpio_request(GPIO_FN_SDHIWP0, NULL);
636 gpio_request(GPIO_FN_SDHICMD0, NULL);
637 gpio_request(GPIO_FN_SDHICLK0, NULL);
638 gpio_request(GPIO_FN_SDHID0_3, NULL);
639 gpio_request(GPIO_FN_SDHID0_2, NULL);
640 gpio_request(GPIO_FN_SDHID0_1, NULL);
641 gpio_request(GPIO_FN_SDHID0_0, NULL);
642
643 /* enable SDHI1 on CN4 [WLAN I/F] */
644 gpio_request(GPIO_FN_SDHICLK1, NULL);
645 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
646 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
647 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
648 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
649 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
650
651#ifdef CONFIG_CACHE_L2X0 655#ifdef CONFIG_CACHE_L2X0
652 /* Shared attribute override enable, 64K*8way */ 656 /* Shared attribute override enable, 64K*8way */
653 l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); 657 l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259a0daf..45f78cadec1d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h> 35#include <linux/i2c/tsc2007.h>
36#include <linux/io.h> 36#include <linux/io.h>
37#include <linux/pinctrl/machine.h>
37#include <linux/regulator/fixed.h> 38#include <linux/regulator/fixed.h>
38#include <linux/regulator/machine.h> 39#include <linux/regulator/machine.h>
39#include <linux/smsc911x.h> 40#include <linux/smsc911x.h>
@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
273 274
274/* 275/*
275 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 276 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
276 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 277 * connected to GPIO A22 of SH7372 (GPIO 41).
277 */ 278 */
278static int slot_cn7_get_cd(struct platform_device *pdev) 279static int slot_cn7_get_cd(struct platform_device *pdev)
279{ 280{
280 return !gpio_get_value(GPIO_PORT41); 281 return !gpio_get_value(41);
281} 282}
282/* MERAM */ 283/* MERAM */
283static struct sh_mobile_meram_info meram_info = { 284static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
838static struct gpio_led ap4evb_leds[] = { 839static struct gpio_led ap4evb_leds[] = {
839 { 840 {
840 .name = "led4", 841 .name = "led4",
841 .gpio = GPIO_PORT185, 842 .gpio = 185,
842 .default_state = LEDS_GPIO_DEFSTATE_ON, 843 .default_state = LEDS_GPIO_DEFSTATE_ON,
843 }, 844 },
844 { 845 {
845 .name = "led2", 846 .name = "led2",
846 .gpio = GPIO_PORT186, 847 .gpio = 186,
847 .default_state = LEDS_GPIO_DEFSTATE_ON, 848 .default_state = LEDS_GPIO_DEFSTATE_ON,
848 }, 849 },
849 { 850 {
850 .name = "led3", 851 .name = "led3",
851 .gpio = GPIO_PORT187, 852 .gpio = 187,
852 .default_state = LEDS_GPIO_DEFSTATE_ON, 853 .default_state = LEDS_GPIO_DEFSTATE_ON,
853 }, 854 },
854 { 855 {
855 .name = "led1", 856 .name = "led1",
856 .gpio = GPIO_PORT188, 857 .gpio = 188,
857 .default_state = LEDS_GPIO_DEFSTATE_ON, 858 .default_state = LEDS_GPIO_DEFSTATE_ON,
858 } 859 }
859}; 860};
@@ -1026,10 +1027,10 @@ out:
1026/* TouchScreen */ 1027/* TouchScreen */
1027#ifdef CONFIG_AP4EVB_QHD 1028#ifdef CONFIG_AP4EVB_QHD
1028# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 1029# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1029# define GPIO_TSC_PORT GPIO_PORT123 1030# define GPIO_TSC_PORT 123
1030#else /* WVGA */ 1031#else /* WVGA */
1031# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 1032# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1032# define GPIO_TSC_PORT GPIO_PORT40 1033# define GPIO_TSC_PORT 40
1033#endif 1034#endif
1034 1035
1035#define IRQ28 evt2irq(0x3380) /* IRQ28A */ 1036#define IRQ28 evt2irq(0x3380) /* IRQ28A */
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
1084}; 1085};
1085 1086
1086 1087
1088static const struct pinctrl_map ap4evb_pinctrl_map[] = {
1089 /* MMCIF */
1090 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1091 "mmc0_data8_0", "mmc0"),
1092 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1093 "mmc0_ctrl_0", "mmc0"),
1094 /* SDHI0 */
1095 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1096 "sdhi0_data4", "sdhi0"),
1097 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1098 "sdhi0_ctrl", "sdhi0"),
1099 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1100 "sdhi0_cd", "sdhi0"),
1101 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1102 "sdhi0_wp", "sdhi0"),
1103 /* SDHI1 */
1104 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1105 "sdhi1_data4", "sdhi1"),
1106 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1107 "sdhi1_ctrl", "sdhi1"),
1108};
1109
1087#define GPIO_PORT9CR IOMEM(0xE6051009) 1110#define GPIO_PORT9CR IOMEM(0xE6051009)
1088#define GPIO_PORT10CR IOMEM(0xE605100A) 1111#define GPIO_PORT10CR IOMEM(0xE605100A)
1089#define USCCR1 IOMEM(0xE6058144) 1112#define USCCR1 IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
1110 /* External clock source */ 1133 /* External clock source */
1111 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1134 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1112 1135
1136 pinctrl_register_mappings(ap4evb_pinctrl_map,
1137 ARRAY_SIZE(ap4evb_pinctrl_map));
1113 sh7372_pinmux_init(); 1138 sh7372_pinmux_init();
1114 1139
1115 /* enable SCIFA0 */ 1140 /* enable SCIFA0 */
@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
1121 gpio_request(GPIO_FN_IRQ6_39, NULL); 1146 gpio_request(GPIO_FN_IRQ6_39, NULL);
1122 1147
1123 /* enable Debug switch (S6) */ 1148 /* enable Debug switch (S6) */
1124 gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL); 1149 gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
1125 gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL); 1150 gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
1126 gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL); 1151 gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
1127 gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL); 1152 gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
1128
1129 /* SDHI0 */
1130 gpio_request(GPIO_FN_SDHICD0, NULL);
1131 gpio_request(GPIO_FN_SDHIWP0, NULL);
1132 gpio_request(GPIO_FN_SDHICMD0, NULL);
1133 gpio_request(GPIO_FN_SDHICLK0, NULL);
1134 gpio_request(GPIO_FN_SDHID0_3, NULL);
1135 gpio_request(GPIO_FN_SDHID0_2, NULL);
1136 gpio_request(GPIO_FN_SDHID0_1, NULL);
1137 gpio_request(GPIO_FN_SDHID0_0, NULL);
1138
1139 /* SDHI1 */
1140 gpio_request(GPIO_FN_SDHICMD1, NULL);
1141 gpio_request(GPIO_FN_SDHICLK1, NULL);
1142 gpio_request(GPIO_FN_SDHID1_3, NULL);
1143 gpio_request(GPIO_FN_SDHID1_2, NULL);
1144 gpio_request(GPIO_FN_SDHID1_1, NULL);
1145 gpio_request(GPIO_FN_SDHID1_0, NULL);
1146
1147 /* MMCIF */
1148 gpio_request(GPIO_FN_MMCD0_0, NULL);
1149 gpio_request(GPIO_FN_MMCD0_1, NULL);
1150 gpio_request(GPIO_FN_MMCD0_2, NULL);
1151 gpio_request(GPIO_FN_MMCD0_3, NULL);
1152 gpio_request(GPIO_FN_MMCD0_4, NULL);
1153 gpio_request(GPIO_FN_MMCD0_5, NULL);
1154 gpio_request(GPIO_FN_MMCD0_6, NULL);
1155 gpio_request(GPIO_FN_MMCD0_7, NULL);
1156 gpio_request(GPIO_FN_MMCCMD0, NULL);
1157 gpio_request(GPIO_FN_MMCCLK0, NULL);
1158 1153
1159 /* USB enable */ 1154 /* USB enable */
1160 gpio_request(GPIO_FN_VBUS0_1, NULL); 1155 gpio_request(GPIO_FN_VBUS0_1, NULL);
@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
1172 gpio_request(GPIO_FN_FSIAILR, NULL); 1167 gpio_request(GPIO_FN_FSIAILR, NULL);
1173 gpio_request(GPIO_FN_FSIAISLD, NULL); 1168 gpio_request(GPIO_FN_FSIAISLD, NULL);
1174 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1169 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1175 gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ 1170 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1176 1171
1177 gpio_request(GPIO_PORT9, NULL); 1172 gpio_request(9, NULL);
1178 gpio_request(GPIO_PORT10, NULL); 1173 gpio_request(10, NULL);
1179 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1174 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1180 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1175 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1181 1176
1182 /* card detect pin for MMC slot (CN7) */ 1177 /* card detect pin for MMC slot (CN7) */
1183 gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); 1178 gpio_request_one(41, GPIOF_IN, NULL);
1184 1179
1185 /* setup FSI2 port B (HDMI) */ 1180 /* setup FSI2 port B (HDMI) */
1186 gpio_request(GPIO_FN_FSIBCK, NULL); 1181 gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
1268 gpio_request(GPIO_FN_LCDDISP, NULL); 1263 gpio_request(GPIO_FN_LCDDISP, NULL);
1269 gpio_request(GPIO_FN_LCDDCK, NULL); 1264 gpio_request(GPIO_FN_LCDDCK, NULL);
1270 1265
1271 gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ 1266 gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
1272 gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1267 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1273 1268
1274 lcdc_info.clock_source = LCDC_CLK_BUS; 1269 lcdc_info.clock_source = LCDC_CLK_BUS;
1275 lcdc_info.ch[0].interface_type = RGB18; 1270 lcdc_info.ch[0].interface_type = RGB18;
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
new file mode 100644
index 000000000000..55b8c9fef954
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -0,0 +1,94 @@
1/*
2 * APE6EVM board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/irqchip.h>
24#include <linux/kernel.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/fixed.h>
28#include <linux/regulator/machine.h>
29#include <linux/smsc911x.h>
30#include <mach/common.h>
31#include <mach/irqs.h>
32#include <mach/r8a73a4.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35
36/* Dummy supplies, where voltage doesn't matter */
37static struct regulator_consumer_supply dummy_supplies[] = {
38 REGULATOR_SUPPLY("vddvario", "smsc911x"),
39 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
40};
41
42/* SMSC LAN9220 */
43static const struct resource lan9220_res[] = {
44 DEFINE_RES_MEM(0x08000000, 0x1000),
45 {
46 .start = irq_pin(40), /* IRQ40 */
47 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
48 },
49};
50
51static const struct smsc911x_platform_config lan9220_data = {
52 .flags = SMSC911X_USE_32BIT,
53 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
54 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
55};
56
57static const struct pinctrl_map ape6evm_pinctrl_map[] = {
58 /* SCIFA0 console */
59 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
60 "scifa0_data", "scifa0"),
61 /* SMSC */
62 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
63 "irqc_irq40", "irqc"),
64};
65
66static void __init ape6evm_add_standard_devices(void)
67{
68 r8a73a4_clock_init();
69 pinctrl_register_mappings(ape6evm_pinctrl_map,
70 ARRAY_SIZE(ape6evm_pinctrl_map));
71 r8a73a4_pinmux_init();
72 r8a73a4_add_standard_devices();
73
74 /* LAN9220 ethernet */
75 gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
76
77 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
78
79 platform_device_register_resndata(&platform_bus, "smsc911x", -1,
80 lan9220_res, ARRAY_SIZE(lan9220_res),
81 &lan9220_data, sizeof(lan9220_data));
82}
83
84static const char *ape6evm_boards_compat_dt[] __initdata = {
85 "renesas,ape6evm",
86 NULL,
87};
88
89DT_MACHINE_START(APE6EVM_DT, "ape6evm")
90 .init_irq = irqchip_init,
91 .init_time = shmobile_timer_init,
92 .init_machine = ape6evm_add_standard_devices,
93 .dt_compat = ape6evm_boards_compat_dt,
94MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index f2ec0777cfbe..b85b2882dbd0 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -24,11 +24,15 @@
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/input.h> 26#include <linux/input.h>
27#include <linux/platform_data/st1232_pdata.h>
27#include <linux/irq.h> 28#include <linux/irq.h>
28#include <linux/platform_device.h> 29#include <linux/platform_device.h>
29#include <linux/gpio.h> 30#include <linux/gpio.h>
30#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
32#include <linux/regulator/driver.h>
33#include <linux/pinctrl/machine.h>
31#include <linux/regulator/fixed.h> 34#include <linux/regulator/fixed.h>
35#include <linux/regulator/gpio-regulator.h>
32#include <linux/regulator/machine.h> 36#include <linux/regulator/machine.h>
33#include <linux/sh_eth.h> 37#include <linux/sh_eth.h>
34#include <linux/videodev2.h> 38#include <linux/videodev2.h>
@@ -145,7 +149,7 @@
145 * see 149 * see
146 * usbhsf_power_ctrl() 150 * usbhsf_power_ctrl()
147 */ 151 */
148#define IRQ7 evt2irq(0x02e0) 152#define IRQ7 irq_pin(7)
149#define USBCR1 IOMEM(0xe605810a) 153#define USBCR1 IOMEM(0xe605810a)
150#define USBH 0xC6700000 154#define USBH 0xC6700000
151#define USBH_USBCTR 0x10834 155#define USBH_USBCTR 0x10834
@@ -169,7 +173,7 @@ static int usbhsf_get_id(struct platform_device *pdev)
169 return USBHS_GADGET; 173 return USBHS_GADGET;
170} 174}
171 175
172static void usbhsf_power_ctrl(struct platform_device *pdev, 176static int usbhsf_power_ctrl(struct platform_device *pdev,
173 void __iomem *base, int enable) 177 void __iomem *base, int enable)
174{ 178{
175 struct usbhsf_private *priv = usbhsf_get_priv(pdev); 179 struct usbhsf_private *priv = usbhsf_get_priv(pdev);
@@ -223,11 +227,13 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
223 clk_disable(priv->pci); /* usb work around */ 227 clk_disable(priv->pci); /* usb work around */
224 clk_disable(priv->usb24); /* usb work around */ 228 clk_disable(priv->usb24); /* usb work around */
225 } 229 }
230
231 return 0;
226} 232}
227 233
228static int usbhsf_get_vbus(struct platform_device *pdev) 234static int usbhsf_get_vbus(struct platform_device *pdev)
229{ 235{
230 return gpio_get_value(GPIO_PORT209); 236 return gpio_get_value(209);
231} 237}
232 238
233static irqreturn_t usbhsf_interrupt(int irq, void *data) 239static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -239,7 +245,7 @@ static irqreturn_t usbhsf_interrupt(int irq, void *data)
239 return IRQ_HANDLED; 245 return IRQ_HANDLED;
240} 246}
241 247
242static void usbhsf_hardware_exit(struct platform_device *pdev) 248static int usbhsf_hardware_exit(struct platform_device *pdev)
243{ 249{
244 struct usbhsf_private *priv = usbhsf_get_priv(pdev); 250 struct usbhsf_private *priv = usbhsf_get_priv(pdev);
245 251
@@ -264,6 +270,8 @@ static void usbhsf_hardware_exit(struct platform_device *pdev)
264 priv->usbh_base = NULL; 270 priv->usbh_base = NULL;
265 271
266 free_irq(IRQ7, pdev); 272 free_irq(IRQ7, pdev);
273
274 return 0;
267} 275}
268 276
269static int usbhsf_hardware_init(struct platform_device *pdev) 277static int usbhsf_hardware_init(struct platform_device *pdev)
@@ -330,7 +338,7 @@ static struct resource usbhsf_resources[] = {
330 .flags = IORESOURCE_MEM, 338 .flags = IORESOURCE_MEM,
331 }, 339 },
332 { 340 {
333 .start = evt2irq(0x0A20), 341 .start = gic_spi(51),
334 .flags = IORESOURCE_IRQ, 342 .flags = IORESOURCE_IRQ,
335 }, 343 },
336}; 344};
@@ -363,7 +371,7 @@ static struct resource sh_eth_resources[] = {
363 .end = 0xe9a02000 - 1, 371 .end = 0xe9a02000 - 1,
364 .flags = IORESOURCE_MEM, 372 .flags = IORESOURCE_MEM,
365 }, { 373 }, {
366 .start = evt2irq(0x0500), 374 .start = gic_spi(110),
367 .flags = IORESOURCE_IRQ, 375 .flags = IORESOURCE_IRQ,
368 }, 376 },
369}; 377};
@@ -417,7 +425,7 @@ static struct resource lcdc0_resources[] = {
417 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
418 }, 426 },
419 [1] = { 427 [1] = {
420 .start = intcs_evt2irq(0x580), 428 .start = gic_spi(177),
421 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
422 }, 430 },
423}; 431};
@@ -452,7 +460,7 @@ static struct resource hdmi_resources[] = {
452 .flags = IORESOURCE_MEM, 460 .flags = IORESOURCE_MEM,
453 }, 461 },
454 [1] = { 462 [1] = {
455 .start = evt2irq(0x1700), 463 .start = gic_spi(131),
456 .flags = IORESOURCE_IRQ, 464 .flags = IORESOURCE_IRQ,
457 }, 465 },
458 [2] = { 466 [2] = {
@@ -514,7 +522,7 @@ static struct resource hdmi_lcdc_resources[] = {
514 .flags = IORESOURCE_MEM, 522 .flags = IORESOURCE_MEM,
515 }, 523 },
516 [1] = { 524 [1] = {
517 .start = intcs_evt2irq(0x1780), 525 .start = gic_spi(178),
518 .flags = IORESOURCE_IRQ, 526 .flags = IORESOURCE_IRQ,
519 }, 527 },
520}; 528};
@@ -535,10 +543,10 @@ static struct platform_device hdmi_lcdc_device = {
535 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } 543 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
536 544
537static struct gpio_keys_button gpio_buttons[] = { 545static struct gpio_keys_button gpio_buttons[] = {
538 GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), 546 GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
539 GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), 547 GPIO_KEY(KEY_BACK, 100, "SW4"),
540 GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), 548 GPIO_KEY(KEY_MENU, 97, "SW5"),
541 GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), 549 GPIO_KEY(KEY_HOME, 98, "SW6"),
542}; 550};
543 551
544static struct gpio_keys_platform_data gpio_key_info = { 552static struct gpio_keys_platform_data gpio_key_info = {
@@ -554,15 +562,119 @@ static struct platform_device gpio_keys_device = {
554 }, 562 },
555}; 563};
556 564
557/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */ 565/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */
558static struct regulator_consumer_supply fixed3v3_power_consumers[] = 566static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
559{ 567 REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
568 REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
569};
570
571/* Fixed 3.3V regulator to be used by SDHI0 */
572static struct regulator_consumer_supply vcc_sdhi0_consumers[] = {
560 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), 573 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
574};
575
576static struct regulator_init_data vcc_sdhi0_init_data = {
577 .constraints = {
578 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
579 },
580 .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
581 .consumer_supplies = vcc_sdhi0_consumers,
582};
583
584static struct fixed_voltage_config vcc_sdhi0_info = {
585 .supply_name = "SDHI0 Vcc",
586 .microvolts = 3300000,
587 .gpio = GPIO_PORT75,
588 .enable_high = 1,
589 .init_data = &vcc_sdhi0_init_data,
590};
591
592static struct platform_device vcc_sdhi0 = {
593 .name = "reg-fixed-voltage",
594 .id = 1,
595 .dev = {
596 .platform_data = &vcc_sdhi0_info,
597 },
598};
599
600/* 1.8 / 3.3V SDHI0 VccQ regulator */
601static struct regulator_consumer_supply vccq_sdhi0_consumers[] = {
561 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), 602 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
603};
604
605static struct regulator_init_data vccq_sdhi0_init_data = {
606 .constraints = {
607 .input_uV = 3300000,
608 .min_uV = 1800000,
609 .max_uV = 3300000,
610 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
611 REGULATOR_CHANGE_STATUS,
612 },
613 .num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers),
614 .consumer_supplies = vccq_sdhi0_consumers,
615};
616
617static struct gpio vccq_sdhi0_gpios[] = {
618 {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
619};
620
621static struct gpio_regulator_state vccq_sdhi0_states[] = {
622 { .value = 3300000, .gpios = (0 << 0) },
623 { .value = 1800000, .gpios = (1 << 0) },
624};
625
626static struct gpio_regulator_config vccq_sdhi0_info = {
627 .supply_name = "vqmmc",
628
629 .enable_gpio = GPIO_PORT74,
630 .enable_high = 1,
631 .enabled_at_boot = 0,
632
633 .gpios = vccq_sdhi0_gpios,
634 .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios),
635
636 .states = vccq_sdhi0_states,
637 .nr_states = ARRAY_SIZE(vccq_sdhi0_states),
638
639 .type = REGULATOR_VOLTAGE,
640 .init_data = &vccq_sdhi0_init_data,
641};
642
643static struct platform_device vccq_sdhi0 = {
644 .name = "gpio-regulator",
645 .id = -1,
646 .dev = {
647 .platform_data = &vccq_sdhi0_info,
648 },
649};
650
651/* Fixed 3.3V regulator to be used by SDHI1 */
652static struct regulator_consumer_supply vcc_sdhi1_consumers[] = {
562 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), 653 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
563 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), 654};
564 REGULATOR_SUPPLY("vmmc", "sh_mmcif"), 655
565 REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), 656static struct regulator_init_data vcc_sdhi1_init_data = {
657 .constraints = {
658 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
659 },
660 .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers),
661 .consumer_supplies = vcc_sdhi1_consumers,
662};
663
664static struct fixed_voltage_config vcc_sdhi1_info = {
665 .supply_name = "SDHI1 Vcc",
666 .microvolts = 3300000,
667 .gpio = GPIO_PORT16,
668 .enable_high = 1,
669 .init_data = &vcc_sdhi1_init_data,
670};
671
672static struct platform_device vcc_sdhi1 = {
673 .name = "reg-fixed-voltage",
674 .id = 2,
675 .dev = {
676 .platform_data = &vcc_sdhi1_info,
677 },
566}; 678};
567 679
568/* SDHI0 */ 680/* SDHI0 */
@@ -574,14 +686,14 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
574 * We can use IRQ31 as card detect irq, 686 * We can use IRQ31 as card detect irq,
575 * but it needs chattering removal operation 687 * but it needs chattering removal operation
576 */ 688 */
577#define IRQ31 evt2irq(0x33E0) 689#define IRQ31 irq_pin(31)
578static struct sh_mobile_sdhi_info sdhi0_info = { 690static struct sh_mobile_sdhi_info sdhi0_info = {
579 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 691 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
580 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 692 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
581 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\ 693 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
582 MMC_CAP_NEEDS_POLL, 694 MMC_CAP_POWER_OFF_CARD,
583 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 695 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
584 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 696 .cd_gpio = GPIO_PORT167,
585}; 697};
586 698
587static struct resource sdhi0_resources[] = { 699static struct resource sdhi0_resources[] = {
@@ -596,12 +708,12 @@ static struct resource sdhi0_resources[] = {
596 */ 708 */
597 { 709 {
598 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 710 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
599 .start = evt2irq(0x0E20), 711 .start = gic_spi(118),
600 .flags = IORESOURCE_IRQ, 712 .flags = IORESOURCE_IRQ,
601 }, 713 },
602 { 714 {
603 .name = SH_MOBILE_SDHI_IRQ_SDIO, 715 .name = SH_MOBILE_SDHI_IRQ_SDIO,
604 .start = evt2irq(0x0E40), 716 .start = gic_spi(119),
605 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
606 }, 718 },
607}; 719};
@@ -620,9 +732,11 @@ static struct platform_device sdhi0_device = {
620static struct sh_mobile_sdhi_info sdhi1_info = { 732static struct sh_mobile_sdhi_info sdhi1_info = {
621 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 733 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
622 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 734 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
623 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, 735 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
624 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 736 MMC_CAP_POWER_OFF_CARD,
625 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 737 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
738 /* Port72 cannot generate IRQs, will be used in polling mode. */
739 .cd_gpio = GPIO_PORT72,
626}; 740};
627 741
628static struct resource sdhi1_resources[] = { 742static struct resource sdhi1_resources[] = {
@@ -633,15 +747,15 @@ static struct resource sdhi1_resources[] = {
633 .flags = IORESOURCE_MEM, 747 .flags = IORESOURCE_MEM,
634 }, 748 },
635 [1] = { 749 [1] = {
636 .start = evt2irq(0x0E80), 750 .start = gic_spi(121),
637 .flags = IORESOURCE_IRQ, 751 .flags = IORESOURCE_IRQ,
638 }, 752 },
639 [2] = { 753 [2] = {
640 .start = evt2irq(0x0EA0), 754 .start = gic_spi(122),
641 .flags = IORESOURCE_IRQ, 755 .flags = IORESOURCE_IRQ,
642 }, 756 },
643 [3] = { 757 [3] = {
644 .start = evt2irq(0x0EC0), 758 .start = gic_spi(123),
645 .flags = IORESOURCE_IRQ, 759 .flags = IORESOURCE_IRQ,
646 }, 760 },
647}; 761};
@@ -656,10 +770,20 @@ static struct platform_device sdhi1_device = {
656 .resource = sdhi1_resources, 770 .resource = sdhi1_resources,
657}; 771};
658 772
773static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
774 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
775 "sdhi1_data4", "sdhi1"),
776 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
777 "sdhi1_ctrl", "sdhi1"),
778 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
779 "sdhi1_cd", "sdhi1"),
780 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
781 "sdhi1_wp", "sdhi1"),
782};
783
659/* MMCIF */ 784/* MMCIF */
660static struct sh_mmcif_plat_data sh_mmcif_plat = { 785static struct sh_mmcif_plat_data sh_mmcif_plat = {
661 .sup_pclk = 0, 786 .sup_pclk = 0,
662 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
663 .caps = MMC_CAP_4_BIT_DATA | 787 .caps = MMC_CAP_4_BIT_DATA |
664 MMC_CAP_8_BIT_DATA | 788 MMC_CAP_8_BIT_DATA |
665 MMC_CAP_NONREMOVABLE, 789 MMC_CAP_NONREMOVABLE,
@@ -674,12 +798,12 @@ static struct resource sh_mmcif_resources[] = {
674 }, 798 },
675 [1] = { 799 [1] = {
676 /* MMC ERR */ 800 /* MMC ERR */
677 .start = evt2irq(0x1AC0), 801 .start = gic_spi(56),
678 .flags = IORESOURCE_IRQ, 802 .flags = IORESOURCE_IRQ,
679 }, 803 },
680 [2] = { 804 [2] = {
681 /* MMC NOR */ 805 /* MMC NOR */
682 .start = evt2irq(0x1AE0), 806 .start = gic_spi(57),
683 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
684 }, 808 },
685}; 809};
@@ -708,9 +832,9 @@ static int mt9t111_power(struct device *dev, int mode)
708 /* video1 (= CON1 camera) expect 24MHz */ 832 /* video1 (= CON1 camera) expect 24MHz */
709 clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); 833 clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
710 clk_enable(mclk); 834 clk_enable(mclk);
711 gpio_set_value(GPIO_PORT158, 1); 835 gpio_set_value(158, 1);
712 } else { 836 } else {
713 gpio_set_value(GPIO_PORT158, 0); 837 gpio_set_value(158, 0);
714 clk_disable(mclk); 838 clk_disable(mclk);
715 } 839 }
716 840
@@ -756,7 +880,7 @@ static struct resource ceu0_resources[] = {
756 .flags = IORESOURCE_MEM, 880 .flags = IORESOURCE_MEM,
757 }, 881 },
758 [1] = { 882 [1] = {
759 .start = intcs_evt2irq(0x0500), 883 .start = gic_spi(160),
760 .flags = IORESOURCE_IRQ, 884 .flags = IORESOURCE_IRQ,
761 }, 885 },
762 [2] = { 886 [2] = {
@@ -798,7 +922,7 @@ static struct resource fsi_resources[] = {
798 .flags = IORESOURCE_MEM, 922 .flags = IORESOURCE_MEM,
799 }, 923 },
800 [1] = { 924 [1] = {
801 .start = evt2irq(0x1840), 925 .start = gic_spi(9),
802 .flags = IORESOURCE_IRQ, 926 .flags = IORESOURCE_IRQ,
803 }, 927 },
804}; 928};
@@ -864,8 +988,8 @@ static struct platform_device fsi_hdmi_device = {
864 988
865/* RTC: RTC connects i2c-gpio. */ 989/* RTC: RTC connects i2c-gpio. */
866static struct i2c_gpio_platform_data i2c_gpio_data = { 990static struct i2c_gpio_platform_data i2c_gpio_data = {
867 .sda_pin = GPIO_PORT208, 991 .sda_pin = 208,
868 .scl_pin = GPIO_PORT91, 992 .scl_pin = 91,
869 .udelay = 5, /* 100 kHz */ 993 .udelay = 5, /* 100 kHz */
870}; 994};
871 995
@@ -878,10 +1002,15 @@ static struct platform_device i2c_gpio_device = {
878}; 1002};
879 1003
880/* I2C */ 1004/* I2C */
1005static struct st1232_pdata st1232_i2c0_pdata = {
1006 .reset_gpio = 166,
1007};
1008
881static struct i2c_board_info i2c0_devices[] = { 1009static struct i2c_board_info i2c0_devices[] = {
882 { 1010 {
883 I2C_BOARD_INFO("st1232-ts", 0x55), 1011 I2C_BOARD_INFO("st1232-ts", 0x55),
884 .irq = evt2irq(0x0340), 1012 .irq = irq_pin(10),
1013 .platform_data = &st1232_i2c0_pdata,
885 }, 1014 },
886 { 1015 {
887 I2C_BOARD_INFO("wm8978", 0x1a), 1016 I2C_BOARD_INFO("wm8978", 0x1a),
@@ -902,6 +1031,8 @@ static struct platform_device *eva_devices[] __initdata = {
902 &lcdc0_device, 1031 &lcdc0_device,
903 &gpio_keys_device, 1032 &gpio_keys_device,
904 &sh_eth_device, 1033 &sh_eth_device,
1034 &vcc_sdhi0,
1035 &vccq_sdhi0,
905 &sdhi0_device, 1036 &sdhi0_device,
906 &sh_mmcif_device, 1037 &sh_mmcif_device,
907 &hdmi_device, 1038 &hdmi_device,
@@ -914,6 +1045,28 @@ static struct platform_device *eva_devices[] __initdata = {
914 &i2c_gpio_device, 1045 &i2c_gpio_device,
915}; 1046};
916 1047
1048static const struct pinctrl_map eva_pinctrl_map[] = {
1049 /* LCD0 */
1050 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
1051 "lcd0_data24_0", "lcd0"),
1052 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
1053 "lcd0_lclk_1", "lcd0"),
1054 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
1055 "lcd0_sync", "lcd0"),
1056 /* MMCIF */
1057 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
1058 "mmc0_data8_1", "mmc0"),
1059 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
1060 "mmc0_ctrl_1", "mmc0"),
1061 /* SDHI0 */
1062 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
1063 "sdhi0_data4", "sdhi0"),
1064 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
1065 "sdhi0_ctrl", "sdhi0"),
1066 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
1067 "sdhi0_wp", "sdhi0"),
1068};
1069
917static void __init eva_clock_init(void) 1070static void __init eva_clock_init(void)
918{ 1071{
919 struct clk *system = clk_get(NULL, "system_clk"); 1072 struct clk *system = clk_get(NULL, "system_clk");
@@ -961,6 +1114,8 @@ static void __init eva_init(void)
961 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 1114 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
962 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 1115 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
963 1116
1117 pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
1118
964 r8a7740_pinmux_init(); 1119 r8a7740_pinmux_init();
965 r8a7740_meram_workaround(); 1120 r8a7740_meram_workaround();
966 1121
@@ -970,42 +1125,12 @@ static void __init eva_init(void)
970 1125
971 /* LCDC0 */ 1126 /* LCDC0 */
972 gpio_request(GPIO_FN_LCDC0_SELECT, NULL); 1127 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
973 gpio_request(GPIO_FN_LCD0_D0, NULL); 1128
974 gpio_request(GPIO_FN_LCD0_D1, NULL); 1129 gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
975 gpio_request(GPIO_FN_LCD0_D2, NULL); 1130 gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
976 gpio_request(GPIO_FN_LCD0_D3, NULL);
977 gpio_request(GPIO_FN_LCD0_D4, NULL);
978 gpio_request(GPIO_FN_LCD0_D5, NULL);
979 gpio_request(GPIO_FN_LCD0_D6, NULL);
980 gpio_request(GPIO_FN_LCD0_D7, NULL);
981 gpio_request(GPIO_FN_LCD0_D8, NULL);
982 gpio_request(GPIO_FN_LCD0_D9, NULL);
983 gpio_request(GPIO_FN_LCD0_D10, NULL);
984 gpio_request(GPIO_FN_LCD0_D11, NULL);
985 gpio_request(GPIO_FN_LCD0_D12, NULL);
986 gpio_request(GPIO_FN_LCD0_D13, NULL);
987 gpio_request(GPIO_FN_LCD0_D14, NULL);
988 gpio_request(GPIO_FN_LCD0_D15, NULL);
989 gpio_request(GPIO_FN_LCD0_D16, NULL);
990 gpio_request(GPIO_FN_LCD0_D17, NULL);
991 gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
992 gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
993 gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
994 gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
995 gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
996 gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
997 gpio_request(GPIO_FN_LCD0_DCK, NULL);
998 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
999 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
1000 gpio_request(GPIO_FN_LCD0_DISP, NULL);
1001 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
1002
1003 gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1004 gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
1005 1131
1006 /* Touchscreen */ 1132 /* Touchscreen */
1007 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ 1133 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
1008 gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
1009 1134
1010 /* GETHER */ 1135 /* GETHER */
1011 gpio_request(GPIO_FN_ET_CRS, NULL); 1136 gpio_request(GPIO_FN_ET_CRS, NULL);
@@ -1028,12 +1153,12 @@ static void __init eva_init(void)
1028 gpio_request(GPIO_FN_ET_RX_DV, NULL); 1153 gpio_request(GPIO_FN_ET_RX_DV, NULL);
1029 gpio_request(GPIO_FN_ET_RX_CLK, NULL); 1154 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
1030 1155
1031 gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ 1156 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
1032 1157
1033 /* USB */ 1158 /* USB */
1034 gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ 1159 gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
1035 1160
1036 if (gpio_get_value(GPIO_PORT159)) { 1161 if (gpio_get_value(159)) {
1037 /* USB Host */ 1162 /* USB Host */
1038 } else { 1163 } else {
1039 /* USB Func */ 1164 /* USB Func */
@@ -1042,47 +1167,15 @@ static void __init eva_init(void)
1042 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide 1167 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
1043 * USB connection/disconnection (usbhsf_get_vbus()). 1168 * USB connection/disconnection (usbhsf_get_vbus()).
1044 * This means we needs to select GPIO_FN_IRQ7_PORT209 first, 1169 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
1045 * and select GPIO_PORT209 here 1170 * and select GPIO 209 here
1046 */ 1171 */
1047 gpio_request(GPIO_FN_IRQ7_PORT209, NULL); 1172 gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
1048 gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL); 1173 gpio_request_one(209, GPIOF_IN, NULL);
1049 1174
1050 platform_device_register(&usbhsf_device); 1175 platform_device_register(&usbhsf_device);
1051 usb = &usbhsf_device; 1176 usb = &usbhsf_device;
1052 } 1177 }
1053 1178
1054 /* SDHI0 */
1055 gpio_request(GPIO_FN_SDHI0_CMD, NULL);
1056 gpio_request(GPIO_FN_SDHI0_CLK, NULL);
1057 gpio_request(GPIO_FN_SDHI0_D0, NULL);
1058 gpio_request(GPIO_FN_SDHI0_D1, NULL);
1059 gpio_request(GPIO_FN_SDHI0_D2, NULL);
1060 gpio_request(GPIO_FN_SDHI0_D3, NULL);
1061 gpio_request(GPIO_FN_SDHI0_WP, NULL);
1062
1063 gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
1064 gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
1065 gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
1066
1067 /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
1068
1069 /*
1070 * MMCIF
1071 *
1072 * Here doesn't care SW1.4 status,
1073 * since CON2 is not mounted.
1074 */
1075 gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
1076 gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
1077 gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
1078 gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
1079 gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
1080 gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
1081 gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
1082 gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
1083 gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
1084 gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
1085
1086 /* CEU0 */ 1179 /* CEU0 */
1087 gpio_request(GPIO_FN_VIO0_D7, NULL); 1180 gpio_request(GPIO_FN_VIO0_D7, NULL);
1088 gpio_request(GPIO_FN_VIO0_D6, NULL); 1181 gpio_request(GPIO_FN_VIO0_D6, NULL);
@@ -1099,10 +1192,10 @@ static void __init eva_init(void)
1099 gpio_request(GPIO_FN_VIO_CKO, NULL); 1192 gpio_request(GPIO_FN_VIO_CKO, NULL);
1100 1193
1101 /* CON1/CON15 Camera */ 1194 /* CON1/CON15 Camera */
1102 gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ 1195 gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
1103 gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ 1196 gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
1104 /* see mt9t111_power() */ 1197 /* see mt9t111_power() */
1105 gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ 1198 gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
1106 1199
1107 /* FSI-WM8978 */ 1200 /* FSI-WM8978 */
1108 gpio_request(GPIO_FN_FSIAIBT, NULL); 1201 gpio_request(GPIO_FN_FSIAIBT, NULL);
@@ -1111,8 +1204,8 @@ static void __init eva_init(void)
1111 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1204 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1112 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); 1205 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
1113 1206
1114 gpio_request(GPIO_PORT7, NULL); 1207 gpio_request(7, NULL);
1115 gpio_request(GPIO_PORT8, NULL); 1208 gpio_request(8, NULL);
1116 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ 1209 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
1117 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ 1210 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
1118 1211
@@ -1129,29 +1222,21 @@ static void __init eva_init(void)
1129 * DBGMD/LCDC0/FSIA MUX 1222 * DBGMD/LCDC0/FSIA MUX
1130 * DBGMD_SELECT_B should be set after setting PFC Function. 1223 * DBGMD_SELECT_B should be set after setting PFC Function.
1131 */ 1224 */
1132 gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL); 1225 gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
1133 1226
1134 /* 1227 /*
1135 * We can switch CON8/CON14 by SW1.5, 1228 * We can switch CON8/CON14 by SW1.5,
1136 * but it needs after DBGMD_SELECT_B 1229 * but it needs after DBGMD_SELECT_B
1137 */ 1230 */
1138 gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL); 1231 gpio_request_one(6, GPIOF_IN, NULL);
1139 if (gpio_get_value(GPIO_PORT6)) { 1232 if (gpio_get_value(6)) {
1140 /* CON14 enable */ 1233 /* CON14 enable */
1141 } else { 1234 } else {
1142 /* CON8 (SDHI1) enable */ 1235 /* CON8 (SDHI1) enable */
1143 gpio_request(GPIO_FN_SDHI1_CLK, NULL); 1236 pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
1144 gpio_request(GPIO_FN_SDHI1_CMD, NULL); 1237 ARRAY_SIZE(eva_sdhi1_pinctrl_map));
1145 gpio_request(GPIO_FN_SDHI1_D0, NULL);
1146 gpio_request(GPIO_FN_SDHI1_D1, NULL);
1147 gpio_request(GPIO_FN_SDHI1_D2, NULL);
1148 gpio_request(GPIO_FN_SDHI1_D3, NULL);
1149 gpio_request(GPIO_FN_SDHI1_CD, NULL);
1150 gpio_request(GPIO_FN_SDHI1_WP, NULL);
1151
1152 /* SDSLOT2_PON */
1153 gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
1154 1238
1239 platform_device_register(&vcc_sdhi1);
1155 platform_device_register(&sdhi1_device); 1240 platform_device_register(&sdhi1_device);
1156 } 1241 }
1157 1242
@@ -1207,7 +1292,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1207 .map_io = r8a7740_map_io, 1292 .map_io = r8a7740_map_io,
1208 .init_early = eva_add_early_devices, 1293 .init_early = eva_add_early_devices,
1209 .init_irq = r8a7740_init_irq, 1294 .init_irq = r8a7740_init_irq,
1210 .handle_irq = shmobile_handle_irq_intc,
1211 .init_machine = eva_init, 1295 .init_machine = eva_init,
1212 .init_late = shmobile_init_late, 1296 .init_late = shmobile_init_late,
1213 .init_time = eva_earlytimer_init, 1297 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
new file mode 100644
index 000000000000..38e5e50fb318
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -0,0 +1,81 @@
1/*
2 * Bock-W board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/smsc911x.h>
23#include <mach/common.h>
24#include <mach/irqs.h>
25#include <mach/r8a7778.h>
26#include <asm/mach/arch.h>
27
28static struct smsc911x_platform_config smsc911x_data = {
29 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
30 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
31 .flags = SMSC911X_USE_32BIT,
32 .phy_interface = PHY_INTERFACE_MODE_MII,
33};
34
35static struct resource smsc911x_resources[] = {
36 DEFINE_RES_MEM(0x18300000, 0x1000),
37 DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
38};
39
40#define IRQ0MR 0x30
41static void __init bockw_init(void)
42{
43 void __iomem *fpga;
44
45 r8a7778_clock_init();
46 r8a7778_init_irq_extpin(1);
47 r8a7778_add_standard_devices();
48
49 fpga = ioremap_nocache(0x18200000, SZ_1M);
50 if (fpga) {
51 /*
52 * CAUTION
53 *
54 * IRQ0/1 is cascaded interrupt from FPGA.
55 * it should be cared in the future
56 * Now, it is assuming IRQ0 was used only from SMSC.
57 */
58 u16 val = ioread16(fpga + IRQ0MR);
59 val &= ~(1 << 4); /* enable SMSC911x */
60 iowrite16(val, fpga + IRQ0MR);
61 iounmap(fpga);
62
63 platform_device_register_resndata(
64 &platform_bus, "smsc911x", -1,
65 smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
66 &smsc911x_data, sizeof(smsc911x_data));
67 }
68}
69
70static const char *bockw_boards_compat_dt[] __initdata = {
71 "renesas,bockw",
72 NULL,
73};
74
75DT_MACHINE_START(BOCKW_DT, "bockw")
76 .init_early = r8a7778_init_delay,
77 .init_irq = r8a7778_init_irq_dt,
78 .init_machine = bockw_init,
79 .init_time = shmobile_timer_init,
80 .dt_compat = bockw_boards_compat_dt,
81MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f86691539..70d992c540ae 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
27#include <linux/platform_device.h> 28#include <linux/platform_device.h>
28#include <linux/gpio.h> 29#include <linux/gpio.h>
29#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
288 }, 289 },
289}; 290};
290 291
292static const struct pinctrl_map lcdc0_pinctrl_map[] = {
293 /* LCD0 */
294 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
295 "lcd0_data24_1", "lcd0"),
296 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
297 "lcd0_lclk_1", "lcd0"),
298 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
299 "lcd0_sync", "lcd0"),
300};
301
291/* 302/*
292 * SMSC 9221 303 * SMSC 9221
293 */ 304 */
@@ -392,8 +403,8 @@ static void __init bonito_init(void)
392 /* 403 /*
393 * base board settings 404 * base board settings
394 */ 405 */
395 gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL); 406 gpio_request_one(176, GPIOF_IN, NULL);
396 if (!gpio_get_value(GPIO_PORT176)) { 407 if (!gpio_get_value(176)) {
397 u16 bsw2; 408 u16 bsw2;
398 u16 bsw3; 409 u16 bsw3;
399 u16 bsw4; 410 u16 bsw4;
@@ -430,38 +441,11 @@ static void __init bonito_init(void)
430 */ 441 */
431 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ 442 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
432 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ 443 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
433 gpio_request(GPIO_FN_LCDC0_SELECT, NULL); 444 pinctrl_register_mappings(lcdc0_pinctrl_map,
434 gpio_request(GPIO_FN_LCD0_D0, NULL); 445 ARRAY_SIZE(lcdc0_pinctrl_map));
435 gpio_request(GPIO_FN_LCD0_D1, NULL); 446 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
436 gpio_request(GPIO_FN_LCD0_D2, NULL); 447
437 gpio_request(GPIO_FN_LCD0_D3, NULL); 448 gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
438 gpio_request(GPIO_FN_LCD0_D4, NULL);
439 gpio_request(GPIO_FN_LCD0_D5, NULL);
440 gpio_request(GPIO_FN_LCD0_D6, NULL);
441 gpio_request(GPIO_FN_LCD0_D7, NULL);
442 gpio_request(GPIO_FN_LCD0_D8, NULL);
443 gpio_request(GPIO_FN_LCD0_D9, NULL);
444 gpio_request(GPIO_FN_LCD0_D10, NULL);
445 gpio_request(GPIO_FN_LCD0_D11, NULL);
446 gpio_request(GPIO_FN_LCD0_D12, NULL);
447 gpio_request(GPIO_FN_LCD0_D13, NULL);
448 gpio_request(GPIO_FN_LCD0_D14, NULL);
449 gpio_request(GPIO_FN_LCD0_D15, NULL);
450 gpio_request(GPIO_FN_LCD0_D16, NULL);
451 gpio_request(GPIO_FN_LCD0_D17, NULL);
452 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
453 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
454 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
455 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
456 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
457 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
458 gpio_request(GPIO_FN_LCD0_DCK, NULL);
459 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
460 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
461 gpio_request(GPIO_FN_LCD0_DISP, NULL);
462 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
463
464 gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
465 NULL); /* LCDDON */ 449 NULL); /* LCDDON */
466 450
467 /* backlight on */ 451 /* backlight on */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860403ef..ef5ca0ef0cb5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,8 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/platform_device.h> 29#include <linux/platform_device.h>
28#include <linux/delay.h> 30#include <linux/delay.h>
29#include <linux/io.h> 31#include <linux/io.h>
@@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
135#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } 137#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
136 138
137static struct gpio_keys_button gpio_buttons[] = { 139static struct gpio_keys_button gpio_buttons[] = {
138 GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */ 140 GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
139 GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */ 141 GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
140 GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */ 142 GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
141 GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */ 143 GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
142 GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */ 144 GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
143 GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */ 145 GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
144 GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */ 146 GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
145 GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */ 147 GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
146 /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */ 148 /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
147 GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */ 149 GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
148 /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */ 150 /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
149}; 151};
150 152
151static struct gpio_keys_platform_data gpio_key_info = { 153static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
165#define GPIO_LED(n, g) { .name = n, .gpio = g } 167#define GPIO_LED(n, g) { .name = n, .gpio = g }
166 168
167static struct gpio_led gpio_leds[] = { 169static struct gpio_led gpio_leds[] = {
168 GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */ 170 GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
169 GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */ 171 GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
170 GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */ 172 GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
171}; 173};
172 174
173static struct gpio_led_platform_data gpio_leds_info = { 175static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
187static struct led_renesas_tpu_config led_renesas_tpu12_pdata = { 189static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
188 .name = "V2513", 190 .name = "V2513",
189 .pin_gpio_fn = GPIO_FN_TPU1TO2, 191 .pin_gpio_fn = GPIO_FN_TPU1TO2,
190 .pin_gpio = GPIO_PORT153, 192 .pin_gpio = 153,
191 .channel_offset = 0x90, 193 .channel_offset = 0x90,
192 .timer_bit = 2, 194 .timer_bit = 2,
193 .max_brightness = 1000, 195 .max_brightness = 1000,
@@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
215static struct led_renesas_tpu_config led_renesas_tpu41_pdata = { 217static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
216 .name = "V2514", 218 .name = "V2514",
217 .pin_gpio_fn = GPIO_FN_TPU4TO1, 219 .pin_gpio_fn = GPIO_FN_TPU4TO1,
218 .pin_gpio = GPIO_PORT199, 220 .pin_gpio = 199,
219 .channel_offset = 0x50, 221 .channel_offset = 0x50,
220 .timer_bit = 1, 222 .timer_bit = 1,
221 .max_brightness = 1000, 223 .max_brightness = 1000,
@@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
243static struct led_renesas_tpu_config led_renesas_tpu21_pdata = { 245static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
244 .name = "V2515", 246 .name = "V2515",
245 .pin_gpio_fn = GPIO_FN_TPU2TO1, 247 .pin_gpio_fn = GPIO_FN_TPU2TO1,
246 .pin_gpio = GPIO_PORT197, 248 .pin_gpio = 197,
247 .channel_offset = 0x50, 249 .channel_offset = 0x50,
248 .timer_bit = 1, 250 .timer_bit = 1,
249 .max_brightness = 1000, 251 .max_brightness = 1000,
@@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
271static struct led_renesas_tpu_config led_renesas_tpu30_pdata = { 273static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
272 .name = "KEYLED", 274 .name = "KEYLED",
273 .pin_gpio_fn = GPIO_FN_TPU3TO0, 275 .pin_gpio_fn = GPIO_FN_TPU3TO0,
274 .pin_gpio = GPIO_PORT163, 276 .pin_gpio = 163,
275 .channel_offset = 0x10, 277 .channel_offset = 0x10,
276 .timer_bit = 0, 278 .timer_bit = 0,
277 .max_brightness = 1000, 279 .max_brightness = 1000,
@@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
433 &sdhi1_device, 435 &sdhi1_device,
434}; 436};
435 437
438static unsigned long pin_pullup_conf[] = {
439 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
440};
441
442static const struct pinctrl_map kota2_pinctrl_map[] = {
443 /* KEYSC */
444 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
445 "keysc_in8", "keysc"),
446 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
447 "keysc_out04", "keysc"),
448 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
449 "keysc_out5", "keysc"),
450 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
451 "keysc_out6_0", "keysc"),
452 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
453 "keysc_out7_0", "keysc"),
454 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
455 "keysc_out8_0", "keysc"),
456 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
457 "keysc_in8", pin_pullup_conf),
458 /* MMCIF */
459 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
460 "mmc0_data8_0", "mmc0"),
461 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
462 "mmc0_ctrl_0", "mmc0"),
463 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
464 "PORT279", pin_pullup_conf),
465 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
466 "mmc0_data8_0", pin_pullup_conf),
467 /* SCIFA2 (UART2) */
468 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
469 "scifa2_data_0", "scifa2"),
470 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
471 "scifa2_ctrl_0", "scifa2"),
472 /* SCIFA4 (UART1) */
473 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
474 "scifa4_data", "scifa4"),
475 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
476 "scifa4_ctrl", "scifa4"),
477 /* SCIFB (BT) */
478 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
479 "scifb_data_0", "scifb"),
480 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
481 "scifb_clk_0", "scifb"),
482 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
483 "scifb_ctrl_0", "scifb"),
484 /* SDHI0 (microSD) */
485 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
486 "sdhi0_data4", "sdhi0"),
487 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
488 "sdhi0_ctrl", "sdhi0"),
489 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
490 "sdhi0_cd", "sdhi0"),
491 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
492 "sdhi0_data4", pin_pullup_conf),
493 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
494 "PORT256", pin_pullup_conf),
495 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
496 "PORT251", pin_pullup_conf),
497 /* SDHI1 (BCM4330) */
498 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
499 "sdhi1_data4", "sdhi1"),
500 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
501 "sdhi1_ctrl", "sdhi1"),
502 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
503 "sdhi1_data4", pin_pullup_conf),
504 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
505 "PORT263", pin_pullup_conf),
506 /* SMSC911X */
507 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
508 "bsc_data_0_7", "bsc"),
509 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
510 "bsc_data_8_15", "bsc"),
511 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
512 "bsc_cs5_a", "bsc"),
513 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
514 "bsc_we0", "bsc"),
515};
516
436static void __init kota2_init(void) 517static void __init kota2_init(void)
437{ 518{
438 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, 519 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,97 +522,16 @@ static void __init kota2_init(void)
441 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 522 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
442 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 523 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
443 524
525 pinctrl_register_mappings(kota2_pinctrl_map,
526 ARRAY_SIZE(kota2_pinctrl_map));
444 sh73a0_pinmux_init(); 527 sh73a0_pinmux_init();
445 528
446 /* SCIFA2 (UART2) */
447 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
448 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
449 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
450 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
451
452 /* SCIFA4 (UART1) */
453 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
454 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
455 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
456 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
457
458 /* SMSC911X */ 529 /* SMSC911X */
459 gpio_request(GPIO_FN_D0_NAF0, NULL); 530 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
460 gpio_request(GPIO_FN_D1_NAF1, NULL); 531 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
461 gpio_request(GPIO_FN_D2_NAF2, NULL);
462 gpio_request(GPIO_FN_D3_NAF3, NULL);
463 gpio_request(GPIO_FN_D4_NAF4, NULL);
464 gpio_request(GPIO_FN_D5_NAF5, NULL);
465 gpio_request(GPIO_FN_D6_NAF6, NULL);
466 gpio_request(GPIO_FN_D7_NAF7, NULL);
467 gpio_request(GPIO_FN_D8_NAF8, NULL);
468 gpio_request(GPIO_FN_D9_NAF9, NULL);
469 gpio_request(GPIO_FN_D10_NAF10, NULL);
470 gpio_request(GPIO_FN_D11_NAF11, NULL);
471 gpio_request(GPIO_FN_D12_NAF12, NULL);
472 gpio_request(GPIO_FN_D13_NAF13, NULL);
473 gpio_request(GPIO_FN_D14_NAF14, NULL);
474 gpio_request(GPIO_FN_D15_NAF15, NULL);
475 gpio_request(GPIO_FN_CS5A_, NULL);
476 gpio_request(GPIO_FN_WE0__FWE, NULL);
477 gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
478 gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
479
480 /* KEYSC */
481 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
482 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
483 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
484 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
485 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
486 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
487 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
488 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
489 gpio_request(GPIO_FN_KEYOUT0, NULL);
490 gpio_request(GPIO_FN_KEYOUT1, NULL);
491 gpio_request(GPIO_FN_KEYOUT2, NULL);
492 gpio_request(GPIO_FN_KEYOUT3, NULL);
493 gpio_request(GPIO_FN_KEYOUT4, NULL);
494 gpio_request(GPIO_FN_KEYOUT5, NULL);
495 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
496 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
497 gpio_request(GPIO_FN_KEYOUT8, NULL);
498 532
499 /* MMCIF */ 533 /* MMCIF */
500 gpio_request(GPIO_FN_MMCCLK0, NULL); 534 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
501 gpio_request(GPIO_FN_MMCD0_0, NULL);
502 gpio_request(GPIO_FN_MMCD0_1, NULL);
503 gpio_request(GPIO_FN_MMCD0_2, NULL);
504 gpio_request(GPIO_FN_MMCD0_3, NULL);
505 gpio_request(GPIO_FN_MMCD0_4, NULL);
506 gpio_request(GPIO_FN_MMCD0_5, NULL);
507 gpio_request(GPIO_FN_MMCD0_6, NULL);
508 gpio_request(GPIO_FN_MMCD0_7, NULL);
509 gpio_request(GPIO_FN_MMCCMD0, NULL);
510 gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
511
512 /* SDHI0 (microSD) */
513 gpio_request(GPIO_FN_SDHICD0_PU, NULL);
514 gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
515 gpio_request(GPIO_FN_SDHICLK0, NULL);
516 gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
517 gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
518 gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
519 gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
520
521 /* SCIFB (BT) */
522 gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
523 gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
524 gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
525 gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
526 gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
527
528 /* SDHI1 (BCM4330) */
529 gpio_request(GPIO_FN_SDHICLK1, NULL);
530 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
531 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
532 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
533 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
534 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
535 535
536#ifdef CONFIG_CACHE_L2X0 536#ifdef CONFIG_CACHE_L2X0
537 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ 537 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
new file mode 100644
index 000000000000..aefa50d385b7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -0,0 +1,107 @@
1/*
2 * KZM-A9-GT board support - Reference Device Tree Implementation
3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on board-kzm9g.c
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqchip.h>
28#include <linux/input.h>
29#include <linux/of_platform.h>
30#include <linux/pinctrl/machine.h>
31#include <linux/pinctrl/pinconf-generic.h>
32#include <mach/sh73a0.h>
33#include <mach/common.h>
34#include <asm/hardware/cache-l2x0.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37
38static unsigned long pin_pullup_conf[] = {
39 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
40};
41
42static const struct pinctrl_map kzm_pinctrl_map[] = {
43 PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
44 "i2c3_1", "i2c3"),
45 /* MMCIF */
46 PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
47 "mmc0_data8_0", "mmc0"),
48 PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
49 "mmc0_ctrl_0", "mmc0"),
50 PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
51 "PORT279", pin_pullup_conf),
52 PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
53 "mmc0_data8_0", pin_pullup_conf),
54 /* SCIFA4 */
55 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
56 "scifa4_data", "scifa4"),
57 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
58 "scifa4_ctrl", "scifa4"),
59 /* SDHI0 */
60 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
61 "sdhi0_data4", "sdhi0"),
62 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
63 "sdhi0_ctrl", "sdhi0"),
64 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
65 "sdhi0_cd", "sdhi0"),
66 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
67 "sdhi0_wp", "sdhi0"),
68 /* SDHI2 */
69 PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
70 "sdhi2_data4", "sdhi2"),
71 PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
72 "sdhi2_ctrl", "sdhi2"),
73};
74
75static void __init kzm_init(void)
76{
77 sh73a0_add_standard_devices_dt();
78 pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
79 sh73a0_pinmux_init();
80
81 /* enable SD */
82 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
83 gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
84
85 gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
86
87#ifdef CONFIG_CACHE_L2X0
88 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
89 l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
90#endif
91}
92
93static const char *kzm9g_boards_compat_dt[] __initdata = {
94 "renesas,kzm9g-reference",
95 NULL,
96};
97
98DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
99 .smp = smp_ops(sh73a0_smp_ops),
100 .map_io = sh73a0_map_io,
101 .init_early = sh73a0_init_delay,
102 .nr_irqs = NR_IRQS_LEGACY,
103 .init_irq = irqchip_init,
104 .init_machine = kzm_init,
105 .init_time = shmobile_timer_init,
106 .dt_compat = kzm9g_boards_compat_dt,
107MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index d34d12ae496b..e6b775a10aad 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,8 @@
30#include <linux/mmc/sh_mmcif.h> 30#include <linux/mmc/sh_mmcif.h>
31#include <linux/mmc/sh_mobile_sdhi.h> 31#include <linux/mmc/sh_mobile_sdhi.h>
32#include <linux/mfd/tmio.h> 32#include <linux/mfd/tmio.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf-generic.h>
33#include <linux/platform_device.h> 35#include <linux/platform_device.h>
34#include <linux/regulator/fixed.h> 36#include <linux/regulator/fixed.h>
35#include <linux/regulator/machine.h> 37#include <linux/regulator/machine.h>
@@ -61,8 +63,8 @@
61 63
62/* Dummy supplies, where voltage doesn't matter */ 64/* Dummy supplies, where voltage doesn't matter */
63static struct regulator_consumer_supply dummy_supplies[] = { 65static struct regulator_consumer_supply dummy_supplies[] = {
64 REGULATOR_SUPPLY("vddvario", "smsc911x"), 66 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
65 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 67 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
66}; 68};
67 69
68/* 70/*
@@ -155,12 +157,14 @@ static int usbhs_get_vbus(struct platform_device *pdev)
155 return !((1 << 7) & __raw_readw(priv->cr2)); 157 return !((1 << 7) & __raw_readw(priv->cr2));
156} 158}
157 159
158static void usbhs_phy_reset(struct platform_device *pdev) 160static int usbhs_phy_reset(struct platform_device *pdev)
159{ 161{
160 struct usbhs_private *priv = usbhs_get_priv(pdev); 162 struct usbhs_private *priv = usbhs_get_priv(pdev);
161 163
162 /* init phy */ 164 /* init phy */
163 __raw_writew(0x8a0a, priv->cr2); 165 __raw_writew(0x8a0a, priv->cr2);
166
167 return 0;
164} 168}
165 169
166static int usbhs_get_id(struct platform_device *pdev) 170static int usbhs_get_id(struct platform_device *pdev)
@@ -202,7 +206,7 @@ static int usbhs_hardware_init(struct platform_device *pdev)
202 return 0; 206 return 0;
203} 207}
204 208
205static void usbhs_hardware_exit(struct platform_device *pdev) 209static int usbhs_hardware_exit(struct platform_device *pdev)
206{ 210{
207 struct usbhs_private *priv = usbhs_get_priv(pdev); 211 struct usbhs_private *priv = usbhs_get_priv(pdev);
208 212
@@ -210,6 +214,8 @@ static void usbhs_hardware_exit(struct platform_device *pdev)
210 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy); 214 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
211 215
212 free_irq(IRQ15, pdev); 216 free_irq(IRQ15, pdev);
217
218 return 0;
213} 219}
214 220
215static u32 usbhs_pipe_cfg[] = { 221static u32 usbhs_pipe_cfg[] = {
@@ -373,13 +379,64 @@ static struct platform_device mmc_device = {
373 .resource = sh_mmcif_resources, 379 .resource = sh_mmcif_resources,
374}; 380};
375 381
376/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */ 382/* Fixed 3.3V regulators to be used by SDHI0 */
377static struct regulator_consumer_supply fixed2v8_power_consumers[] = 383static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
378{ 384{
379 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), 385 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
380 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), 386};
387
388static struct regulator_init_data vcc_sdhi0_init_data = {
389 .constraints = {
390 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
391 },
392 .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
393 .consumer_supplies = vcc_sdhi0_consumers,
394};
395
396static struct fixed_voltage_config vcc_sdhi0_info = {
397 .supply_name = "SDHI0 Vcc",
398 .microvolts = 3300000,
399 .gpio = 15,
400 .enable_high = 1,
401 .init_data = &vcc_sdhi0_init_data,
402};
403
404static struct platform_device vcc_sdhi0 = {
405 .name = "reg-fixed-voltage",
406 .id = 0,
407 .dev = {
408 .platform_data = &vcc_sdhi0_info,
409 },
410};
411
412/* Fixed 3.3V regulators to be used by SDHI2 */
413static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
414{
381 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"), 415 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
382 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"), 416};
417
418static struct regulator_init_data vcc_sdhi2_init_data = {
419 .constraints = {
420 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
421 },
422 .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers),
423 .consumer_supplies = vcc_sdhi2_consumers,
424};
425
426static struct fixed_voltage_config vcc_sdhi2_info = {
427 .supply_name = "SDHI2 Vcc",
428 .microvolts = 3300000,
429 .gpio = 14,
430 .enable_high = 1,
431 .init_data = &vcc_sdhi2_init_data,
432};
433
434static struct platform_device vcc_sdhi2 = {
435 .name = "reg-fixed-voltage",
436 .id = 1,
437 .dev = {
438 .platform_data = &vcc_sdhi2_info,
439 },
383}; 440};
384 441
385/* SDHI */ 442/* SDHI */
@@ -387,8 +444,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
387 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 444 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
388 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 445 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
389 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 446 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
390 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 447 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
391 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 448 MMC_CAP_POWER_OFF_CARD,
392}; 449};
393 450
394static struct resource sdhi0_resources[] = { 451static struct resource sdhi0_resources[] = {
@@ -431,9 +488,8 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
431 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | 488 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
432 TMIO_MMC_USE_GPIO_CD | 489 TMIO_MMC_USE_GPIO_CD |
433 TMIO_MMC_WRPROTECT_DISABLE, 490 TMIO_MMC_WRPROTECT_DISABLE,
434 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 491 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
435 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 492 .cd_gpio = 13,
436 .cd_gpio = GPIO_PORT13,
437}; 493};
438 494
439static struct resource sdhi2_resources[] = { 495static struct resource sdhi2_resources[] = {
@@ -592,6 +648,8 @@ static struct platform_device *kzm_devices[] __initdata = {
592 &usbhs_device, 648 &usbhs_device,
593 &lcdc_device, 649 &lcdc_device,
594 &mmc_device, 650 &mmc_device,
651 &vcc_sdhi0,
652 &vcc_sdhi2,
595 &sdhi0_device, 653 &sdhi0_device,
596 &sdhi2_device, 654 &sdhi2_device,
597 &gpio_keys_device, 655 &gpio_keys_device,
@@ -599,6 +657,64 @@ static struct platform_device *kzm_devices[] __initdata = {
599 &fsi_ak4648_device, 657 &fsi_ak4648_device,
600}; 658};
601 659
660static unsigned long pin_pullup_conf[] = {
661 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
662};
663
664static const struct pinctrl_map kzm_pinctrl_map[] = {
665 /* FSIA (AK4648) */
666 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
667 "fsia_mclk_in", "fsia"),
668 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
669 "fsia_sclk_in", "fsia"),
670 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
671 "fsia_data_in", "fsia"),
672 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
673 "fsia_data_out", "fsia"),
674 /* I2C3 */
675 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
676 "i2c3_1", "i2c3"),
677 /* LCD */
678 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
679 "lcd_data24", "lcd"),
680 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
681 "lcd_sync", "lcd"),
682 /* MMCIF */
683 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
684 "mmc0_data8_0", "mmc0"),
685 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
686 "mmc0_ctrl_0", "mmc0"),
687 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
688 "PORT279", pin_pullup_conf),
689 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
690 "mmc0_data8_0", pin_pullup_conf),
691 /* SCIFA4 */
692 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
693 "scifa4_data", "scifa4"),
694 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
695 "scifa4_ctrl", "scifa4"),
696 /* SDHI0 */
697 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
698 "sdhi0_data4", "sdhi0"),
699 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
700 "sdhi0_ctrl", "sdhi0"),
701 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
702 "sdhi0_cd", "sdhi0"),
703 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
704 "sdhi0_wp", "sdhi0"),
705 /* SDHI2 */
706 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
707 "sdhi2_data4", "sdhi2"),
708 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
709 "sdhi2_ctrl", "sdhi2"),
710 /* SMSC */
711 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
712 "bsc_cs4", "bsc"),
713 /* USB */
714 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
715 "usb_vbus", "usb"),
716};
717
602/* 718/*
603 * FIXME 719 * FIXME
604 * 720 *
@@ -654,106 +770,26 @@ device_initcall(as3711_enable_lcdc_backlight);
654 770
655static void __init kzm_init(void) 771static void __init kzm_init(void)
656{ 772{
657 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, 773 regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
658 ARRAY_SIZE(fixed1v8_power_consumers), 1800000); 774 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
659 regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers, 775 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
660 ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
661 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
662 776
663 sh73a0_pinmux_init(); 777 pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
664
665 /* enable SCIFA4 */
666 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
667 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
668 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
669 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
670 778
671 /* CS4 for SMSC/USB */ 779 sh73a0_pinmux_init();
672 gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
673 780
674 /* SMSC */ 781 /* SMSC */
675 gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */ 782 gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
676 783
677 /* LCDC */ 784 /* LCDC */
678 gpio_request(GPIO_FN_LCDD23, NULL); 785 gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
679 gpio_request(GPIO_FN_LCDD22, NULL); 786 gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
680 gpio_request(GPIO_FN_LCDD21, NULL);
681 gpio_request(GPIO_FN_LCDD20, NULL);
682 gpio_request(GPIO_FN_LCDD19, NULL);
683 gpio_request(GPIO_FN_LCDD18, NULL);
684 gpio_request(GPIO_FN_LCDD17, NULL);
685 gpio_request(GPIO_FN_LCDD16, NULL);
686 gpio_request(GPIO_FN_LCDD15, NULL);
687 gpio_request(GPIO_FN_LCDD14, NULL);
688 gpio_request(GPIO_FN_LCDD13, NULL);
689 gpio_request(GPIO_FN_LCDD12, NULL);
690 gpio_request(GPIO_FN_LCDD11, NULL);
691 gpio_request(GPIO_FN_LCDD10, NULL);
692 gpio_request(GPIO_FN_LCDD9, NULL);
693 gpio_request(GPIO_FN_LCDD8, NULL);
694 gpio_request(GPIO_FN_LCDD7, NULL);
695 gpio_request(GPIO_FN_LCDD6, NULL);
696 gpio_request(GPIO_FN_LCDD5, NULL);
697 gpio_request(GPIO_FN_LCDD4, NULL);
698 gpio_request(GPIO_FN_LCDD3, NULL);
699 gpio_request(GPIO_FN_LCDD2, NULL);
700 gpio_request(GPIO_FN_LCDD1, NULL);
701 gpio_request(GPIO_FN_LCDD0, NULL);
702 gpio_request(GPIO_FN_LCDDISP, NULL);
703 gpio_request(GPIO_FN_LCDDCK, NULL);
704
705 gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
706 gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
707 787
708 /* Touchscreen */ 788 /* Touchscreen */
709 gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */ 789 gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
710
711 /* enable MMCIF */
712 gpio_request(GPIO_FN_MMCCLK0, NULL);
713 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
714 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
715 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
716 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
717 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
718 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
719 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
720 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
721 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
722 790
723 /* enable SD */ 791 /* enable SD */
724 gpio_request(GPIO_FN_SDHIWP0, NULL);
725 gpio_request(GPIO_FN_SDHICD0, NULL);
726 gpio_request(GPIO_FN_SDHICMD0, NULL);
727 gpio_request(GPIO_FN_SDHICLK0, NULL);
728 gpio_request(GPIO_FN_SDHID0_3, NULL);
729 gpio_request(GPIO_FN_SDHID0_2, NULL);
730 gpio_request(GPIO_FN_SDHID0_1, NULL);
731 gpio_request(GPIO_FN_SDHID0_0, NULL);
732 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 792 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
733 gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
734
735 /* enable Micro SD */
736 gpio_request(GPIO_FN_SDHID2_0, NULL);
737 gpio_request(GPIO_FN_SDHID2_1, NULL);
738 gpio_request(GPIO_FN_SDHID2_2, NULL);
739 gpio_request(GPIO_FN_SDHID2_3, NULL);
740 gpio_request(GPIO_FN_SDHICMD2, NULL);
741 gpio_request(GPIO_FN_SDHICLK2, NULL);
742 gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
743
744 /* I2C 3 */
745 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
746 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
747
748 /* enable FSI2 port A (ak4648) */
749 gpio_request(GPIO_FN_FSIACK, NULL);
750 gpio_request(GPIO_FN_FSIAILR, NULL);
751 gpio_request(GPIO_FN_FSIAIBT, NULL);
752 gpio_request(GPIO_FN_FSIAISLD, NULL);
753 gpio_request(GPIO_FN_FSIAOSLD, NULL);
754
755 /* enable USB */
756 gpio_request(GPIO_FN_VBUS_0, NULL);
757 793
758#ifdef CONFIG_CACHE_L2X0 794#ifdef CONFIG_CACHE_L2X0
759 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ 795 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
new file mode 100644
index 000000000000..f587187a8603
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -0,0 +1,46 @@
1/*
2 * Lager board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/interrupt.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <mach/common.h>
26#include <mach/r8a7790.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29
30static void __init lager_add_standard_devices(void)
31{
32 r8a7790_clock_init();
33 r8a7790_add_standard_devices();
34}
35
36static const char *lager_boards_compat_dt[] __initdata = {
37 "renesas,lager",
38 NULL,
39};
40
41DT_MACHINE_START(LAGER_DT, "lager")
42 .init_irq = irqchip_init,
43 .init_time = r8a7790_timer_init,
44 .init_machine = lager_add_standard_devices,
45 .dt_compat = lager_boards_compat_dt,
46MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a585ff0..fa3407da682a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
40#include <linux/mtd/partitions.h> 40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h> 41#include <linux/mtd/physmap.h>
42#include <linux/mtd/sh_flctl.h> 42#include <linux/mtd/sh_flctl.h>
43#include <linux/pinctrl/machine.h>
43#include <linux/pm_clock.h> 44#include <linux/pm_clock.h>
44#include <linux/regulator/fixed.h> 45#include <linux/regulator/fixed.h>
45#include <linux/regulator/machine.h> 46#include <linux/regulator/machine.h>
@@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
363 364
364static int mackerel_set_brightness(int brightness) 365static int mackerel_set_brightness(int brightness)
365{ 366{
366 gpio_set_value(GPIO_PORT31, brightness); 367 gpio_set_value(31, brightness);
367 368
368 return 0; 369 return 0;
369} 370}
@@ -596,12 +597,14 @@ static int usbhs_get_vbus(struct platform_device *pdev)
596 return usbhs_is_connected(usbhs_get_priv(pdev)); 597 return usbhs_is_connected(usbhs_get_priv(pdev));
597} 598}
598 599
599static void usbhs_phy_reset(struct platform_device *pdev) 600static int usbhs_phy_reset(struct platform_device *pdev)
600{ 601{
601 struct usbhs_private *priv = usbhs_get_priv(pdev); 602 struct usbhs_private *priv = usbhs_get_priv(pdev);
602 603
603 /* init phy */ 604 /* init phy */
604 __raw_writew(0x8a0a, priv->usbcrcaddr); 605 __raw_writew(0x8a0a, priv->usbcrcaddr);
606
607 return 0;
605} 608}
606 609
607static int usbhs0_get_id(struct platform_device *pdev) 610static int usbhs0_get_id(struct platform_device *pdev)
@@ -628,11 +631,13 @@ static int usbhs0_hardware_init(struct platform_device *pdev)
628 return 0; 631 return 0;
629} 632}
630 633
631static void usbhs0_hardware_exit(struct platform_device *pdev) 634static int usbhs0_hardware_exit(struct platform_device *pdev)
632{ 635{
633 struct usbhs_private *priv = usbhs_get_priv(pdev); 636 struct usbhs_private *priv = usbhs_get_priv(pdev);
634 637
635 cancel_delayed_work_sync(&priv->work); 638 cancel_delayed_work_sync(&priv->work);
639
640 return 0;
636} 641}
637 642
638static struct usbhs_private usbhs0_private = { 643static struct usbhs_private usbhs0_private = {
@@ -735,7 +740,7 @@ static int usbhs1_hardware_init(struct platform_device *pdev)
735 return 0; 740 return 0;
736} 741}
737 742
738static void usbhs1_hardware_exit(struct platform_device *pdev) 743static int usbhs1_hardware_exit(struct platform_device *pdev)
739{ 744{
740 struct usbhs_private *priv = usbhs_get_priv(pdev); 745 struct usbhs_private *priv = usbhs_get_priv(pdev);
741 746
@@ -743,6 +748,8 @@ static void usbhs1_hardware_exit(struct platform_device *pdev)
743 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr); 748 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
744 749
745 free_irq(IRQ8, pdev); 750 free_irq(IRQ8, pdev);
751
752 return 0;
746} 753}
747 754
748static int usbhs1_get_id(struct platform_device *pdev) 755static int usbhs1_get_id(struct platform_device *pdev)
@@ -819,22 +826,22 @@ static struct platform_device usbhs1_device = {
819static struct gpio_led mackerel_leds[] = { 826static struct gpio_led mackerel_leds[] = {
820 { 827 {
821 .name = "led0", 828 .name = "led0",
822 .gpio = GPIO_PORT0, 829 .gpio = 0,
823 .default_state = LEDS_GPIO_DEFSTATE_ON, 830 .default_state = LEDS_GPIO_DEFSTATE_ON,
824 }, 831 },
825 { 832 {
826 .name = "led1", 833 .name = "led1",
827 .gpio = GPIO_PORT1, 834 .gpio = 1,
828 .default_state = LEDS_GPIO_DEFSTATE_ON, 835 .default_state = LEDS_GPIO_DEFSTATE_ON,
829 }, 836 },
830 { 837 {
831 .name = "led2", 838 .name = "led2",
832 .gpio = GPIO_PORT2, 839 .gpio = 2,
833 .default_state = LEDS_GPIO_DEFSTATE_ON, 840 .default_state = LEDS_GPIO_DEFSTATE_ON,
834 }, 841 },
835 { 842 {
836 .name = "led3", 843 .name = "led3",
837 .gpio = GPIO_PORT159, 844 .gpio = 159,
838 .default_state = LEDS_GPIO_DEFSTATE_ON, 845 .default_state = LEDS_GPIO_DEFSTATE_ON,
839 } 846 }
840}; 847};
@@ -962,40 +969,27 @@ static struct platform_device nand_flash_device = {
962 }, 969 },
963}; 970};
964 971
965/*
966 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
967 * connected to GPIO A22 of SH7372 (GPIO_PORT41).
968 */
969static int slot_cn7_get_cd(struct platform_device *pdev)
970{
971 return !gpio_get_value(GPIO_PORT41);
972}
973
974/* SDHI0 */ 972/* SDHI0 */
975static struct sh_mobile_sdhi_info sdhi0_info = { 973static struct sh_mobile_sdhi_info sdhi0_info = {
976 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 974 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
977 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 975 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
978 .tmio_flags = TMIO_MMC_USE_GPIO_CD, 976 .tmio_flags = TMIO_MMC_USE_GPIO_CD,
979 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, 977 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
980 .cd_gpio = GPIO_PORT172, 978 .cd_gpio = 172,
981}; 979};
982 980
983static struct resource sdhi0_resources[] = { 981static struct resource sdhi0_resources[] = {
984 [0] = { 982 {
985 .name = "SDHI0", 983 .name = "SDHI0",
986 .start = 0xe6850000, 984 .start = 0xe6850000,
987 .end = 0xe68500ff, 985 .end = 0xe68500ff,
988 .flags = IORESOURCE_MEM, 986 .flags = IORESOURCE_MEM,
989 }, 987 }, {
990 [1] = { 988 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
991 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
992 .flags = IORESOURCE_IRQ,
993 },
994 [2] = {
995 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, 989 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
996 .flags = IORESOURCE_IRQ, 990 .flags = IORESOURCE_IRQ,
997 }, 991 }, {
998 [3] = { 992 .name = SH_MOBILE_SDHI_IRQ_SDIO,
999 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, 993 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
1000 .flags = IORESOURCE_IRQ, 994 .flags = IORESOURCE_IRQ,
1001 }, 995 },
@@ -1011,36 +1005,30 @@ static struct platform_device sdhi0_device = {
1011 }, 1005 },
1012}; 1006};
1013 1007
1014#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1008#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1015/* SDHI1 */ 1009/* SDHI1 */
1010
1011/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
1016static struct sh_mobile_sdhi_info sdhi1_info = { 1012static struct sh_mobile_sdhi_info sdhi1_info = {
1017 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 1013 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
1018 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 1014 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
1019 .tmio_ocr_mask = MMC_VDD_165_195, 1015 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1020 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
1021 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 1016 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1022 MMC_CAP_NEEDS_POLL, 1017 MMC_CAP_NEEDS_POLL,
1023 .get_cd = slot_cn7_get_cd, 1018 .cd_gpio = 41,
1024}; 1019};
1025 1020
1026static struct resource sdhi1_resources[] = { 1021static struct resource sdhi1_resources[] = {
1027 [0] = { 1022 {
1028 .name = "SDHI1", 1023 .name = "SDHI1",
1029 .start = 0xe6860000, 1024 .start = 0xe6860000,
1030 .end = 0xe68600ff, 1025 .end = 0xe68600ff,
1031 .flags = IORESOURCE_MEM, 1026 .flags = IORESOURCE_MEM,
1032 }, 1027 }, {
1033 [1] = {
1034 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
1035 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
1036 .flags = IORESOURCE_IRQ,
1037 },
1038 [2] = {
1039 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 1028 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1040 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ 1029 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
1041 .flags = IORESOURCE_IRQ, 1030 .flags = IORESOURCE_IRQ,
1042 }, 1031 }, {
1043 [3] = {
1044 .name = SH_MOBILE_SDHI_IRQ_SDIO, 1032 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1045 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ 1033 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
1046 .flags = IORESOURCE_IRQ, 1034 .flags = IORESOURCE_IRQ,
@@ -1058,43 +1046,32 @@ static struct platform_device sdhi1_device = {
1058}; 1046};
1059#endif 1047#endif
1060 1048
1049/* SDHI2 */
1050
1061/* 1051/*
1062 * The card detect pin of the top SD/MMC slot (CN23) is active low and is 1052 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
1063 * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). 1053 * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
1064 */ 1054 */
1065static int slot_cn23_get_cd(struct platform_device *pdev)
1066{
1067 return !gpio_get_value(GPIO_PORT162);
1068}
1069
1070/* SDHI2 */
1071static struct sh_mobile_sdhi_info sdhi2_info = { 1055static struct sh_mobile_sdhi_info sdhi2_info = {
1072 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, 1056 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
1073 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, 1057 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
1074 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 1058 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1075 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 1059 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1076 MMC_CAP_NEEDS_POLL, 1060 MMC_CAP_NEEDS_POLL,
1077 .get_cd = slot_cn23_get_cd, 1061 .cd_gpio = 162,
1078}; 1062};
1079 1063
1080static struct resource sdhi2_resources[] = { 1064static struct resource sdhi2_resources[] = {
1081 [0] = { 1065 {
1082 .name = "SDHI2", 1066 .name = "SDHI2",
1083 .start = 0xe6870000, 1067 .start = 0xe6870000,
1084 .end = 0xe68700ff, 1068 .end = 0xe68700ff,
1085 .flags = IORESOURCE_MEM, 1069 .flags = IORESOURCE_MEM,
1086 }, 1070 }, {
1087 [1] = {
1088 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
1089 .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
1090 .flags = IORESOURCE_IRQ,
1091 },
1092 [2] = {
1093 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 1071 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1094 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ 1072 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
1095 .flags = IORESOURCE_IRQ, 1073 .flags = IORESOURCE_IRQ,
1096 }, 1074 }, {
1097 [3] = {
1098 .name = SH_MOBILE_SDHI_IRQ_SDIO, 1075 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1099 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ 1076 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
1100 .flags = IORESOURCE_IRQ, 1077 .flags = IORESOURCE_IRQ,
@@ -1112,6 +1089,7 @@ static struct platform_device sdhi2_device = {
1112}; 1089};
1113 1090
1114/* SH_MMCIF */ 1091/* SH_MMCIF */
1092#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1115static struct resource sh_mmcif_resources[] = { 1093static struct resource sh_mmcif_resources[] = {
1116 [0] = { 1094 [0] = {
1117 .name = "MMCIF", 1095 .name = "MMCIF",
@@ -1133,11 +1111,12 @@ static struct resource sh_mmcif_resources[] = {
1133 1111
1134static struct sh_mmcif_plat_data sh_mmcif_plat = { 1112static struct sh_mmcif_plat_data sh_mmcif_plat = {
1135 .sup_pclk = 0, 1113 .sup_pclk = 0,
1136 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
1137 .caps = MMC_CAP_4_BIT_DATA | 1114 .caps = MMC_CAP_4_BIT_DATA |
1138 MMC_CAP_8_BIT_DATA | 1115 MMC_CAP_8_BIT_DATA |
1139 MMC_CAP_NEEDS_POLL, 1116 MMC_CAP_NEEDS_POLL,
1140 .get_cd = slot_cn7_get_cd, 1117 .use_cd_gpio = true,
1118 /* card detect pin for SD/MMC slot (CN7) */
1119 .cd_gpio = 41,
1141 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, 1120 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1142 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, 1121 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
1143}; 1122};
@@ -1153,7 +1132,7 @@ static struct platform_device sh_mmcif_device = {
1153 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 1132 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
1154 .resource = sh_mmcif_resources, 1133 .resource = sh_mmcif_resources,
1155}; 1134};
1156 1135#endif
1157 1136
1158static int mackerel_camera_add(struct soc_camera_device *icd); 1137static int mackerel_camera_add(struct soc_camera_device *icd);
1159static void mackerel_camera_del(struct soc_camera_device *icd); 1138static void mackerel_camera_del(struct soc_camera_device *icd);
@@ -1260,11 +1239,12 @@ static struct platform_device *mackerel_devices[] __initdata = {
1260 &fsi_hdmi_device, 1239 &fsi_hdmi_device,
1261 &nand_flash_device, 1240 &nand_flash_device,
1262 &sdhi0_device, 1241 &sdhi0_device,
1263#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1242#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1264 &sdhi1_device, 1243 &sdhi1_device,
1244#else
1245 &sh_mmcif_device,
1265#endif 1246#endif
1266 &sdhi2_device, 1247 &sdhi2_device,
1267 &sh_mmcif_device,
1268 &ceu_device, 1248 &ceu_device,
1269 &mackerel_camera, 1249 &mackerel_camera,
1270 &hdmi_device, 1250 &hdmi_device,
@@ -1328,6 +1308,34 @@ static struct i2c_board_info i2c1_devices[] = {
1328 }, 1308 },
1329}; 1309};
1330 1310
1311static const struct pinctrl_map mackerel_pinctrl_map[] = {
1312 /* SDHI0 */
1313 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1314 "sdhi0_data4", "sdhi0"),
1315 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1316 "sdhi0_ctrl", "sdhi0"),
1317 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1318 "sdhi0_wp", "sdhi0"),
1319 /* SDHI1 */
1320#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1321 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1322 "sdhi1_data4", "sdhi1"),
1323 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1324 "sdhi1_ctrl", "sdhi1"),
1325#else
1326 /* MMCIF */
1327 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1328 "mmc0_data8_0", "mmc0"),
1329 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1330 "mmc0_ctrl_0", "mmc0"),
1331#endif
1332 /* SDHI2 */
1333 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1334 "sdhi2_data4", "sdhi2"),
1335 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1336 "sdhi2_ctrl", "sdhi2"),
1337};
1338
1331#define GPIO_PORT9CR IOMEM(0xE6051009) 1339#define GPIO_PORT9CR IOMEM(0xE6051009)
1332#define GPIO_PORT10CR IOMEM(0xE605100A) 1340#define GPIO_PORT10CR IOMEM(0xE605100A)
1333#define GPIO_PORT167CR IOMEM(0xE60520A7) 1341#define GPIO_PORT167CR IOMEM(0xE60520A7)
@@ -1344,10 +1352,11 @@ static void __init mackerel_init(void)
1344 { "A3SP", &usbhs0_device, }, 1352 { "A3SP", &usbhs0_device, },
1345 { "A3SP", &usbhs1_device, }, 1353 { "A3SP", &usbhs1_device, },
1346 { "A3SP", &nand_flash_device, }, 1354 { "A3SP", &nand_flash_device, },
1347 { "A3SP", &sh_mmcif_device, },
1348 { "A3SP", &sdhi0_device, }, 1355 { "A3SP", &sdhi0_device, },
1349#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1356#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1350 { "A3SP", &sdhi1_device, }, 1357 { "A3SP", &sdhi1_device, },
1358#else
1359 { "A3SP", &sh_mmcif_device, },
1351#endif 1360#endif
1352 { "A3SP", &sdhi2_device, }, 1361 { "A3SP", &sdhi2_device, },
1353 { "A4R", &ceu_device, }, 1362 { "A4R", &ceu_device, },
@@ -1364,6 +1373,8 @@ static void __init mackerel_init(void)
1364 /* External clock source */ 1373 /* External clock source */
1365 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1374 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1366 1375
1376 pinctrl_register_mappings(mackerel_pinctrl_map,
1377 ARRAY_SIZE(mackerel_pinctrl_map));
1367 sh7372_pinmux_init(); 1378 sh7372_pinmux_init();
1368 1379
1369 /* enable SCIFA0 */ 1380 /* enable SCIFA0 */
@@ -1403,9 +1414,9 @@ static void __init mackerel_init(void)
1403 gpio_request(GPIO_FN_LCDDCK, NULL); 1414 gpio_request(GPIO_FN_LCDDCK, NULL);
1404 1415
1405 /* backlight, off by default */ 1416 /* backlight, off by default */
1406 gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL); 1417 gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
1407 1418
1408 gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1419 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1409 1420
1410 /* USBHS0 */ 1421 /* USBHS0 */
1411 gpio_request(GPIO_FN_VBUS0_0, NULL); 1422 gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1432,10 @@ static void __init mackerel_init(void)
1421 gpio_request(GPIO_FN_FSIAILR, NULL); 1432 gpio_request(GPIO_FN_FSIAILR, NULL);
1422 gpio_request(GPIO_FN_FSIAISLD, NULL); 1433 gpio_request(GPIO_FN_FSIAISLD, NULL);
1423 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1434 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1424 gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ 1435 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1425 1436
1426 gpio_request(GPIO_PORT9, NULL); 1437 gpio_request(9, NULL);
1427 gpio_request(GPIO_PORT10, NULL); 1438 gpio_request(10, NULL);
1428 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1439 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1429 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1440 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1430 1441
@@ -1453,53 +1464,9 @@ static void __init mackerel_init(void)
1453 gpio_request(GPIO_FN_IRQ21, NULL); 1464 gpio_request(GPIO_FN_IRQ21, NULL);
1454 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); 1465 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1455 1466
1456 /* enable SDHI0 */
1457 gpio_request(GPIO_FN_SDHIWP0, NULL);
1458 gpio_request(GPIO_FN_SDHICMD0, NULL);
1459 gpio_request(GPIO_FN_SDHICLK0, NULL);
1460 gpio_request(GPIO_FN_SDHID0_3, NULL);
1461 gpio_request(GPIO_FN_SDHID0_2, NULL);
1462 gpio_request(GPIO_FN_SDHID0_1, NULL);
1463 gpio_request(GPIO_FN_SDHID0_0, NULL);
1464
1465 /* SDHI0 PORT172 card-detect IRQ26 */ 1467 /* SDHI0 PORT172 card-detect IRQ26 */
1466 gpio_request(GPIO_FN_IRQ26_172, NULL); 1468 gpio_request(GPIO_FN_IRQ26_172, NULL);
1467 1469
1468#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1469 /* enable SDHI1 */
1470 gpio_request(GPIO_FN_SDHICMD1, NULL);
1471 gpio_request(GPIO_FN_SDHICLK1, NULL);
1472 gpio_request(GPIO_FN_SDHID1_3, NULL);
1473 gpio_request(GPIO_FN_SDHID1_2, NULL);
1474 gpio_request(GPIO_FN_SDHID1_1, NULL);
1475 gpio_request(GPIO_FN_SDHID1_0, NULL);
1476#endif
1477 /* card detect pin for MMC slot (CN7) */
1478 gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
1479
1480 /* enable SDHI2 */
1481 gpio_request(GPIO_FN_SDHICMD2, NULL);
1482 gpio_request(GPIO_FN_SDHICLK2, NULL);
1483 gpio_request(GPIO_FN_SDHID2_3, NULL);
1484 gpio_request(GPIO_FN_SDHID2_2, NULL);
1485 gpio_request(GPIO_FN_SDHID2_1, NULL);
1486 gpio_request(GPIO_FN_SDHID2_0, NULL);
1487
1488 /* card detect pin for microSD slot (CN23) */
1489 gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
1490
1491 /* MMCIF */
1492 gpio_request(GPIO_FN_MMCD0_0, NULL);
1493 gpio_request(GPIO_FN_MMCD0_1, NULL);
1494 gpio_request(GPIO_FN_MMCD0_2, NULL);
1495 gpio_request(GPIO_FN_MMCD0_3, NULL);
1496 gpio_request(GPIO_FN_MMCD0_4, NULL);
1497 gpio_request(GPIO_FN_MMCD0_5, NULL);
1498 gpio_request(GPIO_FN_MMCD0_6, NULL);
1499 gpio_request(GPIO_FN_MMCD0_7, NULL);
1500 gpio_request(GPIO_FN_MMCCMD0, NULL);
1501 gpio_request(GPIO_FN_MMCCLK0, NULL);
1502
1503 /* FLCTL */ 1470 /* FLCTL */
1504 gpio_request(GPIO_FN_D0_NAF0, NULL); 1471 gpio_request(GPIO_FN_D0_NAF0, NULL);
1505 gpio_request(GPIO_FN_D1_NAF1, NULL); 1472 gpio_request(GPIO_FN_D1_NAF1, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
new file mode 100644
index 000000000000..480d882e42c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -0,0 +1,75 @@
1/*
2 * marzen board support - Reference DT implementation
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Simon Horman
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/pinctrl/machine.h>
23#include <mach/r8a7779.h>
24#include <mach/common.h>
25#include <mach/irqs.h>
26#include <asm/irq.h>
27#include <asm/mach/arch.h>
28
29static const struct pinctrl_map marzen_pinctrl_map[] = {
30 /* SCIF2 (CN18: DEBUG0) */
31 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
32 "scif2_data_c", "scif2"),
33 /* SCIF4 (CN19: DEBUG1) */
34 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
35 "scif4_data", "scif4"),
36 /* SDHI0 */
37 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
38 "sdhi0_data4", "sdhi0"),
39 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
40 "sdhi0_ctrl", "sdhi0"),
41 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
42 "sdhi0_cd", "sdhi0"),
43 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
44 "sdhi0_wp", "sdhi0"),
45 /* SMSC */
46 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
47 "intc_irq1_b", "intc"),
48 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
49 "lbsc_ex_cs0", "lbsc"),
50};
51
52static void __init marzen_init(void)
53{
54 pinctrl_register_mappings(marzen_pinctrl_map,
55 ARRAY_SIZE(marzen_pinctrl_map));
56 r8a7779_pinmux_init();
57
58 r8a7779_add_standard_devices_dt();
59}
60
61static const char *marzen_boards_compat_dt[] __initdata = {
62 "renesas,marzen-reference",
63 NULL,
64};
65
66DT_MACHINE_START(MARZEN, "marzen")
67 .smp = smp_ops(r8a7779_smp_ops),
68 .map_io = r8a7779_map_io,
69 .init_early = r8a7779_init_delay,
70 .nr_irqs = NR_IRQS_LEGACY,
71 .init_irq = r8a7779_init_irq_dt,
72 .init_machine = marzen_init,
73 .init_time = shmobile_timer_init,
74 .dt_compat = marzen_boards_compat_dt,
75MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fec49ebc359a..91052855cc12 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,8 +25,9 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/gpio.h> 28#include <linux/leds.h>
29#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
30#include <linux/pinctrl/machine.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
32#include <linux/smsc911x.h> 33#include <linux/smsc911x.h>
@@ -67,7 +68,7 @@ static struct resource smsc911x_resources[] = {
67 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
68 }, 69 },
69 [1] = { 70 [1] = {
70 .start = gic_spi(28), /* IRQ 1 */ 71 .start = gic_iid(0x3c), /* IRQ 1 */
71 .flags = IORESOURCE_IRQ, 72 .flags = IORESOURCE_IRQ,
72 }, 73 },
73}; 74};
@@ -97,7 +98,7 @@ static struct resource sdhi0_resources[] = {
97 .flags = IORESOURCE_MEM, 98 .flags = IORESOURCE_MEM,
98 }, 99 },
99 [1] = { 100 [1] = {
100 .start = gic_spi(104), 101 .start = gic_iid(0x88),
101 .flags = IORESOURCE_IRQ, 102 .flags = IORESOURCE_IRQ,
102 }, 103 },
103}; 104};
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
168 .num_resources = ARRAY_SIZE(usb_phy_resources), 169 .num_resources = ARRAY_SIZE(usb_phy_resources),
169}; 170};
170 171
172/* LEDS */
173static struct gpio_led marzen_leds[] = {
174 {
175 .name = "led2",
176 .gpio = 157,
177 .default_state = LEDS_GPIO_DEFSTATE_ON,
178 }, {
179 .name = "led3",
180 .gpio = 158,
181 .default_state = LEDS_GPIO_DEFSTATE_ON,
182 }, {
183 .name = "led4",
184 .gpio = 159,
185 .default_state = LEDS_GPIO_DEFSTATE_ON,
186 },
187};
188
189static struct gpio_led_platform_data marzen_leds_pdata = {
190 .leds = marzen_leds,
191 .num_leds = ARRAY_SIZE(marzen_leds),
192};
193
194static struct platform_device leds_device = {
195 .name = "leds-gpio",
196 .id = 0,
197 .dev = {
198 .platform_data = &marzen_leds_pdata,
199 },
200};
201
171static struct platform_device *marzen_devices[] __initdata = { 202static struct platform_device *marzen_devices[] __initdata = {
172 &eth_device, 203 &eth_device,
173 &sdhi0_device, 204 &sdhi0_device,
174 &thermal_device, 205 &thermal_device,
175 &hspi_device, 206 &hspi_device,
176 &usb_phy_device, 207 &usb_phy_device,
208 &leds_device,
177}; 209};
178 210
179/* USB */ 211/* USB */
@@ -215,7 +247,7 @@ static struct resource ehci0_resources[] = {
215 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
216 }, 248 },
217 [1] = { 249 [1] = {
218 .start = gic_spi(44), 250 .start = gic_iid(0x4c),
219 .flags = IORESOURCE_IRQ, 251 .flags = IORESOURCE_IRQ,
220 }, 252 },
221}; 253};
@@ -239,7 +271,7 @@ static struct resource ehci1_resources[] = {
239 .flags = IORESOURCE_MEM, 271 .flags = IORESOURCE_MEM,
240 }, 272 },
241 [1] = { 273 [1] = {
242 .start = gic_spi(45), 274 .start = gic_iid(0x4d),
243 .flags = IORESOURCE_IRQ, 275 .flags = IORESOURCE_IRQ,
244 }, 276 },
245}; 277};
@@ -269,7 +301,7 @@ static struct resource ohci0_resources[] = {
269 .flags = IORESOURCE_MEM, 301 .flags = IORESOURCE_MEM,
270 }, 302 },
271 [1] = { 303 [1] = {
272 .start = gic_spi(44), 304 .start = gic_iid(0x4c),
273 .flags = IORESOURCE_IRQ, 305 .flags = IORESOURCE_IRQ,
274 }, 306 },
275}; 307};
@@ -293,7 +325,7 @@ static struct resource ohci1_resources[] = {
293 .flags = IORESOURCE_MEM, 325 .flags = IORESOURCE_MEM,
294 }, 326 },
295 [1] = { 327 [1] = {
296 .start = gic_spi(45), 328 .start = gic_iid(0x4d),
297 .flags = IORESOURCE_IRQ, 329 .flags = IORESOURCE_IRQ,
298 }, 330 },
299}; 331};
@@ -327,6 +359,41 @@ void __init marzen_init_late(void)
327 ARRAY_SIZE(marzen_late_devices)); 359 ARRAY_SIZE(marzen_late_devices));
328} 360}
329 361
362static const struct pinctrl_map marzen_pinctrl_map[] = {
363 /* HSPI0 */
364 PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
365 "hspi0", "hspi0"),
366 /* SCIF2 (CN18: DEBUG0) */
367 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
368 "scif2_data_c", "scif2"),
369 /* SCIF4 (CN19: DEBUG1) */
370 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
371 "scif4_data", "scif4"),
372 /* SDHI0 */
373 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
374 "sdhi0_data4", "sdhi0"),
375 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
376 "sdhi0_ctrl", "sdhi0"),
377 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
378 "sdhi0_cd", "sdhi0"),
379 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
380 "sdhi0_wp", "sdhi0"),
381 /* SMSC */
382 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
383 "intc_irq1_b", "intc"),
384 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
385 "lbsc_ex_cs0", "lbsc"),
386 /* USB0 */
387 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
388 "usb0", "usb0"),
389 /* USB1 */
390 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
391 "usb1", "usb1"),
392 /* USB2 */
393 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
394 "usb2", "usb2"),
395};
396
330static void __init marzen_init(void) 397static void __init marzen_init(void)
331{ 398{
332 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 399 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -334,44 +401,10 @@ static void __init marzen_init(void)
334 regulator_register_fixed(1, dummy_supplies, 401 regulator_register_fixed(1, dummy_supplies,
335 ARRAY_SIZE(dummy_supplies)); 402 ARRAY_SIZE(dummy_supplies));
336 403
404 pinctrl_register_mappings(marzen_pinctrl_map,
405 ARRAY_SIZE(marzen_pinctrl_map));
337 r8a7779_pinmux_init(); 406 r8a7779_pinmux_init();
338 407
339 /* SCIF2 (CN18: DEBUG0) */
340 gpio_request(GPIO_FN_TX2_C, NULL);
341 gpio_request(GPIO_FN_RX2_C, NULL);
342
343 /* SCIF4 (CN19: DEBUG1) */
344 gpio_request(GPIO_FN_TX4, NULL);
345 gpio_request(GPIO_FN_RX4, NULL);
346
347 /* LAN89218 */
348 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
349 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
350
351 /* SD0 (CN20) */
352 gpio_request(GPIO_FN_SD0_CLK, NULL);
353 gpio_request(GPIO_FN_SD0_CMD, NULL);
354 gpio_request(GPIO_FN_SD0_DAT0, NULL);
355 gpio_request(GPIO_FN_SD0_DAT1, NULL);
356 gpio_request(GPIO_FN_SD0_DAT2, NULL);
357 gpio_request(GPIO_FN_SD0_DAT3, NULL);
358 gpio_request(GPIO_FN_SD0_CD, NULL);
359 gpio_request(GPIO_FN_SD0_WP, NULL);
360
361 /* HSPI 0 */
362 gpio_request(GPIO_FN_HSPI_CLK0, NULL);
363 gpio_request(GPIO_FN_HSPI_CS0, NULL);
364 gpio_request(GPIO_FN_HSPI_TX0, NULL);
365 gpio_request(GPIO_FN_HSPI_RX0, NULL);
366
367 /* USB (CN21) */
368 gpio_request(GPIO_FN_USB_OVC0, NULL);
369 gpio_request(GPIO_FN_USB_OVC1, NULL);
370 gpio_request(GPIO_FN_USB_OVC2, NULL);
371
372 /* USB (CN22) */
373 gpio_request(GPIO_FN_USB_PENC2, NULL);
374
375 r8a7779_add_standard_devices(); 408 r8a7779_add_standard_devices();
376 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); 409 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
377} 410}
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
new file mode 100644
index 000000000000..e710c00c3822
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -0,0 +1,115 @@
1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x270
29
30#define MPCKCR 0xe6150080
31#define SMSTPCR2 0xe6150138
32#define SMSTPCR5 0xe6150144
33
34static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE,
36 .len = CPG_LEN,
37};
38
39static struct clk extalr_clk = {
40 .rate = 32768,
41 .mapping = &cpg_mapping,
42};
43
44static struct clk extal1_clk = {
45 .rate = 26000000,
46 .mapping = &cpg_mapping,
47};
48
49static struct clk extal2_clk = {
50 .rate = 48000000,
51 .mapping = &cpg_mapping,
52};
53
54static struct clk *main_clks[] = {
55 &extalr_clk,
56 &extal1_clk,
57 &extal2_clk,
58};
59
60enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522,
63 MSTP_NR
64};
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74};
75
76static struct clk_lookup lookups[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
84
85 /* for DT */
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
87};
88
89void __init r8a73a4_clock_init(void)
90{
91 void __iomem *cpg_base, *reg;
92 int k, ret = 0;
93
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
96 */
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
98 BUG_ON(!cpg_base);
99 reg = cpg_base + (MPCKCR - CPG_BASE);
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
101 iounmap(cpg_base);
102
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]);
105
106 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
110
111 if (!ret)
112 shmobile_clk_init();
113 else
114 panic("failed to setup r8a73a4 clocks\n");
115}
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 1feb9a2286a8..c0d39aa6de50 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/r8a7740.h> 27#include <mach/r8a7740.h>
27 28
@@ -97,42 +98,13 @@ static struct clk dv_clk = {
97 .rate = 27000000, 98 .rate = 27000000,
98}; 99};
99 100
100static unsigned long div_recalc(struct clk *clk) 101SH_CLK_RATIO(div2, 1, 2);
101{ 102SH_CLK_RATIO(div1k, 1, 1024);
102 return clk->parent->rate / (int)(clk->priv);
103}
104
105static struct sh_clk_ops div_clk_ops = {
106 .recalc = div_recalc,
107};
108
109/* extal1 / 2 */
110static struct clk extal1_div2_clk = {
111 .ops = &div_clk_ops,
112 .priv = (void *)2,
113 .parent = &extal1_clk,
114};
115
116/* extal1 / 1024 */
117static struct clk extal1_div1024_clk = {
118 .ops = &div_clk_ops,
119 .priv = (void *)1024,
120 .parent = &extal1_clk,
121};
122
123/* extal1 / 2 / 1024 */
124static struct clk extal1_div2048_clk = {
125 .ops = &div_clk_ops,
126 .priv = (void *)1024,
127 .parent = &extal1_div2_clk,
128};
129 103
130/* extal2 / 2 */ 104SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
131static struct clk extal2_div2_clk = { 105SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
132 .ops = &div_clk_ops, 106SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
133 .priv = (void *)2, 107SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
134 .parent = &extal2_clk,
135};
136 108
137static struct sh_clk_ops followparent_clk_ops = { 109static struct sh_clk_ops followparent_clk_ops = {
138 .recalc = followparent_recalc, 110 .recalc = followparent_recalc,
@@ -143,11 +115,7 @@ static struct clk system_clk = {
143 .ops = &followparent_clk_ops, 115 .ops = &followparent_clk_ops,
144}; 116};
145 117
146static struct clk system_div2_clk = { 118SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
147 .ops = &div_clk_ops,
148 .priv = (void *)2,
149 .parent = &system_clk,
150};
151 119
152/* r_clk */ 120/* r_clk */
153static struct clk r_clk = { 121static struct clk r_clk = {
@@ -184,11 +152,7 @@ static struct clk pllc1_clk = {
184}; 152};
185 153
186/* PLLC1 / 2 */ 154/* PLLC1 / 2 */
187static struct clk pllc1_div2_clk = { 155SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
188 .ops = &div_clk_ops,
189 .priv = (void *)2,
190 .parent = &pllc1_clk,
191};
192 156
193/* USB clock */ 157/* USB clock */
194/* 158/*
@@ -323,6 +287,7 @@ struct clk *main_clks[] = {
323 &fsibck_clk, 287 &fsibck_clk,
324}; 288};
325 289
290/* DIV4 clocks */
326static void div4_kick(struct clk *clk) 291static void div4_kick(struct clk *clk)
327{ 292{
328 unsigned long value; 293 unsigned long value;
@@ -346,6 +311,26 @@ static struct clk_div4_table div4_table = {
346 .kick = div4_kick, 311 .kick = div4_kick,
347}; 312};
348 313
314enum {
315 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
316 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
317 DIV4_NR
318};
319
320struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
326 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
327 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
328 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
330 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
332};
333
349/* DIV6 reparent */ 334/* DIV6 reparent */
350enum { 335enum {
351 DIV6_HDMI, 336 DIV6_HDMI,
@@ -391,6 +376,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
391 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), 376 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
392}; 377};
393 378
379/* DIV6 clocks */
380enum {
381 DIV6_SUB,
382 DIV6_NR
383};
384
385static struct clk div6_clks[DIV6_NR] = {
386 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
387};
388
394/* HDMI1/2 clock */ 389/* HDMI1/2 clock */
395static unsigned long hdmi12_recalc(struct clk *clk) 390static unsigned long hdmi12_recalc(struct clk *clk)
396{ 391{
@@ -456,35 +451,6 @@ static struct clk fsidivs[] = {
456 451
457/* MSTP */ 452/* MSTP */
458enum { 453enum {
459 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
460 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
461 DIV4_NR
462};
463
464struct clk div4_clks[DIV4_NR] = {
465 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
466 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
467 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
468 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
469 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
470 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
471 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
472 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
473 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
474 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
475 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
476};
477
478enum {
479 DIV6_SUB,
480 DIV6_NR
481};
482
483static struct clk div6_clks[DIV6_NR] = {
484 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
485};
486
487enum {
488 MSTP128, MSTP127, MSTP125, 454 MSTP128, MSTP127, MSTP125,
489 MSTP116, MSTP111, MSTP100, MSTP117, 455 MSTP116, MSTP111, MSTP100, MSTP117,
490 456
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
new file mode 100644
index 000000000000..cd6855290b1f
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -0,0 +1,107 @@
1/*
2 * r8a7778 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/io.h>
27#include <linux/sh_clk.h>
28#include <linux/clkdev.h>
29#include <mach/common.h>
30
31#define MSTPCR0 IOMEM(0xffc80030)
32#define MSTPCR1 IOMEM(0xffc80034)
33#define MSTPCR3 IOMEM(0xffc8003c)
34#define MSTPSR1 IOMEM(0xffc80044)
35#define MSTPSR4 IOMEM(0xffc80048)
36#define MSTPSR6 IOMEM(0xffc8004c)
37#define MSTPCR4 IOMEM(0xffc80050)
38#define MSTPCR5 IOMEM(0xffc80054)
39#define MSTPCR6 IOMEM(0xffc80058)
40
41/* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range.
43 */
44
45static struct clk_mapping cpg_mapping = {
46 .phys = 0xffc80000,
47 .len = 0x80,
48};
49
50static struct clk clkp = {
51 .rate = 62500000, /* FIXME: shortcut */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping,
54};
55
56static struct clk *main_clks[] = {
57 &clkp,
58};
59
60enum {
61 MSTP114,
62 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
63 MSTP016, MSTP015,
64 MSTP_NR };
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
68 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
69 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
70 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
71 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
72 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
73 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
74 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
75 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
76};
77
78static struct clk_lookup lookups[] = {
79 /* MSTP32 clocks */
80 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
81 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
82 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
83 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
84 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
85 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
86 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
87 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
88 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
89};
90
91void __init r8a7778_clock_init(void)
92{
93 int k, ret = 0;
94
95 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
96 ret = clk_register(main_clks[k]);
97
98 if (!ret)
99 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
100
101 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
102
103 if (!ret)
104 shmobile_clk_init();
105 else
106 panic("failed to setup r8a7778 clocks\n");
107}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index d9edeaf66007..31d5cd4d9787 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -17,13 +17,36 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <linux/bitops.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <mach/clock.h>
25#include <mach/common.h> 27#include <mach/common.h>
26 28
29/*
30 * MD1 = 1 MD1 = 0
31 * (PLLA = 1500) (PLLA = 1600)
32 * (MHz) (MHz)
33 *------------------------------------------------+--------------------
34 * clkz 1000 (2/3) 800 (1/2)
35 * clkzs 250 (1/6) 200 (1/8)
36 * clki 750 (1/2) 800 (1/2)
37 * clks 250 (1/6) 200 (1/8)
38 * clks1 125 (1/12) 100 (1/16)
39 * clks3 187.5 (1/8) 200 (1/8)
40 * clks4 93.7 (1/16) 100 (1/16)
41 * clkp 62.5 (1/24) 50 (1/32)
42 * clkg 62.5 (1/24) 66.6 (1/24)
43 * clkb, CLKOUT
44 * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
45 * (MD2 = 1) 41.6 (1/36) 50 (1/32)
46*/
47
48#define MD(nr) BIT(nr)
49
27#define FRQMR IOMEM(0xffc80014) 50#define FRQMR IOMEM(0xffc80014)
28#define MSTPCR0 IOMEM(0xffc80030) 51#define MSTPCR0 IOMEM(0xffc80030)
29#define MSTPCR1 IOMEM(0xffc80034) 52#define MSTPCR1 IOMEM(0xffc80034)
@@ -36,6 +59,9 @@
36#define MSTPCR6 IOMEM(0xffc80058) 59#define MSTPCR6 IOMEM(0xffc80058)
37#define MSTPCR7 IOMEM(0xffc80040) 60#define MSTPCR7 IOMEM(0xffc80040)
38 61
62#define MODEMR 0xffcc0020
63
64
39/* ioremap() through clock mapping mandatory to avoid 65/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range. 66 * collision with ARM coherent DMA virtual memory range.
41 */ 67 */
@@ -50,44 +76,43 @@ static struct clk_mapping cpg_mapping = {
50 * from the platform code. 76 * from the platform code.
51 */ 77 */
52static struct clk plla_clk = { 78static struct clk plla_clk = {
53 .rate = 1500000000, 79 /* .rate will be updated on r8a7779_clock_init() */
54 .mapping = &cpg_mapping, 80 .mapping = &cpg_mapping,
55}; 81};
56 82
83/*
84 * clock ratio of these clock will be updated
85 * on r8a7779_clock_init()
86 */
87SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
88SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
89SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
90SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
91SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
92SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
93SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
94SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
95SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
96SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
97SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
98
57static struct clk *main_clks[] = { 99static struct clk *main_clks[] = {
58 &plla_clk, 100 &plla_clk,
59}; 101 &clkz_clk,
60 102 &clkzs_clk,
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; 103 &clki_clk,
62 104 &clks_clk,
63static struct clk_div_mult_table div4_div_mult_table = { 105 &clks1_clk,
64 .divisors = divisors, 106 &clks3_clk,
65 .nr_divisors = ARRAY_SIZE(divisors), 107 &clks4_clk,
66}; 108 &clkb_clk,
67 109 &clkout_clk,
68static struct clk_div4_table div4_table = { 110 &clkp_clk,
69 .div_mult_table = &div4_div_mult_table, 111 &clkg_clk,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87}; 112};
88 113
89enum { MSTP323, MSTP322, MSTP321, MSTP320, 114enum { MSTP323, MSTP322, MSTP321, MSTP320,
90 MSTP115, 115 MSTP115, MSTP114,
91 MSTP103, MSTP101, MSTP100, 116 MSTP103, MSTP101, MSTP100,
92 MSTP030, 117 MSTP030,
93 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 118 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -96,52 +121,29 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320,
96 MSTP_NR }; 121 MSTP_NR };
97 122
98static struct clk mstp_clks[MSTP_NR] = { 123static struct clk mstp_clks[MSTP_NR] = {
99 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ 124 [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
100 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ 125 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
101 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ 126 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
102 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ 127 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
103 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ 128 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
104 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ 129 [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
105 [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ 130 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
106 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ 131 [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
107 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ 132 [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
108 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ 133 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
109 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ 134 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
110 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ 135 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
111 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ 136 [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
112 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ 137 [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
113 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ 138 [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
114 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ 139 [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
115 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ 140 [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
116 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ 141 [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
117 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ 142 [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
118 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ 143 [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
119 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ 144 [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
120 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ 145 [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
121}; 146 [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
122
123static unsigned long mul4_recalc(struct clk *clk)
124{
125 return clk->parent->rate * 4;
126}
127
128static struct sh_clk_ops mul4_clk_ops = {
129 .recalc = mul4_recalc,
130};
131
132struct clk clkz_clk = {
133 .ops = &mul4_clk_ops,
134 .parent = &div4_clks[DIV4_S],
135};
136
137struct clk clkzs_clk = {
138 /* clks x 4 / 4 = clks */
139 .parent = &div4_clks[DIV4_S],
140};
141
142static struct clk *late_main_clks[] = {
143 &clkz_clk,
144 &clkzs_clk,
145}; 147};
146 148
147static struct clk_lookup lookups[] = { 149static struct clk_lookup lookups[] = {
@@ -151,16 +153,17 @@ static struct clk_lookup lookups[] = {
151 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), 153 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
152 154
153 /* DIV4 clocks */ 155 /* DIV4 clocks */
154 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), 156 CLKDEV_CON_ID("shyway_clk", &clks_clk),
155 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), 157 CLKDEV_CON_ID("bus_clk", &clkout_clk),
156 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), 158 CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
157 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), 159 CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
158 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), 160 CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
159 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 161 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
160 162
161 /* MSTP32 clocks */ 163 /* MSTP32 clocks */
162 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ 164 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
163 CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ 165 CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
166 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
164 CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ 167 CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
165 CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ 168 CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
166 CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ 169 CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -190,20 +193,60 @@ static struct clk_lookup lookups[] = {
190 193
191void __init r8a7779_clock_init(void) 194void __init r8a7779_clock_init(void)
192{ 195{
196 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
197 u32 mode;
193 int k, ret = 0; 198 int k, ret = 0;
194 199
200 BUG_ON(!modemr);
201 mode = ioread32(modemr);
202 iounmap(modemr);
203
204 if (mode & MD(1)) {
205 plla_clk.rate = 1500000000;
206
207 SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
208 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
209 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
210 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
211 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
212 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
213 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
214 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
215 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
216 if (mode & MD(2)) {
217 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
218 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
219 } else {
220 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
221 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
222 }
223 } else {
224 plla_clk.rate = 1600000000;
225
226 SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
227 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
228 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
229 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
230 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
231 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
232 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
233 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
234 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
235 if (mode & MD(2)) {
236 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
237 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
238 } else {
239 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
240 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
241 }
242 }
243
195 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 244 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
196 ret = clk_register(main_clks[k]); 245 ret = clk_register(main_clks[k]);
197 246
198 if (!ret) 247 if (!ret)
199 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
200
201 if (!ret)
202 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 248 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
203 249
204 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
205 ret = clk_register(late_main_clks[k]);
206
207 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 250 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
208 251
209 if (!ret) 252 if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
new file mode 100644
index 000000000000..bad9bf2e34d6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -0,0 +1,93 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x1000
29
30#define SMSTPCR2 0xe6150138
31#define SMSTPCR7 0xe615014c
32
33static struct clk_mapping cpg_mapping = {
34 .phys = CPG_BASE,
35 .len = CPG_LEN,
36};
37
38static struct clk p_clk = {
39 .rate = 65000000, /* shortcut for now */
40 .mapping = &cpg_mapping,
41};
42
43static struct clk mp_clk = {
44 .rate = 52000000, /* shortcut for now */
45 .mapping = &cpg_mapping,
46};
47
48static struct clk *main_clks[] = {
49 &p_clk,
50 &mp_clk,
51};
52
53enum { MSTP721, MSTP720,
54 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
55static struct clk mstp_clks[MSTP_NR] = {
56 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
57 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
58 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
59 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
60 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
61 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
62 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
63 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
64};
65
66static struct clk_lookup lookups[] = {
67 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
68 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
69 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
70 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
71 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
72 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
73 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
74 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
75};
76
77void __init r8a7790_clock_init(void)
78{
79 int k, ret = 0;
80
81 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
82 ret = clk_register(main_clks[k]);
83
84 if (!ret)
85 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
86
87 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
88
89 if (!ret)
90 shmobile_clk_init();
91 else
92 panic("failed to setup r8a7790 clocks\n");
93}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 45d21fe317f4..7e105932c09d 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <mach/clock.h>
24#include <mach/common.h> 25#include <mach/common.h>
25 26
26/* SH7372 registers */ 27/* SH7372 registers */
@@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = {
83 .rate = 48000000, 84 .rate = 48000000,
84}; 85};
85 86
86/* A fixed divide-by-2 block */ 87SH_CLK_RATIO(div2, 1, 2);
87static unsigned long div2_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 2;
90}
91
92static struct sh_clk_ops div2_clk_ops = {
93 .recalc = div2_recalc,
94};
95 88
96/* Divide dv_clki by two */ 89SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
97struct clk sh7372_dv_clki_div2_clk = { 90SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
98 .ops = &div2_clk_ops, 91SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
99 .parent = &sh7372_dv_clki_clk, 92SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
100};
101
102/* Divide extal1 by two */
103static struct clk extal1_div2_clk = {
104 .ops = &div2_clk_ops,
105 .parent = &sh7372_extal1_clk,
106};
107
108/* Divide extal2 by two */
109static struct clk extal2_div2_clk = {
110 .ops = &div2_clk_ops,
111 .parent = &sh7372_extal2_clk,
112};
113
114/* Divide extal2 by four */
115static struct clk extal2_div4_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &extal2_div2_clk,
118};
119 93
120/* PLLC0 and PLLC1 */ 94/* PLLC0 and PLLC1 */
121static unsigned long pllc01_recalc(struct clk *clk) 95static unsigned long pllc01_recalc(struct clk *clk)
@@ -147,10 +121,7 @@ static struct clk pllc1_clk = {
147}; 121};
148 122
149/* Divide PLLC1 by two */ 123/* Divide PLLC1 by two */
150static struct clk pllc1_div2_clk = { 124SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
151 .ops = &div2_clk_ops,
152 .parent = &pllc1_clk,
153};
154 125
155/* PLLC2 */ 126/* PLLC2 */
156 127
@@ -342,7 +313,7 @@ static struct clk_div4_table div4_table = {
342}; 313};
343 314
344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, 315enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
345 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, 316 DIV4_ZX, DIV4_HP,
346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, 317 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
347 DIV4_DDRP, DIV4_NR }; 318 DIV4_DDRP, DIV4_NR };
348 319
@@ -355,8 +326,6 @@ static struct clk div4_clks[DIV4_NR] = {
355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), 330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
362 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), 331 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
@@ -516,8 +485,6 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), 485 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
517 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), 486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
518 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), 487 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
519 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
520 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
521 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), 488 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
522 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), 489 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
523 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), 490 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
@@ -654,5 +621,4 @@ void __init sh7372_clock_init(void)
654 shmobile_clk_init(); 621 shmobile_clk_init();
655 else 622 else
656 panic("failed to setup sh7372 clocks\n"); 623 panic("failed to setup sh7372 clocks\n");
657
658} 624}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 71843dd39e16..784fbaa4cc55 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <asm/processor.h>
25#include <mach/clock.h>
24#include <mach/common.h> 26#include <mach/common.h>
25 27
26#define FRQCRA IOMEM(0xe6150000) 28#define FRQCRA IOMEM(0xe6150000)
@@ -82,61 +84,16 @@ struct clk sh73a0_extal2_clk = {
82 .rate = 48000000, 84 .rate = 48000000,
83}; 85};
84 86
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct sh_clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct sh_clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct sh_clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
113/* Divide extal1 by two */
114static struct clk extal1_div2_clk = {
115 .ops = &div2_clk_ops,
116 .parent = &sh73a0_extal1_clk,
117};
118
119/* Divide extal2 by two */
120static struct clk extal2_div2_clk = {
121 .ops = &div2_clk_ops,
122 .parent = &sh73a0_extal2_clk,
123};
124
125static struct sh_clk_ops main_clk_ops = { 87static struct sh_clk_ops main_clk_ops = {
126 .recalc = followparent_recalc, 88 .recalc = followparent_recalc,
127}; 89};
128 90
129/* Main clock */ 91/* Main clock */
130static struct clk main_clk = { 92static struct clk main_clk = {
93 /* .parent wll be set on sh73a0_clock_init() */
131 .ops = &main_clk_ops, 94 .ops = &main_clk_ops,
132}; 95};
133 96
134/* Divide Main clock by two */
135static struct clk main_div2_clk = {
136 .ops = &div2_clk_ops,
137 .parent = &main_clk,
138};
139
140/* PLL0, PLL1, PLL2, PLL3 */ 97/* PLL0, PLL1, PLL2, PLL3 */
141static unsigned long pll_recalc(struct clk *clk) 98static unsigned long pll_recalc(struct clk *clk)
142{ 99{
@@ -192,21 +149,17 @@ static struct clk pll3_clk = {
192 .enable_bit = 3, 149 .enable_bit = 3,
193}; 150};
194 151
195/* Divide PLL */ 152/* A fixed divide block */
196static struct clk pll1_div2_clk = { 153SH_CLK_RATIO(div2, 1, 2);
197 .ops = &div2_clk_ops, 154SH_CLK_RATIO(div7, 1, 7);
198 .parent = &pll1_clk, 155SH_CLK_RATIO(div13, 1, 13);
199};
200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205 156
206static struct clk pll1_div13_clk = { 157SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
207 .ops = &div13_clk_ops, 158SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
208 .parent = &pll1_clk, 159SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
209}; 160SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
161SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
162SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
210 163
211/* External input clock */ 164/* External input clock */
212struct clk sh73a0_extcki_clk = { 165struct clk sh73a0_extcki_clk = {
@@ -234,14 +187,24 @@ static struct clk *main_clks[] = {
234 &sh73a0_extalr_clk, 187 &sh73a0_extalr_clk,
235}; 188};
236 189
237static void div4_kick(struct clk *clk) 190static int frqcr_kick(void)
238{ 191{
239 unsigned long value; 192 int i;
193
194 /* set KICK bit in FRQCRB to update hardware setting, check success */
195 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
196 for (i = 1000; i; i--)
197 if (__raw_readl(FRQCRB) & (1 << 31))
198 cpu_relax();
199 else
200 return i;
240 201
241 /* set KICK bit in FRQCRB to update hardware setting */ 202 return -ETIMEDOUT;
242 value = __raw_readl(FRQCRB); 203}
243 value |= (1 << 31); 204
244 __raw_writel(value, FRQCRB); 205static void div4_kick(struct clk *clk)
206{
207 frqcr_kick();
245} 208}
246 209
247static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 210static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
@@ -258,7 +221,7 @@ static struct clk_div4_table div4_table = {
258}; 221};
259 222
260enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, 223enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
261 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; 224 DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
262 225
263#define DIV4(_reg, _bit, _mask, _flags) \ 226#define DIV4(_reg, _bit, _mask, _flags) \
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) 227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
@@ -271,12 +234,24 @@ static struct clk div4_clks[DIV4_NR] = {
271 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), 234 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
272 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), 235 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
273 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), 236 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
274 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
275 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
276 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), 237 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
277 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), 238 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
278}; 239};
279 240
241static unsigned long twd_recalc(struct clk *clk)
242{
243 return clk_get_rate(clk->parent) / 4;
244}
245
246static struct sh_clk_ops twd_clk_ops = {
247 .recalc = twd_recalc,
248};
249
250static struct clk twd_clk = {
251 .parent = &div4_clks[DIV4_Z],
252 .ops = &twd_clk_ops,
253};
254
280enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, 255enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
281 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, 256 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
282 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, 257 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -471,6 +446,7 @@ static struct clk dsi1phy_clk = {
471static struct clk *late_main_clks[] = { 446static struct clk *late_main_clks[] = {
472 &dsi0phy_clk, 447 &dsi0phy_clk,
473 &dsi1phy_clk, 448 &dsi1phy_clk,
449 &twd_clk,
474}; 450};
475 451
476enum { MSTP001, 452enum { MSTP001,
@@ -535,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
535static struct clk_lookup lookups[] = { 511static struct clk_lookup lookups[] = {
536 /* main clocks */ 512 /* main clocks */
537 CLKDEV_CON_ID("r_clk", &r_clk), 513 CLKDEV_CON_ID("r_clk", &r_clk),
514 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
538 515
539 /* DIV6 clocks */ 516 /* DIV6 clocks */
540 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 517 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e816ca9bd213..ad7df629d995 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -23,6 +23,19 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
25#include <linux/export.h> 25#include <linux/export.h>
26#include <mach/clock.h>
27#include <mach/common.h>
28
29unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
30{
31 struct clk_ratio *p = clk->priv;
32
33 return clk->parent->rate / p->div * p->mul;
34};
35
36struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
37 .recalc = shmobile_fixed_ratio_clk_recalc,
38};
26 39
27int __init shmobile_clk_init(void) 40int __init shmobile_clk_init(void)
28{ 41{
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 9e050268cde4..0afeb5c7061c 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -16,39 +16,22 @@
16#include <asm/cpuidle.h> 16#include <asm/cpuidle.h>
17#include <asm/io.h> 17#include <asm/io.h>
18 18
19int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv,
20 int index)
21{
22 cpu_do_idle();
23 return 0;
24}
25
26static struct cpuidle_device shmobile_cpuidle_dev;
27static struct cpuidle_driver shmobile_cpuidle_default_driver = { 19static struct cpuidle_driver shmobile_cpuidle_default_driver = {
28 .name = "shmobile_cpuidle", 20 .name = "shmobile_cpuidle",
29 .owner = THIS_MODULE, 21 .owner = THIS_MODULE,
30 .en_core_tk_irqen = 1,
31 .states[0] = ARM_CPUIDLE_WFI_STATE, 22 .states[0] = ARM_CPUIDLE_WFI_STATE,
32 .states[0].enter = shmobile_enter_wfi,
33 .safe_state_index = 0, /* C1 */ 23 .safe_state_index = 0, /* C1 */
34 .state_count = 1, 24 .state_count = 1,
35}; 25};
36 26
37static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver; 27static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver;
38 28
39void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv) 29void __init shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
40{ 30{
41 cpuidle_drv = drv; 31 cpuidle_drv = drv;
42} 32}
43 33
44int shmobile_cpuidle_init(void) 34int __init shmobile_cpuidle_init(void)
45{ 35{
46 struct cpuidle_device *dev = &shmobile_cpuidle_dev; 36 return cpuidle_register(cpuidle_drv, NULL);
47
48 cpuidle_register_driver(cpuidle_drv);
49
50 dev->state_count = cpuidle_drv->state_count;
51 cpuidle_register_device(dev);
52
53 return 0;
54} 37}
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
new file mode 100644
index 000000000000..76ac61292e48
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -0,0 +1,39 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3
4unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
5extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
6
7/* clock ratio */
8struct clk_ratio {
9 int mul;
10 int div;
11};
12
13#define SH_CLK_RATIO(name, m, d) \
14static struct clk_ratio name ##_ratio = { \
15 .mul = m, \
16 .div = d, \
17}
18
19#define SH_FIXED_RATIO_CLKg(name, p, r) \
20struct clk name = { \
21 .parent = &p, \
22 .ops = &shmobile_fixed_ratio_clk_ops,\
23 .priv = &r ## _ratio, \
24}
25
26#define SH_FIXED_RATIO_CLK(name, p, r) \
27static SH_FIXED_RATIO_CLKg(name, p, r);
28
29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
30 SH_CLK_RATIO(name, m, d); \
31 SH_FIXED_RATIO_CLK(name, p, name);
32
33#define SH_CLK_SET_RATIO(p, m, d) \
34{ \
35 (p)->mul = m; \
36 (p)->div = d; \
37}
38
39#endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 03f73def2fc6..4634a5d4b63f 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -14,65 +14,8 @@ extern int shmobile_clk_init(void);
14extern void shmobile_handle_irq_intc(struct pt_regs *); 14extern void shmobile_handle_irq_intc(struct pt_regs *);
15extern struct platform_suspend_ops shmobile_suspend_ops; 15extern struct platform_suspend_ops shmobile_suspend_ops;
16struct cpuidle_driver; 16struct cpuidle_driver;
17struct cpuidle_device;
18extern int shmobile_enter_wfi(struct cpuidle_device *dev,
19 struct cpuidle_driver *drv, int index);
20extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 17extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
21 18
22extern void sh7372_init_irq(void);
23extern void sh7372_map_io(void);
24extern void sh7372_earlytimer_init(void);
25extern void sh7372_add_early_devices(void);
26extern void sh7372_add_standard_devices(void);
27extern void sh7372_add_early_devices_dt(void);
28extern void sh7372_add_standard_devices_dt(void);
29extern void sh7372_clock_init(void);
30extern void sh7372_pinmux_init(void);
31extern void sh7372_pm_init(void);
32extern void sh7372_resume_core_standby_sysc(void);
33extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
34extern struct clk sh7372_extal1_clk;
35extern struct clk sh7372_extal2_clk;
36
37extern void sh73a0_init_delay(void);
38extern void sh73a0_init_irq(void);
39extern void sh73a0_init_irq_dt(void);
40extern void sh73a0_map_io(void);
41extern void sh73a0_earlytimer_init(void);
42extern void sh73a0_add_early_devices(void);
43extern void sh73a0_add_standard_devices(void);
44extern void sh73a0_add_standard_devices_dt(void);
45extern void sh73a0_clock_init(void);
46extern void sh73a0_pinmux_init(void);
47extern void sh73a0_pm_init(void);
48extern struct clk sh73a0_extal1_clk;
49extern struct clk sh73a0_extal2_clk;
50extern struct clk sh73a0_extcki_clk;
51extern struct clk sh73a0_extalr_clk;
52
53extern void r8a7740_meram_workaround(void);
54extern void r8a7740_init_irq(void);
55extern void r8a7740_map_io(void);
56extern void r8a7740_add_early_devices(void);
57extern void r8a7740_add_standard_devices(void);
58extern void r8a7740_clock_init(u8 md_ck);
59extern void r8a7740_pinmux_init(void);
60extern void r8a7740_pm_init(void);
61
62extern void r8a7779_init_delay(void);
63extern void r8a7779_init_irq(void);
64extern void r8a7779_init_irq_extpin(int irlm);
65extern void r8a7779_init_irq_dt(void);
66extern void r8a7779_map_io(void);
67extern void r8a7779_earlytimer_init(void);
68extern void r8a7779_add_early_devices(void);
69extern void r8a7779_add_standard_devices(void);
70extern void r8a7779_add_standard_devices_dt(void);
71extern void r8a7779_clock_init(void);
72extern void r8a7779_pinmux_init(void);
73extern void r8a7779_pm_init(void);
74extern void r8a7779_register_twd(void);
75
76#ifdef CONFIG_SUSPEND 19#ifdef CONFIG_SUSPEND
77int shmobile_suspend_init(void); 20int shmobile_suspend_init(void);
78#else 21#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
new file mode 100644
index 000000000000..f043103e32c9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A73A4_H__
2#define __ASM_R8A73A4_H__
3
4void r8a73a4_add_standard_devices(void);
5void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void);
7
8#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 59d252f4cf97..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
241 241
242 /* LCD0 */ 242 /* LCD0 */
243 GPIO_FN_LCDC0_SELECT, 243 GPIO_FN_LCDC0_SELECT,
244 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
245 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
246 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
247 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
248 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
249 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
250 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
251
252 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
253 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
254
255 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
256 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
257
258 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
259 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
260 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
261 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
262
263 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
264 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
265 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
266 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
267 244
268 /* LCD1 */ 245 /* LCD1 */
269 GPIO_FN_LCDC1_SELECT, 246 GPIO_FN_LCDC1_SELECT,
270 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
271 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
272 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
273 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
274 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
275 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
276 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
277 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
278 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
279 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
280
281 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
282 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
283
284 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
285 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
286 247
287 /* RSPI */ 248 /* RSPI */
288 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, 249 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
@@ -346,26 +307,6 @@ enum {
346 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ 307 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
347 GPIO_FN_SIM_D_PORT199, 308 GPIO_FN_SIM_D_PORT199,
348 309
349 /* SDHI0 */
350 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
351 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
352 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
353
354 /* SDHI1 */
355 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
356 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
357 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
358
359 /* SDHI2 */
360 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
361 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
362
363 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
364 GPIO_FN_SDHI2_WP_PORT25,
365
366 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
367 GPIO_FN_SDHI2_CD_PORT202,
368
369 /* MSIOF2 */ 310 /* MSIOF2 */
370 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, 311 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
371 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, 312 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
@@ -417,21 +358,6 @@ enum {
417 GPIO_FN_MEMC_DREQ1, 358 GPIO_FN_MEMC_DREQ1,
418 GPIO_FN_MEMC_A0, 359 GPIO_FN_MEMC_A0,
419 360
420 /* MMC */
421 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
422 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
423 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
424 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
425 GPIO_FN_MMC0_CLK_PORT66,
426 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
427
428 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
429 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
430 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
431 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
432 GPIO_FN_MMC1_CLK_PORT103,
433 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
434
435 /* MSIOF0 */ 361 /* MSIOF0 */
436 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, 362 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
437 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, 363 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
@@ -606,6 +532,15 @@ enum {
606 SHDMA_SLAVE_USBHS_RX, 532 SHDMA_SLAVE_USBHS_RX,
607}; 533};
608 534
535extern void r8a7740_meram_workaround(void);
536extern void r8a7740_init_irq(void);
537extern void r8a7740_map_io(void);
538extern void r8a7740_add_early_devices(void);
539extern void r8a7740_add_standard_devices(void);
540extern void r8a7740_clock_init(u8 md_ck);
541extern void r8a7740_pinmux_init(void);
542extern void r8a7740_pm_init(void);
543
609#ifdef CONFIG_PM 544#ifdef CONFIG_PM
610extern void __init r8a7740_init_pm_domains(void); 545extern void __init r8a7740_init_pm_domains(void);
611#else 546#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
new file mode 100644
index 000000000000..951149e6bcca
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__
20
21#include <linux/sh_eth.h>
22
23extern void r8a7778_add_standard_devices(void);
24extern void r8a7778_add_standard_devices_dt(void);
25extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
26extern void r8a7778_init_delay(void);
27extern void r8a7778_init_irq(void);
28extern void r8a7778_init_irq_dt(void);
29extern void r8a7778_clock_init(void);
30extern void r8a7778_init_irq_extpin(int irlm);
31
32#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ab0cd6ad6b0..188b295938a5 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -3,327 +3,7 @@
3 3
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6 6#include <linux/sh_eth.h>
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
78 GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
79 GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
80 GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
83 GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
85 GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
86 GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
87 GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
88 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
89 GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
90
91 /* IPSR1 */
92 GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
93 GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
94 GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
95 GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
96 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
97 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
98 GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
99 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
100 GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
101 GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
102 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
103 GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
104 GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
105 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
106 GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
107 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
108 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
109
110 /* IPSR2 */
111 GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
112 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
113 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
114 GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
115 GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
116 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
117 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
118 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
119 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
120 GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
121 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
122 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
123 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
124 GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
125 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
126 GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
127 GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
128 GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
129 GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
130 GPIO_FN_AUDATA2,
131
132 /* IPSR3 */
133 GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
134 GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
135 GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
136 GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
137 GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
138 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
139 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
140 GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
141 GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
142 GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
143 GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
144 GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
145 GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
146 GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
147 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
148 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
149 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
150 GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
151 GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
152
153 /* IPSR4 */
154 GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
155 GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
156 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
157 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
158 GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
159 GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
160 GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
161 GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
162 GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
163 GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
164 GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
165 GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
166 GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
167 GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
168 GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
169 GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
170 GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
171 GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
172 GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
173
174 /* IPSR5 */
175 GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
176 GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
177 GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
178 GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
179 GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
180 GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
181 GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
182 GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
183 GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
184 GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
185 GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
186 GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
187 GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
188 GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
189 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
190 GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
191 GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
192 GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
193 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
194 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
195 GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
196 GPIO_FN_MOUT0,
197
198 /* IPSR6 */
199 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
200 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
201 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
202 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
203 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
204 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
205 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
206 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
207 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
208 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
209 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
210 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
211 GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
212 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
213 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
214 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
215
216 /* IPSR7 */
217 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
218 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
219 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
220 GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
221 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
222 GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
223 GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
224 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
225 GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
226 GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
227 GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
228 GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
229 GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
230 GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
231 GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
232 GPIO_FN_CTS1_B,
233
234 /* IPSR8 */
235 GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
236 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
237 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
238 GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
239 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
240 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
241 GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
242 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
243 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
244 GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
245 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
246 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
247 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
248 GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
249 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
250 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
251 GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
252 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
253 GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
254
255 /* IPSR9 */
256 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
257 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
258 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
259 GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
260 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
261 GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
262 GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
263 GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
264 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
265 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
266 GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
267 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
268 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
269 GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
270 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
271 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
272 GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
273 GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
274
275 /* IPSR10 */
276 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
277 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
278 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
279 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
280 GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
281 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
282 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
283 GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
284 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
285 GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
286 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
287 GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
288 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
289 GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
290 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
291 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
292 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
293 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
294 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
295
296 /* IPSR11 */
297 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
298 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
299 GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
300 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
301 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
302 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
303 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
304 GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
305 GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
306 GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
307 GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
308 GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
309 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
310 GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
311 GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
312 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
313 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
314 GPIO_FN_HRTS0_B,
315
316 /* IPSR12 */
317 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
318 GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
319 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
320 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
321 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
322 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
323 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
324 GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
325 GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
326};
327 7
328struct platform_device; 8struct platform_device;
329 9
@@ -343,6 +23,20 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
343 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; 23 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
344} 24}
345 25
26extern void r8a7779_init_delay(void);
27extern void r8a7779_init_irq(void);
28extern void r8a7779_init_irq_extpin(int irlm);
29extern void r8a7779_init_irq_dt(void);
30extern void r8a7779_map_io(void);
31extern void r8a7779_earlytimer_init(void);
32extern void r8a7779_add_early_devices(void);
33extern void r8a7779_add_standard_devices(void);
34extern void r8a7779_add_standard_devices_dt(void);
35extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
36extern void r8a7779_clock_init(void);
37extern void r8a7779_pinmux_init(void);
38extern void r8a7779_pm_init(void);
39extern void r8a7779_register_twd(void);
346extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); 40extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
347extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); 41extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
348 42
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
new file mode 100644
index 000000000000..2e919e61fa0d
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__
3
4void r8a7790_add_standard_devices(void);
5void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void);
7void r8a7790_timer_init(void);
8
9#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b582facc1cf6..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
294 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, 294 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
295 GPIO_FN_D15_NAF15, 295 GPIO_FN_D15_NAF15,
296 296
297 /*
298 * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
299 * 90, 91, 92, 99)
300 */
301 GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
302 GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
303 GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
304 GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
305
306 /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
307 GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
308 GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
309 GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
310 GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
311
312 /* SPU2 (PORT 65) */ 297 /* SPU2 (PORT 65) */
313 GPIO_FN_VINT_I, 298 GPIO_FN_VINT_I,
314 299
@@ -416,20 +401,6 @@ enum {
416 /* HDMI (PORT 169, 170) */ 401 /* HDMI (PORT 169, 170) */
417 GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, 402 GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
418 403
419 /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
420 GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
421 GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
422 GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
423 GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
424
425 /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
426 GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
427 GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
428
429 /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
430 GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
431 GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
432
433 /* SDENC see MSEL4CR 19 */ 404 /* SDENC see MSEL4CR 19 */
434 GPIO_FN_SDENC_CPG, 405 GPIO_FN_SDENC_CPG,
435 GPIO_FN_SDENC_DV_CLKI, 406 GPIO_FN_SDENC_DV_CLKI,
@@ -478,6 +449,18 @@ extern struct clk sh7372_dv_clki_clk;
478extern struct clk sh7372_dv_clki_div2_clk; 449extern struct clk sh7372_dv_clki_div2_clk;
479extern struct clk sh7372_pllc2_clk; 450extern struct clk sh7372_pllc2_clk;
480 451
452extern void sh7372_init_irq(void);
453extern void sh7372_map_io(void);
454extern void sh7372_earlytimer_init(void);
455extern void sh7372_add_early_devices(void);
456extern void sh7372_add_standard_devices(void);
457extern void sh7372_add_early_devices_dt(void);
458extern void sh7372_add_standard_devices_dt(void);
459extern void sh7372_clock_init(void);
460extern void sh7372_pinmux_init(void);
461extern void sh7372_pm_init(void);
462extern void sh7372_resume_core_standby_sysc(void);
463extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
481extern void sh7372_intcs_suspend(void); 464extern void sh7372_intcs_suspend(void);
482extern void sh7372_intcs_resume(void); 465extern void sh7372_intcs_resume(void);
483extern void sh7372_intca_suspend(void); 466extern void sh7372_intca_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 606d31d02a4e..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, 94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
95 95
96 /* Table 25-1 (Function 0-7) */ 96 /* Table 25-1 (Function 0-7) */
97 GPIO_FN_VBUS_0, 97 GPIO_FN_GPI0 = 310,
98 GPIO_FN_GPI0,
99 GPIO_FN_GPI1, 98 GPIO_FN_GPI1,
100 GPIO_FN_GPI2, 99 GPIO_FN_GPI2,
101 GPIO_FN_GPI3, 100 GPIO_FN_GPI3,
@@ -103,15 +102,11 @@ enum {
103 GPIO_FN_GPI5, 102 GPIO_FN_GPI5,
104 GPIO_FN_GPI6, 103 GPIO_FN_GPI6,
105 GPIO_FN_GPI7, 104 GPIO_FN_GPI7,
106 GPIO_FN_SCIFA7_RXD,
107 GPIO_FN_SCIFA7_CTS_,
108 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, 105 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
109 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, 106 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
110 GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ 107 GPIO_FN_GPO5,
111 GPIO_FN_PORT16_VIO_CKOR, 108 GPIO_FN_PORT16_VIO_CKOR,
112 GPIO_FN_SCIFA0_TXD, 109 GPIO_FN_PORT19_VIO_CKO2,
113 GPIO_FN_SCIFA7_TXD,
114 GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
115 GPIO_FN_GPO0, 110 GPIO_FN_GPO0,
116 GPIO_FN_GPO1, 111 GPIO_FN_GPO1,
117 GPIO_FN_GPO2, GPIO_FN_STATUS0, 112 GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -119,83 +114,44 @@ enum {
119 GPIO_FN_GPO4, GPIO_FN_STATUS2, 114 GPIO_FN_GPO4, GPIO_FN_STATUS2,
120 GPIO_FN_VINT, 115 GPIO_FN_VINT,
121 GPIO_FN_TCKON, 116 GPIO_FN_TCKON,
122 GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ 117 GPIO_FN_XDVFS1,
123 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, 118 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
124 GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ 119 GPIO_FN_XDVFS2,
125 GPIO_FN_PORT28_TPU1TO1, 120 GPIO_FN_PORT28_TPU1TO1,
126 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, 121 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
127 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, 122 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
128 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, 123 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
129 GPIO_FN_SCIFA4_TXD, 124 GPIO_FN_XWUP,
130 GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
131 GPIO_FN_SCIFA4_RTS_,
132 GPIO_FN_SCIFA4_CTS_,
133 GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
134 GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
135 GPIO_FN_FSIBOSLD,
136 GPIO_FN_FSIBISLD,
137 GPIO_FN_VACK, 125 GPIO_FN_VACK,
138 GPIO_FN_XTAL1L, 126 GPIO_FN_XTAL1L,
139 GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, 127 GPIO_FN_PORT49_IROUT,
140 GPIO_FN_SCIFA0_RXD, 128 GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
141 GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, 129
142 GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, 130 GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
143 GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, 131 GPIO_FN_BBIF2_TXD2,
144 GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, 132 GPIO_FN_TPU3TO3,
145 GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, 133 GPIO_FN_TPU3TO2,
146 GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ 134 GPIO_FN_TPU0TO0,
147 GPIO_FN_FSIAOMC,
148 GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
149
150 GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
151 GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
152 GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
153 GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
154 GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
155 GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
156 GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
157 GPIO_FN_A0, GPIO_FN_BS_, 135 GPIO_FN_A0, GPIO_FN_BS_,
158 GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, 136 GPIO_FN_A12, GPIO_FN_TPU4TO2,
159 GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, 137 GPIO_FN_A13, GPIO_FN_TPU0TO1,
160 GPIO_FN_A14, GPIO_FN_KEYOUT5, 138 GPIO_FN_A14,
161 GPIO_FN_A15, GPIO_FN_KEYOUT4, 139 GPIO_FN_A15,
162 GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, 140 GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
163 GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, 141 GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
164 GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, 142 GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
165 GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, 143 GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
166 GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, 144 GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
167 GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, 145 GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
168 GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, 146 GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
169 GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, 147 GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
170 GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, 148 GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
171 GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, 149 GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
172 GPIO_FN_A26, GPIO_FN_KEYIN6, 150 GPIO_FN_A26,
173 GPIO_FN_KEYIN7, 151 GPIO_FN_FCE1_,
174 GPIO_FN_D0_NAF0, 152 GPIO_FN_DACK0,
175 GPIO_FN_D1_NAF1, 153 GPIO_FN_FCE0_,
176 GPIO_FN_D2_NAF2,
177 GPIO_FN_D3_NAF3,
178 GPIO_FN_D4_NAF4,
179 GPIO_FN_D5_NAF5,
180 GPIO_FN_D6_NAF6,
181 GPIO_FN_D7_NAF7,
182 GPIO_FN_D8_NAF8,
183 GPIO_FN_D9_NAF9,
184 GPIO_FN_D10_NAF10,
185 GPIO_FN_D11_NAF11,
186 GPIO_FN_D12_NAF12,
187 GPIO_FN_D13_NAF13,
188 GPIO_FN_D14_NAF14,
189 GPIO_FN_D15_NAF15,
190 GPIO_FN_CS4_,
191 GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
192 GPIO_FN_CS5B_, GPIO_FN_FCE1_,
193 GPIO_FN_CS6B_, GPIO_FN_DACK0,
194 GPIO_FN_FCE0_, GPIO_FN_CS6A_,
195 GPIO_FN_WAIT_, GPIO_FN_DREQ0, 154 GPIO_FN_WAIT_, GPIO_FN_DREQ0,
196 GPIO_FN_RD__FSC,
197 GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
198 GPIO_FN_WE1_,
199 GPIO_FN_FRB, 155 GPIO_FN_FRB,
200 GPIO_FN_CKO, 156 GPIO_FN_CKO,
201 GPIO_FN_NBRSTOUT_, 157 GPIO_FN_NBRSTOUT_,
@@ -204,145 +160,118 @@ enum {
204 GPIO_FN_BBIF2_RXD, 160 GPIO_FN_BBIF2_RXD,
205 GPIO_FN_BBIF2_SYNC, 161 GPIO_FN_BBIF2_SYNC,
206 GPIO_FN_BBIF2_SCK, 162 GPIO_FN_BBIF2_SCK,
207 GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, 163 GPIO_FN_MFG3_IN2,
208 GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, 164 GPIO_FN_MFG3_IN1,
209 GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, 165 GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
210 GPIO_FN_SCIFA3_TXD,
211 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, 166 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
212 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, 167 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
213 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, 168 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
214 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, 169 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
215 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ 170 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
216 GPIO_FN_PORT115_I2C_SCL3, 171 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
217 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
218 GPIO_FN_PORT116_I2C_SDA3,
219 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, 172 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
220 GPIO_FN_HSI_TX_FLAG, 173 GPIO_FN_HSI_TX_FLAG,
221 GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ 174 GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
222 GPIO_FN_LCD2D0, 175
223 176 GPIO_FN_VIO_HD,
224 GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ 177 GPIO_FN_VIO2_HD,
225 GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, 178 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
226 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, 179 GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
227 GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ 180 GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
228 GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, 181 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
229 GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ 182 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
230 GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, 183 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
231 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, 184 GPIO_FN_VIO_D6,
232 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, 185 GPIO_FN_VIO_D7,
233 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, 186 GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
234 GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, 187 GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
235 GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, 188 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
236 GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ 189 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
237 GPIO_FN_LCD2D6, 190 GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
238 GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ 191 GPIO_FN_VIO_D13,
239 GPIO_FN_LCD2D7, 192 GPIO_FN_VIO2_D5,
240 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, 193 GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
241 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, 194 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
242 GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ 195 GPIO_FN_VIO2_D7,
243 GPIO_FN_LCD2D2, 196 GPIO_FN_VIO_CLK,
244 GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ 197 GPIO_FN_VIO2_CLK,
245 GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, 198 GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
246 GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
247 GPIO_FN_LCD2D4,
248 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
249 GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
250 GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
251 GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
252 GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
253 GPIO_FN_VIO_CKO, 199 GPIO_FN_VIO_CKO,
254 GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ 200 GPIO_FN_A27, GPIO_FN_MFG0_IN1,
255 GPIO_FN_PORT149_KEYOUT9,
256 GPIO_FN_MFG0_IN2, 201 GPIO_FN_MFG0_IN2,
257 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, 202 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
258 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, 203 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
259 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, 204 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
260 GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, 205 GPIO_FN_MSIOF2_MCK0,
261 GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, 206 GPIO_FN_MSIOF2_MCK1,
262 GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, 207 GPIO_FN_PORT156_MSIOF2_SS2,
263 GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, 208 GPIO_FN_PORT157_MSIOF2_RXD,
264 GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, 209 GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
265 GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, 210 GPIO_FN_NMI,
266 GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
267 GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
268 GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
269 GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
270 GPIO_FN_TPU3TO0, 211 GPIO_FN_TPU3TO0,
271 GPIO_FN_LCDD0, 212 GPIO_FN_BBIF2_TSYNC1,
272 GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, 213 GPIO_FN_BBIF2_TSCK1,
273 GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, 214 GPIO_FN_BBIF2_TXD1,
274 GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, 215 GPIO_FN_MFG2_OUT2,
275 GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
276 GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
277 GPIO_FN_TPU2TO1, 216 GPIO_FN_TPU2TO1,
278 GPIO_FN_LCDD6, 217 GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
279 GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, 218 GPIO_FN_D16,
280 GPIO_FN_LCDD8, GPIO_FN_D16, 219 GPIO_FN_D17,
281 GPIO_FN_LCDD9, GPIO_FN_D17, 220 GPIO_FN_D18,
282 GPIO_FN_LCDD10, GPIO_FN_D18, 221 GPIO_FN_D19,
283 GPIO_FN_LCDD11, GPIO_FN_D19, 222 GPIO_FN_D20,
284 GPIO_FN_LCDD12, GPIO_FN_D20, 223 GPIO_FN_D21,
285 GPIO_FN_LCDD13, GPIO_FN_D21, 224 GPIO_FN_D22,
286 GPIO_FN_LCDD14, GPIO_FN_D22, 225 GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
287 GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, 226 GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
288 GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, 227 GPIO_FN_D25,
289 GPIO_FN_LCDD17, GPIO_FN_D25, 228 GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
290 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, 229 GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
291 GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, 230 GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
292 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, 231 GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
293 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, 232 GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
294 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, 233 GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
295 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, 234 GPIO_FN_DACK2,
296 GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, 235 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
297 GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ 236 GPIO_FN_DACK3,
298 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
299 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
300 GPIO_FN_PORT218_VIO_CKOR, 237 GPIO_FN_PORT218_VIO_CKOR,
301 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
302 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ 238 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
303 GPIO_FN_LCD2DCK_2, 239 GPIO_FN_DREQ1,
304 GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
305 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
306 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ 240 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
307 GPIO_FN_PORT221_LCD2HSYN, 241 GPIO_FN_DACK1, GPIO_FN_OVCN,
308 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ 242 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
309 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, 243
310 244 GPIO_FN_OVCN2,
311 GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, 245 GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
312 GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, 246 GPIO_FN_IDIN,
313 GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, 247 GPIO_FN_MFG1_IN1,
314 GPIO_FN_SCIFA1_RXD, 248 GPIO_FN_MSIOF1_TXD,
315 GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, 249 GPIO_FN_MSIOF1_TSYNC,
316 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, 250 GPIO_FN_MSIOF1_TSCK,
317 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, 251 GPIO_FN_MSIOF1_RXD,
318 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, 252 GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
319 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
320 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
321 GPIO_FN_LCD2D20,
322 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ 253 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
323 GPIO_FN_LCD2D21, 254 GPIO_FN_MSIOF1_MCK0,
324 GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, 255 GPIO_FN_MSIOF1_MCK1,
325 GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, 256 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
326 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, 257 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
327 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, 258 GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
328 GPIO_FN_SCIFA6_TXD,
329 GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
330 GPIO_FN_TPU4TO0, 259 GPIO_FN_TPU4TO0,
331 GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, 260 GPIO_FN_MFG4_IN2,
332 GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, 261 GPIO_FN_PORT243_VIO_CKO2,
333 GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ 262 GPIO_FN_MFG2_IN1,
334 GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, 263 GPIO_FN_MSIOF2R_RXD,
335 GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ 264 GPIO_FN_MFG2_IN2,
336 GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, 265 GPIO_FN_MSIOF2R_TXD,
337 GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ 266 GPIO_FN_MFG1_OUT1,
338 GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, 267 GPIO_FN_TPU1TO0,
339 GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ 268 GPIO_FN_MFG3_OUT2,
340 GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, 269 GPIO_FN_TPU3TO1,
341 GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ 270 GPIO_FN_MFG2_OUT1,
342 GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ 271 GPIO_FN_TPU2TO0,
343 GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, 272 GPIO_FN_MSIOF2R_TSCK,
344 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ 273 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
345 GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, 274 GPIO_FN_MSIOF2R_TSYNC,
346 GPIO_FN_SDHICLK0, 275 GPIO_FN_SDHICLK0,
347 GPIO_FN_SDHICD0, 276 GPIO_FN_SDHICD0,
348 GPIO_FN_SDHID0_0, 277 GPIO_FN_SDHID0_0,
@@ -435,54 +364,12 @@ enum {
435 GPIO_FN_IRQ9_MEM_INT, 364 GPIO_FN_IRQ9_MEM_INT,
436 GPIO_FN_IRQ9_MCP_INT, 365 GPIO_FN_IRQ9_MCP_INT,
437 GPIO_FN_A11, 366 GPIO_FN_A11,
438 GPIO_FN_KEYOUT8,
439 GPIO_FN_TPU4TO3, 367 GPIO_FN_TPU4TO3,
440 GPIO_FN_RESETA_N_PU_ON, 368 GPIO_FN_RESETA_N_PU_ON,
441 GPIO_FN_RESETA_N_PU_OFF, 369 GPIO_FN_RESETA_N_PU_OFF,
442 GPIO_FN_EDBGREQ_PD, 370 GPIO_FN_EDBGREQ_PD,
443 GPIO_FN_EDBGREQ_PU, 371 GPIO_FN_EDBGREQ_PU,
444 372
445 /* Functions with pull-ups */
446 GPIO_FN_KEYIN0_PU,
447 GPIO_FN_KEYIN1_PU,
448 GPIO_FN_KEYIN2_PU,
449 GPIO_FN_KEYIN3_PU,
450 GPIO_FN_KEYIN4_PU,
451 GPIO_FN_KEYIN5_PU,
452 GPIO_FN_KEYIN6_PU,
453 GPIO_FN_KEYIN7_PU,
454 GPIO_FN_SDHICD0_PU,
455 GPIO_FN_SDHID0_0_PU,
456 GPIO_FN_SDHID0_1_PU,
457 GPIO_FN_SDHID0_2_PU,
458 GPIO_FN_SDHID0_3_PU,
459 GPIO_FN_SDHICMD0_PU,
460 GPIO_FN_SDHIWP0_PU,
461 GPIO_FN_SDHID1_0_PU,
462 GPIO_FN_SDHID1_1_PU,
463 GPIO_FN_SDHID1_2_PU,
464 GPIO_FN_SDHID1_3_PU,
465 GPIO_FN_SDHICMD1_PU,
466 GPIO_FN_SDHID2_0_PU,
467 GPIO_FN_SDHID2_1_PU,
468 GPIO_FN_SDHID2_2_PU,
469 GPIO_FN_SDHID2_3_PU,
470 GPIO_FN_SDHICMD2_PU,
471 GPIO_FN_MMCCMD0_PU,
472 GPIO_FN_MMCCMD1_PU,
473 GPIO_FN_MMCD0_0_PU,
474 GPIO_FN_MMCD0_1_PU,
475 GPIO_FN_MMCD0_2_PU,
476 GPIO_FN_MMCD0_3_PU,
477 GPIO_FN_MMCD0_4_PU,
478 GPIO_FN_MMCD0_5_PU,
479 GPIO_FN_MMCD0_6_PU,
480 GPIO_FN_MMCD0_7_PU,
481 GPIO_FN_FSIACK_PU,
482 GPIO_FN_FSIAILR_PU,
483 GPIO_FN_FSIAIBT_PU,
484 GPIO_FN_FSIAISLD_PU,
485
486 /* end of GPIO */ 373 /* end of GPIO */
487 GPIO_NR, 374 GPIO_NR,
488}; 375};
@@ -557,6 +444,21 @@ enum {
557#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) 444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
558#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) 445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
559 446
447extern void sh73a0_init_delay(void);
448extern void sh73a0_init_irq(void);
449extern void sh73a0_init_irq_dt(void);
450extern void sh73a0_map_io(void);
451extern void sh73a0_earlytimer_init(void);
452extern void sh73a0_add_early_devices(void);
453extern void sh73a0_add_standard_devices(void);
454extern void sh73a0_add_standard_devices_dt(void);
455extern void sh73a0_clock_init(void);
456extern void sh73a0_pinmux_init(void);
457extern void sh73a0_pm_init(void);
458extern struct clk sh73a0_extal1_clk;
459extern struct clk sh73a0_extal2_clk;
460extern struct clk sh73a0_extcki_clk;
461extern struct clk sh73a0_extalr_clk;
560extern struct smp_operations sh73a0_smp_ops; 462extern struct smp_operations sh73a0_smp_ops;
561 463
562#endif /* __ASM_SH73A0_H__ */ 464#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 9a69a31918ba..b741c8409a5a 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -18,620 +18,39 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h> 22#include <linux/io.h>
26#include <linux/sh_intc.h> 23#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h>
28#include <mach/irqs.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/*
33 * INTCA
34 */
35enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98};
99
100static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216};
217
218static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258};
259
260static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330};
331
332static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377};
378
379static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388/*
389 * INTCS
390 */
391enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443};
444
445static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499};
500
501static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508};
509
510static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558};
559
560/* Priority is needed for INTCA to receive the INTCS interrupt */
561static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595};
596
597static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608};
609
610static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616};
617
618static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619{
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624}
625 24
626void __init r8a7740_init_irq(void) 25void __init r8a7740_init_irq(void)
627{ 26{
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 27 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
629 28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
630 register_intc_controller(&intca_desc); 29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
631 register_intc_controller(&intca_irq_pins_desc); 30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
632 register_intc_controller(&intcs_desc); 31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
633 32
634 /* demux using INTEVTSA */ 33 /* initialize the Generic Interrupt Controller PL390 r0p0 */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); 34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux); 35
36 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
637} 56}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index a0826a48dd08..dec9293bb90d 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -410,11 +410,9 @@ static int sh7372_enter_a4s(struct cpuidle_device *dev,
410static struct cpuidle_driver sh7372_cpuidle_driver = { 410static struct cpuidle_driver sh7372_cpuidle_driver = {
411 .name = "sh7372_cpuidle", 411 .name = "sh7372_cpuidle",
412 .owner = THIS_MODULE, 412 .owner = THIS_MODULE,
413 .en_core_tk_irqen = 1,
414 .state_count = 5, 413 .state_count = 5,
415 .safe_state_index = 0, /* C1 */ 414 .safe_state_index = 0, /* C1 */
416 .states[0] = ARM_CPUIDLE_WFI_STATE, 415 .states[0] = ARM_CPUIDLE_WFI_STATE,
417 .states[0].enter = shmobile_enter_wfi,
418 .states[1] = { 416 .states[1] = {
419 .name = "C2", 417 .name = "C2",
420 .desc = "Core Standby Mode", 418 .desc = "Core Standby Mode",
@@ -450,12 +448,12 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
450 }, 448 },
451}; 449};
452 450
453static void sh7372_cpuidle_init(void) 451static void __init sh7372_cpuidle_init(void)
454{ 452{
455 shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver); 453 shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
456} 454}
457#else 455#else
458static void sh7372_cpuidle_init(void) {} 456static void __init sh7372_cpuidle_init(void) {}
459#endif 457#endif
460 458
461#ifdef CONFIG_SUSPEND 459#ifdef CONFIG_SUSPEND
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
new file mode 100644
index 000000000000..c5a75a7a508f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -0,0 +1,202 @@
1/*
2 * r8a73a4 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h>
26#include <mach/common.h>
27#include <mach/irqs.h>
28#include <mach/r8a73a4.h>
29#include <asm/mach/arch.h>
30
31static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
41#define SCIF_COMMON(scif_type, baseaddr, irq) \
42 .type = scif_type, \
43 .mapbase = baseaddr, \
44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
45 .scbrr_algo_id = SCBRR_ALGO_4, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
52}
53
54#define SCIFB_DATA(index, baseaddr, irq) \
55[index] = { \
56 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
57 .scscr = SCSCR_RE | SCSCR_TE, \
58}
59
60enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
61
62static const struct plat_sci_port scif[] = {
63 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
64 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
65 SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
66 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
67 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
68 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
69};
70
71static inline void r8a73a4_register_scif(int idx)
72{
73 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
74 sizeof(struct plat_sci_port));
75}
76
77static const struct renesas_irqc_config irqc0_data = {
78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
79};
80
81static const struct resource irqc0_resources[] = {
82 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
83 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
84 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
85 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
86 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
87 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
88 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
89 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
90 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
91 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
92 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
93 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
94 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
95 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
96 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
97 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
98 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
99 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
100 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
101 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
102 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
103 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
104 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
105 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
106 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
107 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
108 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
109 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
110 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
111 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
112 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
113 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
114 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
115};
116
117static const struct renesas_irqc_config irqc1_data = {
118 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
119};
120
121static const struct resource irqc1_resources[] = {
122 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
123 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
124 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
125 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
126 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
127 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
128 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
129 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
130 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
131 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
132 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
133 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
134 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
135 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
136 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
137 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
138 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
139 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
140 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
141 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
142 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
143 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
144 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
145 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
146 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
147 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
148 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
149};
150
151#define r8a73a4_register_irqc(idx) \
152 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
153 idx, irqc##idx##_resources, \
154 ARRAY_SIZE(irqc##idx##_resources), \
155 &irqc##idx##_data, \
156 sizeof(struct renesas_irqc_config))
157
158/* Thermal0 -> Thermal2 */
159static const struct resource thermal0_resources[] = {
160 DEFINE_RES_MEM(0xe61f0000, 0x14),
161 DEFINE_RES_MEM(0xe61f0100, 0x38),
162 DEFINE_RES_MEM(0xe61f0200, 0x38),
163 DEFINE_RES_MEM(0xe61f0300, 0x38),
164 DEFINE_RES_IRQ(gic_spi(69)),
165};
166
167#define r8a73a4_register_thermal() \
168 platform_device_register_simple("rcar_thermal", -1, \
169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources))
171
172void __init r8a73a4_add_standard_devices(void)
173{
174 r8a73a4_register_scif(SCIFA0);
175 r8a73a4_register_scif(SCIFA1);
176 r8a73a4_register_scif(SCIFB0);
177 r8a73a4_register_scif(SCIFB1);
178 r8a73a4_register_scif(SCIFB2);
179 r8a73a4_register_scif(SCIFB3);
180 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal();
183}
184
185#ifdef CONFIG_USE_OF
186void __init r8a73a4_add_standard_devices_dt(void)
187{
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
189}
190
191static const char *r8a73a4_boards_compat_dt[] __initdata = {
192 "renesas,r8a73a4",
193 NULL,
194};
195
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init,
198 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt,
201MACHINE_END
202#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 104b474a2ccf..326a4ab0bd5f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/serial_sci.h> 28#include <linux/serial_sci.h>
@@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device); 95 platform_device_register(&r8a7740_pfc_device);
95} 96}
96 97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
97/* SCIFA0 */ 218/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = { 219static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000, 220 .mapbase = 0xe6c40000,
@@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
101 .scscr = SCSCR_RE | SCSCR_TE, 222 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4, 223 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 224 .type = PORT_SCIFA,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), 225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
105}; 226};
106 227
107static struct platform_device scif0_device = { 228static struct platform_device scif0_device = {
@@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
119 .scscr = SCSCR_RE | SCSCR_TE, 240 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4, 241 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA, 242 .type = PORT_SCIFA,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), 243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
123}; 244};
124 245
125static struct platform_device scif1_device = { 246static struct platform_device scif1_device = {
@@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
137 .scscr = SCSCR_RE | SCSCR_TE, 258 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4, 259 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA, 260 .type = PORT_SCIFA,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), 261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
141}; 262};
142 263
143static struct platform_device scif2_device = { 264static struct platform_device scif2_device = {
@@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
155 .scscr = SCSCR_RE | SCSCR_TE, 276 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4, 277 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA, 278 .type = PORT_SCIFA,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), 279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
159}; 280};
160 281
161static struct platform_device scif3_device = { 282static struct platform_device scif3_device = {
@@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE, 294 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4, 295 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA, 296 .type = PORT_SCIFA,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), 297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
177}; 298};
178 299
179static struct platform_device scif4_device = { 300static struct platform_device scif4_device = {
@@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
191 .scscr = SCSCR_RE | SCSCR_TE, 312 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4, 313 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA, 314 .type = PORT_SCIFA,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), 315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
195}; 316};
196 317
197static struct platform_device scif5_device = { 318static struct platform_device scif5_device = {
@@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
209 .scscr = SCSCR_RE | SCSCR_TE, 330 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4, 331 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA, 332 .type = PORT_SCIFA,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), 333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
213}; 334};
214 335
215static struct platform_device scif6_device = { 336static struct platform_device scif6_device = {
@@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
227 .scscr = SCSCR_RE | SCSCR_TE, 348 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4, 349 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), 351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
231}; 352};
232 353
233static struct platform_device scif7_device = { 354static struct platform_device scif7_device = {
@@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
245 .scscr = SCSCR_RE | SCSCR_TE, 366 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4, 367 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB, 368 .type = PORT_SCIFB,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), 369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
249}; 370};
250 371
251static struct platform_device scifb_device = { 372static struct platform_device scifb_device = {
@@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
274 }, 395 },
275 [1] = { 396 [1] = {
276 .start = evt2irq(0x0b00), 397 .start = gic_spi(58),
277 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
278 }, 399 },
279}; 400};
@@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
304 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
305 }, 426 },
306 [1] = { 427 [1] = {
307 .start = intcs_evt2irq(0xe80), 428 .start = gic_spi(198),
308 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
309 }, 430 },
310}; 431};
@@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
334 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
335 }, 456 },
336 [1] = { 457 [1] = {
337 .start = intcs_evt2irq(0xea0), 458 .start = gic_spi(199),
338 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
339 }, 460 },
340}; 461};
@@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
364 .flags = IORESOURCE_MEM, 485 .flags = IORESOURCE_MEM,
365 }, 486 },
366 [1] = { 487 [1] = {
367 .start = intcs_evt2irq(0xec0), 488 .start = gic_spi(200),
368 .flags = IORESOURCE_IRQ, 489 .flags = IORESOURCE_IRQ,
369 }, 490 },
370}; 491};
@@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
411}; 532};
412 533
413static struct platform_device *r8a7740_early_devices[] __initdata = { 534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
414 &scif0_device, 539 &scif0_device,
415 &scif1_device, 540 &scif1_device,
416 &scif2_device, 541 &scif2_device,
@@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
525 }, 650 },
526 { 651 {
527 .name = "error_irq", 652 .name = "error_irq",
528 .start = evt2irq(0x20c0), 653 .start = gic_spi(34),
529 .end = evt2irq(0x20c0), 654 .end = gic_spi(34),
530 .flags = IORESOURCE_IRQ, 655 .flags = IORESOURCE_IRQ,
531 }, 656 },
532 { 657 {
533 /* IRQ for channels 0-5 */ 658 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000), 659 .start = gic_spi(28),
535 .end = evt2irq(0x20a0), 660 .end = gic_spi(33),
536 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
537 }, 662 },
538}; 663};
@@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
553 }, 678 },
554 { 679 {
555 .name = "error_irq", 680 .name = "error_irq",
556 .start = evt2irq(0x21c0), 681 .start = gic_spi(41),
557 .end = evt2irq(0x21c0), 682 .end = gic_spi(41),
558 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
559 }, 684 },
560 { 685 {
561 /* IRQ for channels 0-5 */ 686 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100), 687 .start = gic_spi(35),
563 .end = evt2irq(0x21a0), 688 .end = gic_spi(40),
564 .flags = IORESOURCE_IRQ, 689 .flags = IORESOURCE_IRQ,
565 }, 690 },
566}; 691};
@@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
581 }, 706 },
582 { 707 {
583 .name = "error_irq", 708 .name = "error_irq",
584 .start = evt2irq(0x22c0), 709 .start = gic_spi(48),
585 .end = evt2irq(0x22c0), 710 .end = gic_spi(48),
586 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
587 }, 712 },
588 { 713 {
589 /* IRQ for channels 0-5 */ 714 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200), 715 .start = gic_spi(42),
591 .end = evt2irq(0x22a0), 716 .end = gic_spi(47),
592 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
593 }, 718 },
594}; 719};
@@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
677 }, 802 },
678 { 803 {
679 /* IRQ for channels */ 804 /* IRQ for channels */
680 .start = evt2irq(0x0a00), 805 .start = gic_spi(49),
681 .end = evt2irq(0x0a00), 806 .end = gic_spi(49),
682 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
683 }, 808 },
684}; 809};
@@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
702 .flags = IORESOURCE_MEM, 827 .flags = IORESOURCE_MEM,
703 }, 828 },
704 [1] = { 829 [1] = {
705 .start = intcs_evt2irq(0xe00), 830 .start = gic_spi(201),
706 .end = intcs_evt2irq(0xe60), 831 .end = gic_spi(204),
707 .flags = IORESOURCE_IRQ, 832 .flags = IORESOURCE_IRQ,
708 }, 833 },
709}; 834};
@@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
716 .flags = IORESOURCE_MEM, 841 .flags = IORESOURCE_MEM,
717 }, 842 },
718 [1] = { 843 [1] = {
719 .start = evt2irq(0x780), /* IIC1_ALI1 */ 844 .start = gic_spi(70), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ 845 .end = gic_spi(73), /* IIC1_DTEI1 */
721 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
722 }, 847 },
723}; 848};
@@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
738 863
739static struct resource pmu_resources[] = { 864static struct resource pmu_resources[] = {
740 [0] = { 865 [0] = {
741 .start = evt2irq(0x19a0), 866 .start = gic_spi(83),
742 .end = evt2irq(0x19a0), 867 .end = gic_spi(83),
743 .flags = IORESOURCE_IRQ, 868 .flags = IORESOURCE_IRQ,
744 }, 869 },
745}; 870};
@@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
904 .map_io = r8a7740_map_io, 1029 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt, 1030 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq, 1031 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt, 1032 .init_machine = r8a7740_add_standard_devices_dt,
909 .dt_compat = r8a7740_boards_compat_dt, 1033 .dt_compat = r8a7740_boards_compat_dt,
910MACHINE_END 1034MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
new file mode 100644
index 000000000000..30b4a336308f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -0,0 +1,244 @@
1/*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/irqchip/arm-gic.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
28#include <linux/platform_device.h>
29#include <linux/irqchip.h>
30#include <linux/serial_sci.h>
31#include <linux/sh_timer.h>
32#include <mach/irqs.h>
33#include <mach/r8a7778.h>
34#include <mach/common.h>
35#include <asm/mach/arch.h>
36#include <asm/hardware/cache-l2x0.h>
37
38/* SCIF */
39#define SCIF_INFO(baseaddr, irq) \
40{ \
41 .mapbase = baseaddr, \
42 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
44 .scbrr_algo_id = SCBRR_ALGO_2, \
45 .type = PORT_SCIF, \
46 .irqs = SCIx_IRQ_MUXED(irq), \
47}
48
49static struct plat_sci_port scif_platform_data[] = {
50 SCIF_INFO(0xffe40000, gic_iid(0x66)),
51 SCIF_INFO(0xffe41000, gic_iid(0x67)),
52 SCIF_INFO(0xffe42000, gic_iid(0x68)),
53 SCIF_INFO(0xffe43000, gic_iid(0x69)),
54 SCIF_INFO(0xffe44000, gic_iid(0x6a)),
55 SCIF_INFO(0xffe45000, gic_iid(0x6b)),
56};
57
58/* TMU */
59static struct resource sh_tmu0_resources[] = {
60 DEFINE_RES_MEM(0xffd80008, 12),
61 DEFINE_RES_IRQ(gic_iid(0x40)),
62};
63
64static struct sh_timer_config sh_tmu0_platform_data = {
65 .name = "TMU00",
66 .channel_offset = 0x4,
67 .timer_bit = 0,
68 .clockevent_rating = 200,
69};
70
71static struct resource sh_tmu1_resources[] = {
72 DEFINE_RES_MEM(0xffd80014, 12),
73 DEFINE_RES_IRQ(gic_iid(0x41)),
74};
75
76static struct sh_timer_config sh_tmu1_platform_data = {
77 .name = "TMU01",
78 .channel_offset = 0x10,
79 .timer_bit = 1,
80 .clocksource_rating = 200,
81};
82
83/* Ether */
84static struct resource ether_resources[] = {
85 DEFINE_RES_MEM(0xfde00000, 0x400),
86 DEFINE_RES_IRQ(gic_iid(0x89)),
87};
88
89#define r8a7778_register_tmu(idx) \
90 platform_device_register_resndata( \
91 &platform_bus, "sh_tmu", idx, \
92 sh_tmu##idx##_resources, \
93 ARRAY_SIZE(sh_tmu##idx##_resources), \
94 &sh_tmu##idx##_platform_data, \
95 sizeof(sh_tmu##idx##_platform_data))
96
97void __init r8a7778_add_standard_devices(void)
98{
99 int i;
100
101#ifdef CONFIG_CACHE_L2X0
102 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
103 if (base) {
104 /*
105 * Early BRESP enable, Shared attribute override enable, 64K*16way
106 * don't call iounmap(base)
107 */
108 l2x0_init(base, 0x40470000, 0x82000fff);
109 }
110#endif
111
112 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
113 platform_device_register_data(&platform_bus, "sh-sci", i,
114 &scif_platform_data[i],
115 sizeof(struct plat_sci_port));
116
117 r8a7778_register_tmu(0);
118 r8a7778_register_tmu(1);
119}
120
121void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
122{
123 platform_device_register_resndata(&platform_bus, "sh_eth", -1,
124 ether_resources,
125 ARRAY_SIZE(ether_resources),
126 pdata, sizeof(*pdata));
127}
128
129static struct renesas_intc_irqpin_config irqpin_platform_data = {
130 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
131 .sense_bitfield_width = 2,
132};
133
134static struct resource irqpin_resources[] = {
135 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
136 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
137 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
138 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
139 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
140 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
141 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
142 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
143 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
144};
145
146void __init r8a7778_init_irq_extpin(int irlm)
147{
148 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
149 unsigned long tmp;
150
151 if (!icr0) {
152 pr_warn("r8a7778: unable to setup external irq pin mode\n");
153 return;
154 }
155
156 tmp = ioread32(icr0);
157 if (irlm)
158 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
159 else
160 tmp &= ~(1 << 23); /* IRL mode - not supported */
161 tmp |= (1 << 21); /* LVLMODE = 1 */
162 iowrite32(tmp, icr0);
163 iounmap(icr0);
164
165 if (irlm)
166 platform_device_register_resndata(
167 &platform_bus, "renesas_intc_irqpin", -1,
168 irqpin_resources, ARRAY_SIZE(irqpin_resources),
169 &irqpin_platform_data, sizeof(irqpin_platform_data));
170}
171
172#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
173#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
174
175#define INT2NTSR0 0x00018 /* 0xfe700018 */
176#define INT2NTSR1 0x0002c /* 0xfe70002c */
177static void __init r8a7778_init_irq_common(void)
178{
179 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
180
181 BUG_ON(!base);
182
183 /* route all interrupts to ARM */
184 __raw_writel(0x73ffffff, base + INT2NTSR0);
185 __raw_writel(0xffffffff, base + INT2NTSR1);
186
187 /* unmask all known interrupts in INTCS2 */
188 __raw_writel(0x08330773, base + INT2SMSKCR0);
189 __raw_writel(0x00311110, base + INT2SMSKCR1);
190
191 iounmap(base);
192}
193
194void __init r8a7778_init_irq(void)
195{
196 void __iomem *gic_dist_base;
197 void __iomem *gic_cpu_base;
198
199 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
200 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
201 BUG_ON(!gic_dist_base || !gic_cpu_base);
202
203 /* use GIC to handle interrupts */
204 gic_init(0, 29, gic_dist_base, gic_cpu_base);
205
206 r8a7778_init_irq_common();
207}
208
209void __init r8a7778_init_delay(void)
210{
211 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
212}
213
214#ifdef CONFIG_USE_OF
215void __init r8a7778_init_irq_dt(void)
216{
217 irqchip_init();
218 r8a7778_init_irq_common();
219}
220
221static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
222 {},
223};
224
225void __init r8a7778_add_standard_devices_dt(void)
226{
227 of_platform_populate(NULL, of_default_bus_match_table,
228 r8a7778_auxdata_lookup, NULL);
229}
230
231static const char *r8a7778_compat_dt[] __initdata = {
232 "renesas,r8a7778",
233 NULL,
234};
235
236DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
237 .init_early = r8a7778_init_delay,
238 .init_irq = r8a7778_init_irq_dt,
239 .init_machine = r8a7778_add_standard_devices_dt,
240 .init_time = shmobile_timer_init,
241 .dt_compat = r8a7778_compat_dt,
242MACHINE_END
243
244#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35e71a0..b0b394842ea5 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -1,8 +1,9 @@
1/* 1/*
2 * r8a7779 processor support 2 * r8a7779 processor support
3 * 3 *
4 * Copyright (C) 2011 Renesas Solutions Corp. 4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm 5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -22,6 +23,7 @@
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
23#include <linux/irq.h> 24#include <linux/irq.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
26#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_device.h> 27#include <linux/platform_device.h>
26#include <linux/delay.h> 28#include <linux/delay.h>
27#include <linux/input.h> 29#include <linux/input.h>
@@ -68,11 +70,6 @@ static struct resource r8a7779_pfc_resources[] = {
68 .end = 0xfffc023b, 70 .end = 0xfffc023b,
69 .flags = IORESOURCE_MEM, 71 .flags = IORESOURCE_MEM,
70 }, 72 },
71 [1] = {
72 .start = 0xffc40000,
73 .end = 0xffc46fff,
74 .flags = IORESOURCE_MEM,
75 }
76}; 73};
77 74
78static struct platform_device r8a7779_pfc_device = { 75static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +79,59 @@ static struct platform_device r8a7779_pfc_device = {
82 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 79 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
83}; 80};
84 81
82#define R8A7779_GPIO(idx, npins) \
83static struct resource r8a7779_gpio##idx##_resources[] = { \
84 [0] = { \
85 .start = 0xffc40000 + 0x1000 * (idx), \
86 .end = 0xffc4002b + 0x1000 * (idx), \
87 .flags = IORESOURCE_MEM, \
88 }, \
89 [1] = { \
90 .start = gic_iid(0xad + (idx)), \
91 .flags = IORESOURCE_IRQ, \
92 } \
93}; \
94 \
95static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
96 .gpio_base = 32 * (idx), \
97 .irq_base = 0, \
98 .number_of_pins = npins, \
99 .pctl_name = "pfc-r8a7779", \
100}; \
101 \
102static struct platform_device r8a7779_gpio##idx##_device = { \
103 .name = "gpio_rcar", \
104 .id = idx, \
105 .resource = r8a7779_gpio##idx##_resources, \
106 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
107 .dev = { \
108 .platform_data = &r8a7779_gpio##idx##_platform_data, \
109 }, \
110}
111
112R8A7779_GPIO(0, 32);
113R8A7779_GPIO(1, 32);
114R8A7779_GPIO(2, 32);
115R8A7779_GPIO(3, 32);
116R8A7779_GPIO(4, 32);
117R8A7779_GPIO(5, 32);
118R8A7779_GPIO(6, 9);
119
120static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
121 &r8a7779_pfc_device,
122 &r8a7779_gpio0_device,
123 &r8a7779_gpio1_device,
124 &r8a7779_gpio2_device,
125 &r8a7779_gpio3_device,
126 &r8a7779_gpio4_device,
127 &r8a7779_gpio5_device,
128 &r8a7779_gpio6_device,
129};
130
85void __init r8a7779_pinmux_init(void) 131void __init r8a7779_pinmux_init(void)
86{ 132{
87 platform_device_register(&r8a7779_pfc_device); 133 platform_add_devices(r8a7779_pinctrl_devices,
134 ARRAY_SIZE(r8a7779_pinctrl_devices));
88} 135}
89 136
90static struct plat_sci_port scif0_platform_data = { 137static struct plat_sci_port scif0_platform_data = {
@@ -347,6 +394,18 @@ static struct platform_device sata_device = {
347 }, 394 },
348}; 395};
349 396
397/* Ether */
398static struct resource ether_resources[] = {
399 {
400 .start = 0xfde00000,
401 .end = 0xfde003ff,
402 .flags = IORESOURCE_MEM,
403 }, {
404 .start = gic_iid(0xb4),
405 .flags = IORESOURCE_IRQ,
406 },
407};
408
350static struct platform_device *r8a7779_devices_dt[] __initdata = { 409static struct platform_device *r8a7779_devices_dt[] __initdata = {
351 &scif0_device, 410 &scif0_device,
352 &scif1_device, 411 &scif1_device,
@@ -382,6 +441,14 @@ void __init r8a7779_add_standard_devices(void)
382 ARRAY_SIZE(r8a7779_late_devices)); 441 ARRAY_SIZE(r8a7779_late_devices));
383} 442}
384 443
444void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
445{
446 platform_device_register_resndata(&platform_bus, "sh_eth", -1,
447 ether_resources,
448 ARRAY_SIZE(ether_resources),
449 pdata, sizeof(*pdata));
450}
451
385/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 452/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
386void __init __weak r8a7779_register_twd(void) { } 453void __init __weak r8a7779_register_twd(void) { }
387 454
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
new file mode 100644
index 000000000000..49de2d56f86d
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -0,0 +1,150 @@
1/*
2 * r8a7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/irq-renesas-irqc.h>
27#include <mach/common.h>
28#include <mach/irqs.h>
29#include <mach/r8a7790.h>
30#include <asm/mach/arch.h>
31
32static const struct resource pfc_resources[] = {
33 DEFINE_RES_MEM(0xe6060000, 0x250),
34 DEFINE_RES_MEM(0xe6050000, 0x5050),
35};
36
37void __init r8a7790_pinmux_init(void)
38{
39 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
40 ARRAY_SIZE(pfc_resources));
41}
42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \
44 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .irqs = SCIx_IRQ_MUXED(irq)
48
49#define SCIFA_DATA(index, baseaddr, irq) \
50[index] = { \
51 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
52 .scbrr_algo_id = SCBRR_ALGO_4, \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54}
55
56#define SCIFB_DATA(index, baseaddr, irq) \
57[index] = { \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
59 .scbrr_algo_id = SCBRR_ALGO_4, \
60 .scscr = SCSCR_RE | SCSCR_TE, \
61}
62
63#define SCIF_DATA(index, baseaddr, irq) \
64[index] = { \
65 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
66 .scbrr_algo_id = SCBRR_ALGO_2, \
67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
68}
69
70enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
71
72static const struct plat_sci_port scif[] = {
73 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
74 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
75 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
76 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
77 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
78 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
79 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
80 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
81};
82
83static inline void r8a7790_register_scif(int idx)
84{
85 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
86 sizeof(struct plat_sci_port));
87}
88
89static struct renesas_irqc_config irqc0_data = {
90 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
91};
92
93static struct resource irqc0_resources[] = {
94 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
95 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
99};
100
101#define r8a7790_register_irqc(idx) \
102 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
103 idx, irqc##idx##_resources, \
104 ARRAY_SIZE(irqc##idx##_resources), \
105 &irqc##idx##_data, \
106 sizeof(struct renesas_irqc_config))
107
108void __init r8a7790_add_standard_devices(void)
109{
110 r8a7790_register_scif(SCIFA0);
111 r8a7790_register_scif(SCIFA1);
112 r8a7790_register_scif(SCIFB0);
113 r8a7790_register_scif(SCIFB1);
114 r8a7790_register_scif(SCIFB2);
115 r8a7790_register_scif(SCIFA2);
116 r8a7790_register_scif(SCIF0);
117 r8a7790_register_scif(SCIF1);
118 r8a7790_register_irqc(0);
119}
120
121void __init r8a7790_timer_init(void)
122{
123 void __iomem *cntcr;
124
125 /* make sure arch timer is started by setting bit 0 of CNTCT */
126 cntcr = ioremap(0xe6080000, PAGE_SIZE);
127 iowrite32(1, cntcr);
128 iounmap(cntcr);
129
130 shmobile_timer_init();
131}
132
133#ifdef CONFIG_USE_OF
134void __init r8a7790_add_standard_devices_dt(void)
135{
136 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
137}
138
139static const char *r8a7790_boards_compat_dt[] __initdata = {
140 "renesas,r8a7790",
141 NULL,
142};
143
144DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
145 .init_irq = irqchip_init,
146 .init_machine = r8a7790_add_standard_devices_dt,
147 .init_time = r8a7790_timer_init,
148 .dt_compat = r8a7790_boards_compat_dt,
149MACHINE_END
150#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 8225c16b371b..e38691b4d0dd 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,7 +23,6 @@
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/irqchip/arm-gic.h>
27#include <mach/common.h> 26#include <mach/common.h>
28#include <mach/emev2.h> 27#include <mach/emev2.h>
29#include <asm/smp_plat.h> 28#include <asm/smp_plat.h>
@@ -31,11 +30,6 @@
31 30
32#define EMEV2_SCU_BASE 0x1e000000 31#define EMEV2_SCU_BASE 0x1e000000
33 32
34static void __cpuinit emev2_secondary_init(unsigned int cpu)
35{
36 gic_secondary_init(0);
37}
38
39static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) 33static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
40{ 34{
41 arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); 35 arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
@@ -69,6 +63,5 @@ static void __init emev2_smp_init_cpus(void)
69struct smp_operations emev2_smp_ops __initdata = { 63struct smp_operations emev2_smp_ops __initdata = {
70 .smp_init_cpus = emev2_smp_init_cpus, 64 .smp_init_cpus = emev2_smp_init_cpus,
71 .smp_prepare_cpus = emev2_smp_prepare_cpus, 65 .smp_prepare_cpus = emev2_smp_prepare_cpus,
72 .smp_secondary_init = emev2_secondary_init,
73 .smp_boot_secondary = emev2_boot_secondary, 66 .smp_boot_secondary = emev2_boot_secondary,
74}; 67};
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index ea4535a5c4e2..a853bf182ed5 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,7 +23,6 @@
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/irqchip/arm-gic.h>
27#include <mach/common.h> 26#include <mach/common.h>
28#include <mach/r8a7779.h> 27#include <mach/r8a7779.h>
29#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
@@ -82,11 +81,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
82 return ret ? ret : 1; 81 return ret ? ret : 1;
83} 82}
84 83
85static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
86{
87 gic_secondary_init(0);
88}
89
90static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) 84static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
91{ 85{
92 struct r8a7779_pm_ch *ch = NULL; 86 struct r8a7779_pm_ch *ch = NULL;
@@ -181,7 +175,6 @@ static int r8a7779_cpu_disable(unsigned int cpu)
181struct smp_operations r8a7779_smp_ops __initdata = { 175struct smp_operations r8a7779_smp_ops __initdata = {
182 .smp_init_cpus = r8a7779_smp_init_cpus, 176 .smp_init_cpus = r8a7779_smp_init_cpus,
183 .smp_prepare_cpus = r8a7779_smp_prepare_cpus, 177 .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
184 .smp_secondary_init = r8a7779_secondary_init,
185 .smp_boot_secondary = r8a7779_boot_secondary, 178 .smp_boot_secondary = r8a7779_boot_secondary,
186#ifdef CONFIG_HOTPLUG_CPU 179#ifdef CONFIG_HOTPLUG_CPU
187 .cpu_kill = r8a7779_cpu_kill, 180 .cpu_kill = r8a7779_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 5ae502b16437..496592b6c763 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,7 +23,6 @@
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/irqchip/arm-gic.h>
27#include <mach/common.h> 26#include <mach/common.h>
28#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
29#include <asm/smp_plat.h> 28#include <asm/smp_plat.h>
@@ -49,11 +48,6 @@ void __init sh73a0_register_twd(void)
49} 48}
50#endif 49#endif
51 50
52static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
53{
54 gic_secondary_init(0);
55}
56
57static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) 51static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
58{ 52{
59 cpu = cpu_logical_map(cpu); 53 cpu = cpu_logical_map(cpu);
@@ -110,14 +104,6 @@ static int sh73a0_cpu_kill(unsigned int cpu)
110 104
111static void sh73a0_cpu_die(unsigned int cpu) 105static void sh73a0_cpu_die(unsigned int cpu)
112{ 106{
113 /*
114 * The ARM MPcore does not issue a cache coherency request for the L1
115 * cache when powering off single CPUs. We must take care of this and
116 * further caches.
117 */
118 dsb();
119 flush_cache_all();
120
121 /* Set power off mode. This takes the CPU out of the MP cluster */ 107 /* Set power off mode. This takes the CPU out of the MP cluster */
122 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); 108 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
123 109
@@ -134,7 +120,6 @@ static int sh73a0_cpu_disable(unsigned int cpu)
134struct smp_operations sh73a0_smp_ops __initdata = { 120struct smp_operations sh73a0_smp_ops __initdata = {
135 .smp_init_cpus = sh73a0_smp_init_cpus, 121 .smp_init_cpus = sh73a0_smp_init_cpus,
136 .smp_prepare_cpus = sh73a0_smp_prepare_cpus, 122 .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
137 .smp_secondary_init = sh73a0_secondary_init,
138 .smp_boot_secondary = sh73a0_boot_secondary, 123 .smp_boot_secondary = sh73a0_boot_secondary,
139#ifdef CONFIG_HOTPLUG_CPU 124#ifdef CONFIG_HOTPLUG_CPU
140 .cpu_kill = sh73a0_cpu_kill, 125 .cpu_kill = sh73a0_cpu_kill,
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index 47d83f7a70b6..5d92b5dd486b 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -12,6 +12,8 @@
12#include <linux/suspend.h> 12#include <linux/suspend.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/cpu.h>
16
15#include <asm/io.h> 17#include <asm/io.h>
16#include <asm/system_misc.h> 18#include <asm/system_misc.h>
17 19
@@ -23,13 +25,13 @@ static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
23 25
24static int shmobile_suspend_begin(suspend_state_t state) 26static int shmobile_suspend_begin(suspend_state_t state)
25{ 27{
26 disable_hlt(); 28 cpu_idle_poll_ctrl(true);
27 return 0; 29 return 0;
28} 30}
29 31
30static void shmobile_suspend_end(void) 32static void shmobile_suspend_end(void)
31{ 33{
32 enable_hlt(); 34 cpu_idle_poll_ctrl(false);
33} 35}
34 36
35struct platform_suspend_ops shmobile_suspend_ops = { 37struct platform_suspend_ops shmobile_suspend_ops = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 02:25:33 -0400