15 files changed, 368 insertions, 48 deletions

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index cdefd7dcca79..403c939ddf99 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -61,9 +61,10 @@ config ARCH_R8A73A4
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -97,7 +98,6 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 1fbc39a14e25..af6dd39d3758 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -101,6 +101,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
+        .init_early     = r8a73a4_init_delay,
         .init_time      = shmobile_timer_init,
         .init_machine   = ape6evm_add_standard_devices,
         .dt_compat      = ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 78d92d34665d..f89f16650731 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -102,6 +102,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .init_machine   = lager_add_standard_devices,
         .dt_compat      = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 56dd0cfcddc7..5ac13ba71d54 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -40,7 +40,6 @@
 #define USIB2SCLKDIV 0x65c
 #define USIB3SCLKDIV 0x660
 #define STI_CLKSEL 0x688
-#define SMU_GENERAL_REG0 0x7c0
 
 /* not pretty, but hey */
 static void __iomem *smu_base;
@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs)
         iowrite32(value, smu_base + offs);
 }
 
-void emev2_set_boot_vector(unsigned long value)
-{
-        emev2_smu_write(value, SMU_GENERAL_REG0);
-}
-
 static struct clk_mapping smu_mapping = {
         .phys   = EMEV2_SMU_BASE,
         .len    = PAGE_SIZE,
@@ -205,18 +199,6 @@ static struct clk_lookup lookups[] = {
 void __init emev2_clock_init(void)
 {
         int k, ret = 0;
-        static int is_setup;
-
-        /* yuck, this is ugly as hell, but the non-smp case of clocks
-         * code is now designed to rely on ioremap() instead of static
-         * entity maps. in the case of smp we need access to the SMU
-         * register earlier than ioremap() is actually working without
-         * any static maps. to enable SMP in ugly but with dynamic
-         * mappings we have to call emev2_clock_init() from different
-         * places depending on UP and SMP...
-         */
-        if (is_setup++)
-                return;
 
         smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
         BUG_ON(!smu_base);
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe628b8a1..8ea5ef6c79cc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -30,10 +30,12 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA          0xE6150000
 #define FRQCRB          0xE6150004
+#define FRQCRC          0xE61500E0
 #define VCLKCR1         0xE6150008
 #define VCLKCR2         0xE615000C
 #define VCLKCR3         0xE615001C
@@ -52,6 +54,7 @@
 #define HSICKCR         0xE615026C
 #define M4CKCR          0xE6150098
 #define PLLECR          0xE61500D0
+#define PLL0CR          0xE61500D8
 #define PLL1CR          0xE6150028
 #define PLL2CR          0xE615002C
 #define PLL2SCR         0xE61501F4
@@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = {
                 .mapping        = &cpg_mapping,         \
         }
 
+PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 
 SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 
+static atomic_t frqcr_lock;
+
+/* Several clocks need to access FRQCRB, have to lock */
+static bool frqcr_kick_check(struct clk *clk)
+{
+        return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
+}
+
+static int frqcr_kick_do(struct clk *clk)
+{
+        int i;
+
+        /* set KICK bit in FRQCRB to update hardware setting, check success */
+        iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
+        for (i = 1000; i; i--)
+                if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
+                        cpu_relax();
+                else
+                        return 0;
+
+        return -ETIMEDOUT;
+}
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        void __iomem *frqcrc;
+        int ret;
+        unsigned long step, p_rate;
+        u32 val;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
+                ret = -EBUSY;
+                goto done;
+        }
+
+        /*
+         * Users are supposed to first call clk_set_rate() only with
+         * clk_round_rate() results. So, we don't fix wrong rates here, but
+         * guard against them anyway
+         */
+
+        p_rate = clk_get_rate(clk->parent);
+        if (rate == p_rate) {
+                val = 0;
+        } else {
+                step = DIV_ROUND_CLOSEST(p_rate, 32);
+
+                if (rate > p_rate || rate < step) {
+                        ret = -EINVAL;
+                        goto done;
+                }
+
+                val = 32 - rate / step;
+        }
+
+        frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+        iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+                  (val << clk->enable_bit), frqcrc);
+
+        ret = frqcr_kick_do(clk);
+
+done:
+        atomic_dec(&frqcr_lock);
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        /*
+         * theoretical rate = parent rate * multiplier / 32,
+         * where 1 <= multiplier <= 32. Therefore we should do
+         * multiplier = rate * 32 / parent rate
+         * rounded rate = parent rate * multiplier / 32.
+         * However, multiplication before division won't fit in 32 bits, so
+         * we sacrifice some precision by first dividing and then multiplying.
+         * To find the nearest divisor we calculate both and pick up the best
+         * one. This avoids 64-bit arithmetics.
+         */
+        unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+        rate_max = clk_get_rate(clk->parent);
+
+        /* output freq <= parent */
+        if (rate >= rate_max)
+                return rate_max;
+
+        step = DIV_ROUND_CLOSEST(rate_max, 32);
+        /* output freq >= parent / 32 */
+        if (step >= rate)
+                return step;
+
+        mul_min = rate / step;
+        mul_max = DIV_ROUND_UP(rate, step);
+        rate_min = step * mul_min;
+        if (mul_max == mul_min)
+                return rate_min;
+
+        rate_max = step * mul_max;
+
+        if (rate_max - rate <  rate - rate_min)
+                return rate_max;
+
+        return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+        unsigned int max = clk->div_mask + 1;
+        unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+                             clk->div_mask);
+
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+                (max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+        .recalc = zclk_recalc,
+        .set_rate = zclk_set_rate,
+        .round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+        .parent = &pll0_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 8,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
+/*
+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
+ * switching is only available in auto-DVFS mode
+ */
+SH_FIXED_RATIO_CLK(pll0_div2_clk,       pll0_clk,               div2);
+
+static struct clk z2_clk = {
+        .parent = &pll0_div2_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 0,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
@@ -195,22 +350,23 @@ static struct clk *main_clks[] = {
         &main_div2_clk,
         &fsiack_clk,
         &fsibck_clk,
+        &pll0_clk,
         &pll1_clk,
         &pll1_div2_clk,
         &pll2_clk,
         &pll2s_clk,
         &pll2h_clk,
+        &z_clk,
+        &pll0_div2_clk,
+        &z2_clk,
 };
 
 /* DIV4 */
 static void div4_kick(struct clk *clk)
 {
-        unsigned long value;
-
-        /* set KICK bit in FRQCRB to update hardware setting */
-        value = ioread32(CPG_MAP(FRQCRB));
-        value |= (1 << 31);
-        iowrite32(value, CPG_MAP(FRQCRB));
+        if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
+                frqcr_kick_do(clk);
+        atomic_dec(&frqcr_lock);
 }
 
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
-        MSTP522,
+        MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
+        MSTP411, MSTP410, MSTP409,
+        MSTP522, MSTP515,
         MSTP_NR
 };
 
@@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 0, 0), /* IIC2 */
         [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
         [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
         [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
+        [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 16, 0), /* IIC6 */
+        [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 17, 0), /* IIC7 */
+        [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 18, 0), /* IIC0 */
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP409] = SH_CLK_MSTP32(&main_div2_clk,       SMSTPCR4, 9, 0), /* IIC5 */
+        [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 11, 0), /* IIC3 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
+        [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR5, 15, 0), /* IIC8 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
         CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
 
+        /* CPU clock */
+        CLKDEV_DEV_ID("cpufreq-cpu0",           &z_clk),
+
         /* DIV6 */
         CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
         CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
@@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
@@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
+        CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
+        CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
+        CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
+        CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
+        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
+        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
+        CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
 
         /* for DT */
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void)
         int k, ret = 0;
         u32 ckscr;
 
+        atomic_set(&frqcr_lock, -1);
+
         reg = ioremap_nocache(CKSCR, PAGE_SIZE);
         BUG_ON(!reg);
         ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index f4265e52432c..c826bca4024e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -597,6 +597,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
+        CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 5d71313df52d..fc36d3db0b4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -24,6 +24,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7790.h>
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
@@ -42,16 +43,16 @@
  *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  */
 
-#define MD(nr)  (1 << nr)
-
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define SMSTPCR1 0xe6150134
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
-#define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
 #define SD3CKCR         0xE615007C
@@ -180,16 +181,23 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+        MSTP813,
         MSTP721, MSTP720,
         MSTP717, MSTP716,
+        MSTP522,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP124,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
@@ -203,8 +211,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
         [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
         [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
-        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -254,6 +261,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
@@ -266,6 +275,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
@@ -280,14 +290,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-        u32 mode;
+        u32 mode = r8a7790_read_mode_pins();
         int k, ret = 0;
 
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
         switch (mode & (MD(14) | MD(13))) {
         case 0:
                 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index b0ab4b72770a..c2eb7568d9be 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -5,7 +5,6 @@ extern void emev2_map_io(void);
 extern void emev2_init_delay(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
-extern void emev2_set_boot_vector(unsigned long value);
 
 #define EMEV2_GPIO_BASE 200
 #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103e32c9..144a85e29245 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -4,5 +4,6 @@
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
+void r8a73a4_init_delay(void);
 
 #endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index b34d19b5ca5c..56f375005fcd 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -42,6 +42,8 @@ enum {
         SHDMA_SLAVE_FSIB_TX,
         SHDMA_SLAVE_USBHS_TX,
         SHDMA_SLAVE_USBHS_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_MMCIF_RX,
 };
 
 extern void r8a7740_meram_workaround(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e61fa0d..7aaef409a059 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -4,6 +4,10 @@
 void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
+void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
 
+#define MD(nr) BIT(nr)
+u32 r8a7790_read_mode_pins(void);
+
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index a8c4e41bf27a..d533bd23865c 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
@@ -168,6 +169,25 @@ static const struct resource thermal0_resources[] = {
                                         thermal0_resources,             \
                                         ARRAY_SIZE(thermal0_resources))
 
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt10_resources[] = {
+        DEFINE_RES_MEM(0xe6130010, 0x0c),
+        DEFINE_RES_MEM(0xe6130000, 0x04),
+        DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a73a4_add_standard_devices(void)
 {
         r8a73a4_register_scif(SCIFA0);
@@ -179,11 +199,20 @@ void __init r8a73a4_add_standard_devices(void)
         r8a73a4_register_irqc(0);
         r8a73a4_register_irqc(1);
         r8a73a4_register_thermal();
+        r8a7790_register_cmt(10);
+}
+
+void __init r8a73a4_init_delay(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
+#endif
 }
 
 #ifdef CONFIG_USE_OF
 void __init r8a73a4_add_standard_devices_dt(void)
 {
+        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -193,6 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
+        .init_early     = r8a73a4_init_delay,
         .init_machine   = r8a73a4_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index ac29c2ee011f..84c5bb6d9725 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
                 .addr           = 0xfe1f0064,
                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xb5,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
         },
 };
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index b7e78b9a7fdf..4c96dad21195 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -21,9 +21,10 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <linux/serial_sci.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
@@ -148,6 +149,36 @@ static struct resource irqc0_resources[] __initdata = {
                                           &irqc##idx##_data,            \
                                           sizeof(struct renesas_irqc_config))
 
+static struct resource thermal_resources[] __initdata = {
+        DEFINE_RES_MEM(0xe61f0000, 0x14),
+        DEFINE_RES_MEM(0xe61f0100, 0x38),
+        DEFINE_RES_IRQ(gic_spi(69)),
+};
+
+#define r8a7790_register_thermal()                                      \
+        platform_device_register_simple("rcar_thermal", -1,             \
+                                        thermal_resources,              \
+                                        ARRAY_SIZE(thermal_resources))
+
+static struct sh_timer_config cmt00_platform_data = {
+        .name = "CMT00",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt00_resources[] = {
+        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a7790_add_standard_devices(void)
 {
         r8a7790_register_scif(SCIFA0);
@@ -161,20 +192,82 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_scif(HSCIF0);
         r8a7790_register_scif(HSCIF1);
         r8a7790_register_irqc(0);
+        r8a7790_register_thermal();
+        r8a7790_register_cmt(00);
 }
 
+#define MODEMR 0xe6160060
+
+u32 __init r8a7790_read_mode_pins(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        u32 mode;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        return mode;
+}
+
+#define CNTCR 0
+#define CNTFID0 0x20
+
 void __init r8a7790_timer_init(void)
 {
-        void __iomem *cntcr;
+#ifdef CONFIG_ARM_ARCH_TIMER
+        u32 mode = r8a7790_read_mode_pins();
+        void __iomem *base;
+        int extal_mhz = 0;
+        u32 freq;
+
+        /* At Linux boot time the r8a7790 arch timer comes up
+         * with the counter disabled. Moreover, it may also report
+         * a potentially incorrect fixed 13 MHz frequency. To be
+         * correct these registers need to be updated to use the
+         * frequency EXTAL / 2 which can be determined by the MD pins.
+         */
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                extal_mhz = 15;
+                break;
+        case MD(13):
+                extal_mhz = 20;
+                break;
+        case MD(14):
+                extal_mhz = 26;
+                break;
+        case MD(13) | MD(14):
+                extal_mhz = 30;
+                break;
+        }
 
-        /* make sure arch timer is started by setting bit 0 of CNTCT */
-        cntcr = ioremap(0xe6080000, PAGE_SIZE);
-        iowrite32(1, cntcr);
-        iounmap(cntcr);
+        /* The arch timer frequency equals EXTAL / 2 */
+        freq = extal_mhz * (1000000 / 2);
+
+        /* Remap "armgcnt address map" space */
+        base = ioremap(0xe6080000, PAGE_SIZE);
+
+        /* Update registers with correct frequency */
+        iowrite32(freq, base + CNTFID0);
+        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+        /* make sure arch timer is started by setting bit 0 of CNTCR */
+        iowrite32(1, base + CNTCR);
+        iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
 
         shmobile_timer_init();
 }
 
+void __init r8a7790_init_delay(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
+#endif
+}
+
 #ifdef CONFIG_USE_OF
 
 static const char *r8a7790_boards_compat_dt[] __initdata = {
@@ -183,6 +276,7 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 1fcd607d64ad..78e84c582453 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -29,6 +29,8 @@
 #include <asm/smp_scu.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
+#define EMEV2_SMU_BASE 0xe0110000
+#define SMU_GENERAL_REG0 0x7c0
 
 static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
@@ -38,13 +40,18 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void __iomem *smu;
+
         /* setup EMEV2 specific SCU base, enable */
         shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
         scu_enable(shmobile_scu_base);
 
         /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
-        emev2_clock_init(); /* need ioremapped SMU */
-        emev2_set_boot_vector(__pa(shmobile_boot_vector));
+        smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
+        if (smu) {
+                iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
+                iounmap(smu);
+        }
         shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
         shmobile_boot_arg = (unsigned long)shmobile_scu_base;