diff options
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r-- | arch/arm/mach-shmobile/intc-sh7372.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 3b28743c77eb..739315e30eb9 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c | |||
@@ -379,7 +379,7 @@ enum { | |||
379 | /* BBIF2 */ | 379 | /* BBIF2 */ |
380 | VPU, | 380 | VPU, |
381 | TSIF1, | 381 | TSIF1, |
382 | _3DG_SGX530, | 382 | /* 3DG */ |
383 | _2DDMAC, | 383 | _2DDMAC, |
384 | IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, | 384 | IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, |
385 | IPMMU_IPMMUR, IPMMU_IPMMUR2, | 385 | IPMMU_IPMMUR, IPMMU_IPMMUR2, |
@@ -436,7 +436,7 @@ static struct intc_vect intcs_vectors[] = { | |||
436 | /* BBIF2 */ | 436 | /* BBIF2 */ |
437 | INTCS_VECT(VPU, 0x980), | 437 | INTCS_VECT(VPU, 0x980), |
438 | INTCS_VECT(TSIF1, 0x9a0), | 438 | INTCS_VECT(TSIF1, 0x9a0), |
439 | INTCS_VECT(_3DG_SGX530, 0x9e0), | 439 | /* 3DG */ |
440 | INTCS_VECT(_2DDMAC, 0xa00), | 440 | INTCS_VECT(_2DDMAC, 0xa00), |
441 | INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), | 441 | INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), |
442 | INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), | 442 | INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), |
@@ -521,7 +521,7 @@ static struct intc_mask_reg intcs_mask_registers[] = { | |||
521 | RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, | 521 | RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, |
522 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ | 522 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ |
523 | { 0, 0, MSIOF, 0, | 523 | { 0, 0, MSIOF, 0, |
524 | _3DG_SGX530, 0, 0, 0 } }, | 524 | 0, 0, 0, 0 } }, |
525 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ | 525 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ |
526 | { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, | 526 | { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, |
527 | 0, 0, 0, 0 } }, | 527 | 0, 0, 0, 0 } }, |
@@ -561,7 +561,6 @@ static struct intc_prio_reg intcs_prio_registers[] = { | |||
561 | TMU_TUNI2, TSIF1 } }, | 561 | TMU_TUNI2, TSIF1 } }, |
562 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, | 562 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, |
563 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, | 563 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, |
564 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } }, | ||
565 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, | 564 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, |
566 | { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, | 565 | { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, |
567 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, | 566 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, |