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-rw-r--r--arch/arm/mach-shmobile/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c181
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c2
-rw-r--r--arch/arm/mach-shmobile/board-g3evm.c1
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c7
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c40
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-ap4evb.txt10
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-mackerel.txt10
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h29
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmcif.h18
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c11
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c5
14 files changed, 330 insertions, 29 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4d1b4c5c9389..0c8f6cf3e948 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -60,6 +60,8 @@ endchoice
60 60
61config MACH_AG5EVM 61config MACH_AG5EVM
62 bool "AG5EVM board" 62 bool "AG5EVM board"
63 select ARCH_REQUIRE_GPIOLIB
64 select SH_LCD_MIPI_DSI
63 depends on ARCH_SH73A0 65 depends on ARCH_SH73A0
64 66
65config MACH_MACKEREL 67config MACH_MACKEREL
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index c18a740a4159..4303a86e6e38 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -34,9 +34,10 @@
34#include <linux/input/sh_keysc.h> 34#include <linux/input/sh_keysc.h>
35#include <linux/mmc/host.h> 35#include <linux/mmc/host.h>
36#include <linux/mmc/sh_mmcif.h> 36#include <linux/mmc/sh_mmcif.h>
37 37#include <linux/sh_clk.h>
38#include <video/sh_mobile_lcdc.h>
39#include <video/sh_mipi_dsi.h>
38#include <sound/sh_fsi.h> 40#include <sound/sh_fsi.h>
39
40#include <mach/hardware.h> 41#include <mach/hardware.h>
41#include <mach/sh73a0.h> 42#include <mach/sh73a0.h>
42#include <mach/common.h> 43#include <mach/common.h>
@@ -183,11 +184,165 @@ static struct platform_device mmc_device = {
183 .resource = sh_mmcif_resources, 184 .resource = sh_mmcif_resources,
184}; 185};
185 186
187/* IrDA */
188static struct resource irda_resources[] = {
189 [0] = {
190 .start = 0xE6D00000,
191 .end = 0xE6D01FD4 - 1,
192 .flags = IORESOURCE_MEM,
193 },
194 [1] = {
195 .start = gic_spi(95),
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device irda_device = {
201 .name = "sh_irda",
202 .id = 0,
203 .resource = irda_resources,
204 .num_resources = ARRAY_SIZE(irda_resources),
205};
206
207static unsigned char lcd_backlight_seq[3][2] = {
208 { 0x04, 0x07 },
209 { 0x23, 0x80 },
210 { 0x03, 0x01 },
211};
212
213static void lcd_backlight_on(void)
214{
215 struct i2c_adapter *a;
216 struct i2c_msg msg;
217 int k;
218
219 a = i2c_get_adapter(1);
220 for (k = 0; a && k < 3; k++) {
221 msg.addr = 0x6d;
222 msg.buf = &lcd_backlight_seq[k][0];
223 msg.len = 2;
224 msg.flags = 0;
225 if (i2c_transfer(a, &msg, 1) != 1)
226 break;
227 }
228}
229
230static void lcd_backlight_reset(void)
231{
232 gpio_set_value(GPIO_PORT235, 0);
233 mdelay(24);
234 gpio_set_value(GPIO_PORT235, 1);
235}
236
237static void lcd_on(void *board_data, struct fb_info *info)
238{
239 lcd_backlight_on();
240}
241
242static void lcd_off(void *board_data)
243{
244 lcd_backlight_reset();
245}
246
247/* LCDC0 */
248static const struct fb_videomode lcdc0_modes[] = {
249 {
250 .name = "R63302(QHD)",
251 .xres = 544,
252 .yres = 961,
253 .left_margin = 72,
254 .right_margin = 600,
255 .hsync_len = 16,
256 .upper_margin = 8,
257 .lower_margin = 8,
258 .vsync_len = 2,
259 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
260 },
261};
262
263static struct sh_mobile_lcdc_info lcdc0_info = {
264 .clock_source = LCDC_CLK_PERIPHERAL,
265 .ch[0] = {
266 .chan = LCDC_CHAN_MAINLCD,
267 .interface_type = RGB24,
268 .clock_divider = 1,
269 .flags = LCDC_FLAGS_DWPOL,
270 .lcd_size_cfg.width = 44,
271 .lcd_size_cfg.height = 79,
272 .bpp = 16,
273 .lcd_cfg = lcdc0_modes,
274 .num_cfg = ARRAY_SIZE(lcdc0_modes),
275 .board_cfg = {
276 .display_on = lcd_on,
277 .display_off = lcd_off,
278 },
279 }
280};
281
282static struct resource lcdc0_resources[] = {
283 [0] = {
284 .name = "LCDC0",
285 .start = 0xfe940000, /* P4-only space */
286 .end = 0xfe943fff,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = intcs_evt2irq(0x580),
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device lcdc0_device = {
296 .name = "sh_mobile_lcdc_fb",
297 .num_resources = ARRAY_SIZE(lcdc0_resources),
298 .resource = lcdc0_resources,
299 .id = 0,
300 .dev = {
301 .platform_data = &lcdc0_info,
302 .coherent_dma_mask = ~0,
303 },
304};
305
306/* MIPI-DSI */
307static struct resource mipidsi0_resources[] = {
308 [0] = {
309 .start = 0xfeab0000,
310 .end = 0xfeab3fff,
311 .flags = IORESOURCE_MEM,
312 },
313 [1] = {
314 .start = 0xfeab4000,
315 .end = 0xfeab7fff,
316 .flags = IORESOURCE_MEM,
317 },
318};
319
320static struct sh_mipi_dsi_info mipidsi0_info = {
321 .data_format = MIPI_RGB888,
322 .lcd_chan = &lcdc0_info.ch[0],
323 .vsynw_offset = 20,
324 .clksrc = 1,
325 .flags = SH_MIPI_DSI_HSABM,
326};
327
328static struct platform_device mipidsi0_device = {
329 .name = "sh-mipi-dsi",
330 .num_resources = ARRAY_SIZE(mipidsi0_resources),
331 .resource = mipidsi0_resources,
332 .id = 0,
333 .dev = {
334 .platform_data = &mipidsi0_info,
335 },
336};
337
186static struct platform_device *ag5evm_devices[] __initdata = { 338static struct platform_device *ag5evm_devices[] __initdata = {
187 &eth_device, 339 &eth_device,
188 &keysc_device, 340 &keysc_device,
189 &fsi_device, 341 &fsi_device,
190 &mmc_device, 342 &mmc_device,
343 &irda_device,
344 &lcdc0_device,
345 &mipidsi0_device,
191}; 346};
192 347
193static struct map_desc ag5evm_io_desc[] __initdata = { 348static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -224,6 +379,8 @@ void __init ag5evm_init_irq(void)
224 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A); 379 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
225} 380}
226 381
382#define DSI0PHYCR 0xe615006c
383
227static void __init ag5evm_init(void) 384static void __init ag5evm_init(void)
228{ 385{
229 sh73a0_pinmux_init(); 386 sh73a0_pinmux_init();
@@ -287,6 +444,26 @@ static void __init ag5evm_init(void)
287 gpio_request(GPIO_FN_FSIAISLD, NULL); 444 gpio_request(GPIO_FN_FSIAISLD, NULL);
288 gpio_request(GPIO_FN_FSIAOSLD, NULL); 445 gpio_request(GPIO_FN_FSIAOSLD, NULL);
289 446
447 /* IrDA */
448 gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
449 gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
450 gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
451
452 /* LCD panel */
453 gpio_request(GPIO_PORT217, NULL); /* RESET */
454 gpio_direction_output(GPIO_PORT217, 0);
455 mdelay(1);
456 gpio_set_value(GPIO_PORT217, 1);
457 mdelay(100);
458
459 /* LCD backlight controller */
460 gpio_request(GPIO_PORT235, NULL); /* RESET */
461 gpio_direction_output(GPIO_PORT235, 0);
462 lcd_backlight_reset();
463
464 /* MIPI-DSI clock setup */
465 __raw_writel(0x2a809010, DSI0PHYCR);
466
290#ifdef CONFIG_CACHE_L2X0 467#ifdef CONFIG_CACHE_L2X0
291 /* Shared attribute override enable, 64K*8way */ 468 /* Shared attribute override enable, 64K*8way */
292 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff); 469 l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 3cf0951caa2d..81d6536552a9 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1303,7 +1303,7 @@ static void __init ap4evb_init(void)
1303 1303
1304 lcdc_info.clock_source = LCDC_CLK_BUS; 1304 lcdc_info.clock_source = LCDC_CLK_BUS;
1305 lcdc_info.ch[0].interface_type = RGB18; 1305 lcdc_info.ch[0].interface_type = RGB18;
1306 lcdc_info.ch[0].clock_divider = 2; 1306 lcdc_info.ch[0].clock_divider = 3;
1307 lcdc_info.ch[0].flags = 0; 1307 lcdc_info.ch[0].flags = 0;
1308 lcdc_info.ch[0].lcd_size_cfg.width = 152; 1308 lcdc_info.ch[0].lcd_size_cfg.width = 152;
1309 lcdc_info.ch[0].lcd_size_cfg.height = 91; 1309 lcdc_info.ch[0].lcd_size_cfg.height = 91;
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 686b304a7708..ef4613b993a2 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -347,7 +347,6 @@ static void __init g3evm_init(void)
347 gpio_request(GPIO_FN_IRDA_OUT, NULL); 347 gpio_request(GPIO_FN_IRDA_OUT, NULL);
348 gpio_request(GPIO_FN_IRDA_IN, NULL); 348 gpio_request(GPIO_FN_IRDA_IN, NULL);
349 gpio_request(GPIO_FN_IRDA_FIRSEL, NULL); 349 gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
350 set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
351 350
352 sh7367_add_standard_devices(); 351 sh7367_add_standard_devices();
353 352
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7b15d21f0f68..1657eac5dde2 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -169,9 +169,8 @@
169 * SW1 | SW33 169 * SW1 | SW33
170 * | bit1 | bit2 | bit3 | bit4 170 * | bit1 | bit2 | bit3 | bit4
171 * -------------+------+------+------+------- 171 * -------------+------+------+------+-------
172 * MMC0 OFF | OFF | ON | ON | X 172 * MMC0 OFF | OFF | X | ON | X (Use MMCIF)
173 * MMC1 ON | OFF | ON | X | ON 173 * SDHI1 OFF | ON | X | OFF | X (Use MFD_SH_MOBILE_SDHI)
174 * SDHI1 OFF | ON | X | OFF | ON
175 * 174 *
176 */ 175 */
177 176
@@ -304,7 +303,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
304 .lcd_cfg = mackerel_lcdc_modes, 303 .lcd_cfg = mackerel_lcdc_modes,
305 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes), 304 .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
306 .interface_type = RGB24, 305 .interface_type = RGB24,
307 .clock_divider = 2, 306 .clock_divider = 3,
308 .flags = 0, 307 .flags = 0,
309 .lcd_size_cfg.width = 152, 308 .lcd_size_cfg.width = 152,
310 .lcd_size_cfg.height = 91, 309 .lcd_size_cfg.height = 91,
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 9aa8d68d1a9c..e9731b5a73ed 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -234,7 +234,9 @@ static int pllc2_set_rate(struct clk *clk, unsigned long rate)
234 234
235 value = __raw_readl(PLLC2CR) & ~(0x3f << 24); 235 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
236 236
237 __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR); 237 __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
238
239 clk->rate = clk->freq_table[idx].frequency;
238 240
239 return 0; 241 return 0;
240} 242}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 720a71433be6..7e58904c1c8c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
118{ 118{
119 unsigned long mult = 1; 119 unsigned long mult = 1;
120 120
121 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) 121 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
122 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); 122 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
123 /* handle CFG bit for PLL1 and PLL2 */
124 switch (clk->enable_bit) {
125 case 1:
126 case 2:
127 if (__raw_readl(clk->enable_reg) & (1 << 20))
128 mult *= 2;
129 }
130 }
123 131
124 return clk->parent->rate * mult; 132 return clk->parent->rate * mult;
125} 133}
@@ -212,7 +220,7 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
212static struct clk div4_clks[DIV4_NR] = { 220static struct clk div4_clks[DIV4_NR] = {
213 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT), 221 [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
214 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT), 222 [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
215 [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), 223 [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
216 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), 224 [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
217 [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0), 225 [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
218 [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0), 226 [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
@@ -255,10 +263,10 @@ static struct clk div6_clks[DIV6_NR] = {
255}; 263};
256 264
257enum { MSTP001, 265enum { MSTP001,
258 MSTP125, MSTP116, 266 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
259 MSTP219, 267 MSTP219,
260 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 268 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
261 MSTP331, MSTP329, MSTP323, MSTP312, 269 MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
262 MSTP411, MSTP410, MSTP403, 270 MSTP411, MSTP410, MSTP403,
263 MSTP_NR }; 271 MSTP_NR };
264 272
@@ -267,8 +275,14 @@ enum { MSTP001,
267 275
268static struct clk mstp_clks[MSTP_NR] = { 276static struct clk mstp_clks[MSTP_NR] = {
269 [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */ 277 [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
278 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
279 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
280 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
281 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
270 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ 282 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
283 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
271 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ 284 [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
285 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
272 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ 286 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
273 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ 287 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
274 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ 288 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
@@ -279,6 +293,7 @@ static struct clk mstp_clks[MSTP_NR] = {
279 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ 293 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
280 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ 294 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
281 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ 295 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
296 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
282 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ 297 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
283 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ 298 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
284 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ 299 [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
@@ -288,16 +303,32 @@ static struct clk mstp_clks[MSTP_NR] = {
288 303
289#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 304#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
290#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 305#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
306#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
291 307
292static struct clk_lookup lookups[] = { 308static struct clk_lookup lookups[] = {
293 /* main clocks */ 309 /* main clocks */
294 CLKDEV_CON_ID("r_clk", &r_clk), 310 CLKDEV_CON_ID("r_clk", &r_clk),
295 311
312 /* DIV6 clocks */
313 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
314 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
315 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
316 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
317 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
318 CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
319 CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
320
296 /* MSTP32 clocks */ 321 /* MSTP32 clocks */
297 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ 322 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
323 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
324 CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
325 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
326 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
298 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ 327 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
299 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ 328 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
329 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
300 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ 330 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
331 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
301 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ 332 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
302 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 333 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
303 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ 334 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
@@ -308,6 +339,7 @@ static struct clk_lookup lookups[] = {
308 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ 339 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
309 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ 340 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
310 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ 341 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
342 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
311 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ 343 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
312 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ 344 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
313 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ 345 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
6EW 0xE6020004, 0xA500 6EW 0xE6020004, 0xA500
7EW 0xE6030004, 0xA500 7EW 0xE6030004, 0xA500
8 8
9DD 0x01001000, 0x01001000
10
11LIST "GPIO Setting" 9LIST "GPIO Setting"
12EB 0xE6051013, 0xA2 10EB 0xE6051013, 0xA2
13 11
14LIST "CPG" 12LIST "CPG"
15ED 0xE6150080, 0x00000180
16ED 0xE61500C0, 0x00000002 13ED 0xE61500C0, 0x00000002
17 14
18WAIT 1, 0xFE40009C 15WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
37 34
38WAIT 1, 0xFE40009C 35WAIT 1, 0xFE40009C
39 36
37LIST "SUB/USBClk"
38ED 0xE6150080, 0x00000180
39
40LIST "BSC" 40LIST "BSC"
41ED 0xFEC10000, 0x00E0001B 41ED 0xFEC10000, 0x00E0001B
42 42
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
53ED 0xFE40004C, 0x00110209 53ED 0xFE40004C, 0x00110209
54ED 0xFE400010, 0x00000087 54ED 0xFE400010, 0x00000087
55 55
56WAIT 10, 0xFE40009C 56WAIT 30, 0xFE40009C
57 57
58ED 0xFE400084, 0x0000003F 58ED 0xFE400084, 0x0000003F
59EB 0xFE500000, 0x00 59EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
84 84
85WAIT 1, 0xFE40009C 85WAIT 1, 0xFE40009C
86 86
87ED 0xE6150354, 0x00000002 87ED 0xFE400354, 0x01AD8002
88 88
89LIST "SCIF0 - Serial port for earlyprintk" 89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0x11 90EB 0xE6053098, 0x11
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index efd3687ba190..3029aba38688 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -6,13 +6,10 @@ LIST "RWT Setting"
6EW 0xE6020004, 0xA500 6EW 0xE6020004, 0xA500
7EW 0xE6030004, 0xA500 7EW 0xE6030004, 0xA500
8 8
9DD 0x01001000, 0x01001000
10
11LIST "GPIO Setting" 9LIST "GPIO Setting"
12EB 0xE6051013, 0xA2 10EB 0xE6051013, 0xA2
13 11
14LIST "CPG" 12LIST "CPG"
15ED 0xE6150080, 0x00000180
16ED 0xE61500C0, 0x00000002 13ED 0xE61500C0, 0x00000002
17 14
18WAIT 1, 0xFE40009C 15WAIT 1, 0xFE40009C
@@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
37 34
38WAIT 1, 0xFE40009C 35WAIT 1, 0xFE40009C
39 36
37LIST "SUB/USBClk"
38ED 0xE6150080, 0x00000180
39
40LIST "BSC" 40LIST "BSC"
41ED 0xFEC10000, 0x00E0001B 41ED 0xFEC10000, 0x00E0001B
42 42
@@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
53ED 0xFE40004C, 0x00110209 53ED 0xFE40004C, 0x00110209
54ED 0xFE400010, 0x00000087 54ED 0xFE400010, 0x00000087
55 55
56WAIT 10, 0xFE40009C 56WAIT 30, 0xFE40009C
57 57
58ED 0xFE400084, 0x0000003F 58ED 0xFE400084, 0x0000003F
59EB 0xFE500000, 0x00 59EB 0xFE500000, 0x00
@@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
84 84
85WAIT 1, 0xFE40009C 85WAIT 1, 0xFE40009C
86 86
87ED 0xE6150354, 0x00000002 87ED 0xFE400354, 0x01AD8002
88 88
89LIST "SCIF0 - Serial port for earlyprintk" 89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0x11 90EB 0xE6053098, 0x11
diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h
new file mode 100644
index 000000000000..a8d02be8d2b6
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/mmcif-ap4eb.h
@@ -0,0 +1,29 @@
1#ifndef MMCIF_AP4EB_H
2#define MMCIF_AP4EB_H
3
4#define PORT185CR (void __iomem *)0xe60520b9
5#define PORT186CR (void __iomem *)0xe60520ba
6#define PORT187CR (void __iomem *)0xe60520bb
7#define PORT188CR (void __iomem *)0xe60520bc
8
9#define PORTR191_160DR (void __iomem *)0xe6056014
10
11static inline void mmcif_init_progress(void)
12{
13 /* Initialise LEDS1-4
14 * registers: PORT185CR-PORT188CR (LED1-LED4 Control)
15 * value: 0x10 - enable output
16 */
17 __raw_writeb(0x10, PORT185CR);
18 __raw_writeb(0x10, PORT186CR);
19 __raw_writeb(0x10, PORT187CR);
20 __raw_writeb(0x10, PORT188CR);
21}
22
23static inline void mmcif_update_progress(int n)
24{
25 __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) |
26 (1 << (25 + n)), PORTR191_160DR);
27}
28
29#endif /* MMCIF_AP4EB_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h
new file mode 100644
index 000000000000..4b4f6949a868
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/mmcif-mackerel.h
@@ -0,0 +1,39 @@
1#ifndef MMCIF_MACKEREL_H
2#define MMCIF_MACKEREL_H
3
4#define PORT0CR (void __iomem *)0xe6051000
5#define PORT1CR (void __iomem *)0xe6051001
6#define PORT2CR (void __iomem *)0xe6051002
7#define PORT159CR (void __iomem *)0xe605009f
8
9#define PORTR031_000DR (void __iomem *)0xe6055000
10#define PORTL159_128DR (void __iomem *)0xe6054010
11
12static inline void mmcif_init_progress(void)
13{
14 /* Initialise LEDS0-3
15 * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control)
16 * value: 0x10 - enable output
17 */
18 __raw_writeb(0x10, PORT0CR);
19 __raw_writeb(0x10, PORT1CR);
20 __raw_writeb(0x10, PORT2CR);
21 __raw_writeb(0x10, PORT159CR);
22}
23
24static inline void mmcif_update_progress(int n)
25{
26 unsigned a = 0, b = 0;
27
28 if (n < 3)
29 a = 1 << n;
30 else
31 b = 1 << 31;
32
33 __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a,
34 PORTR031_000DR);
35 __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b,
36 PORTL159_128DR);
37}
38
39#endif /* MMCIF_MACKEREL_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmcif.h b/arch/arm/mach-shmobile/include/mach/mmcif.h
new file mode 100644
index 000000000000..f4dc3279cf03
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/mmcif.h
@@ -0,0 +1,18 @@
1#ifndef MMCIF_H
2#define MMCIF_H
3
4/**************************************************
5 *
6 * board specific settings
7 *
8 **************************************************/
9
10#ifdef CONFIG_MACH_AP4EVB
11#include "mach/mmcif-ap4eb.h"
12#elif CONFIG_MACH_MACKEREL
13#include "mach/mmcif-mackerel.h"
14#else
15#error "unsupported board."
16#endif
17
18#endif /* MMCIF_H */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index f78a1ead71a5..ca5f9d17b39a 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -365,6 +365,7 @@ static struct intc_desc intca_desc __initdata = {
365 365
366enum { 366enum {
367 UNUSED_INTCS = 0, 367 UNUSED_INTCS = 0,
368 ENABLED_INTCS,
368 369
369 INTCS, 370 INTCS,
370 371
@@ -413,7 +414,7 @@ enum {
413 CMT4, 414 CMT4,
414 DSITX1_DSITX1_0, 415 DSITX1_DSITX1_0,
415 DSITX1_DSITX1_1, 416 DSITX1_DSITX1_1,
416 /* MFIS2 */ 417 MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
417 CPORTS2R, 418 CPORTS2R,
418 /* CEC */ 419 /* CEC */
419 JPU6E, 420 JPU6E,
@@ -477,7 +478,7 @@ static struct intc_vect intcs_vectors[] = {
477 INTCS_VECT(CMT4, 0x1980), 478 INTCS_VECT(CMT4, 0x1980),
478 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), 479 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
479 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), 480 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
480 /* MFIS2 */ 481 INTCS_VECT(MFIS2_INTCS, 0x1a00),
481 INTCS_VECT(CPORTS2R, 0x1a20), 482 INTCS_VECT(CPORTS2R, 0x1a20),
482 /* CEC */ 483 /* CEC */
483 INTCS_VECT(JPU6E, 0x1a80), 484 INTCS_VECT(JPU6E, 0x1a80),
@@ -543,7 +544,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
543 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 544 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
544 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } }, 545 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
545 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ 546 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
546 { 0, CPORTS2R, 0, 0, 547 { MFIS2_INTCS, CPORTS2R, 0, 0,
547 JPU6E, 0, 0, 0 } }, 548 JPU6E, 0, 0, 0 } },
548 { 0xffd20104, 0, 16, /* INTAMASK */ 549 { 0xffd20104, 0, 16, /* INTAMASK */
549 { 0, 0, 0, 0, 0, 0, 0, 0, 550 { 0, 0, 0, 0, 0, 0, 0, 0,
@@ -571,7 +572,8 @@ static struct intc_prio_reg intcs_prio_registers[] = {
571 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, 572 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
572 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0, 573 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
573 DSITX1_DSITX1_1, 0 } }, 574 DSITX1_DSITX1_1, 0 } },
574 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } }, 575 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
576 0, 0 } },
575 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } }, 577 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
576}; 578};
577 579
@@ -590,6 +592,7 @@ static struct resource intcs_resources[] __initdata = {
590 592
591static struct intc_desc intcs_desc __initdata = { 593static struct intc_desc intcs_desc __initdata = {
592 .name = "sh7372-intcs", 594 .name = "sh7372-intcs",
595 .force_enable = ENABLED_INTCS,
593 .resource = intcs_resources, 596 .resource = intcs_resources,
594 .num_resources = ARRAY_SIZE(intcs_resources), 597 .num_resources = ARRAY_SIZE(intcs_resources),
595 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, 598 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 322d8d57cbcf..5d0e1503ece6 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -252,10 +252,11 @@ static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
252 252
253void __init sh73a0_init_irq(void) 253void __init sh73a0_init_irq(void)
254{ 254{
255 void __iomem *gic_base = __io(0xf0001000); 255 void __iomem *gic_dist_base = __io(0xf0001000);
256 void __iomem *gic_cpu_base = __io(0xf0000100);
256 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 257 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
257 258
258 gic_init(0, 29, gic_base, gic_base); 259 gic_init(0, 29, gic_dist_base, gic_cpu_base);
259 260
260 register_intc_controller(&intcs_desc); 261 register_intc_controller(&intcs_desc);
261 262