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Diffstat (limited to 'arch/arm/mach-shmobile/smp-sh73a0.c')
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c23
1 files changed, 2 insertions, 21 deletions
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 624f00f70abf..96ddb97babbe 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
41 return (void __iomem *)0xf0000000; 41 return (void __iomem *)0xf0000000;
42} 42}
43 43
44static DEFINE_SPINLOCK(scu_lock);
45static unsigned long tmp;
46
47#ifdef CONFIG_HAVE_ARM_TWD 44#ifdef CONFIG_HAVE_ARM_TWD
48static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 45static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
49void __init sh73a0_register_twd(void) 46void __init sh73a0_register_twd(void)
@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
52} 49}
53#endif 50#endif
54 51
55static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
56{
57 void __iomem *scu_base = scu_base_addr();
58
59 spin_lock(&scu_lock);
60 tmp = __raw_readl(scu_base + 8);
61 tmp &= ~clr;
62 tmp |= set;
63 spin_unlock(&scu_lock);
64
65 /* disable cache coherency after releasing the lock */
66 __raw_writel(tmp, scu_base + 8);
67}
68
69static unsigned int __init sh73a0_get_core_count(void) 52static unsigned int __init sh73a0_get_core_count(void)
70{ 53{
71 void __iomem *scu_base = scu_base_addr(); 54 void __iomem *scu_base = scu_base_addr();
@@ -83,7 +66,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
83 cpu = cpu_logical_map(cpu); 66 cpu = cpu_logical_map(cpu);
84 67
85 /* enable cache coherency */ 68 /* enable cache coherency */
86 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 69 scu_power_mode(scu_base_addr(), 0);
87 70
88 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) 71 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
89 __raw_writel(1 << cpu, WUPCR); /* wake up */ 72 __raw_writel(1 << cpu, WUPCR); /* wake up */
@@ -95,8 +78,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
95 78
96static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) 79static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
97{ 80{
98 int cpu = cpu_logical_map(0);
99
100 scu_enable(scu_base_addr()); 81 scu_enable(scu_base_addr());
101 82
102 /* Map the reset vector (in headsmp.S) */ 83 /* Map the reset vector (in headsmp.S) */
@@ -104,7 +85,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
104 __raw_writel(__pa(shmobile_secondary_vector), SBAR); 85 __raw_writel(__pa(shmobile_secondary_vector), SBAR);
105 86
106 /* enable cache coherency on CPU0 */ 87 /* enable cache coherency on CPU0 */
107 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 88 scu_power_mode(scu_base_addr(), 0);
108} 89}
109 90
110static void __init sh73a0_smp_init_cpus(void) 91static void __init sh73a0_smp_init_cpus(void)