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-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c244
1 files changed, 244 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 685c40a2f5e6..e46821c0a62e 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -27,9 +27,11 @@
27#include <linux/input.h> 27#include <linux/input.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/serial_sci.h> 29#include <linux/serial_sci.h>
30#include <linux/sh_dma.h>
30#include <linux/sh_intc.h> 31#include <linux/sh_intc.h>
31#include <linux/sh_timer.h> 32#include <linux/sh_timer.h>
32#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/sh73a0.h>
33#include <asm/mach-types.h> 35#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
35 37
@@ -392,6 +394,242 @@ static struct platform_device i2c4_device = {
392 .num_resources = ARRAY_SIZE(i2c4_resources), 394 .num_resources = ARRAY_SIZE(i2c4_resources),
393}; 395};
394 396
397/* Transmit sizes and respective CHCR register values */
398enum {
399 XMIT_SZ_8BIT = 0,
400 XMIT_SZ_16BIT = 1,
401 XMIT_SZ_32BIT = 2,
402 XMIT_SZ_64BIT = 7,
403 XMIT_SZ_128BIT = 3,
404 XMIT_SZ_256BIT = 4,
405 XMIT_SZ_512BIT = 5,
406};
407
408/* log2(size / 8) - used to calculate number of transfers */
409#define TS_SHIFT { \
410 [XMIT_SZ_8BIT] = 0, \
411 [XMIT_SZ_16BIT] = 1, \
412 [XMIT_SZ_32BIT] = 2, \
413 [XMIT_SZ_64BIT] = 3, \
414 [XMIT_SZ_128BIT] = 4, \
415 [XMIT_SZ_256BIT] = 5, \
416 [XMIT_SZ_512BIT] = 6, \
417}
418
419#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
420#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
421#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
422
423static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
424 {
425 .slave_id = SHDMA_SLAVE_SCIF0_TX,
426 .addr = 0xe6c40020,
427 .chcr = CHCR_TX(XMIT_SZ_8BIT),
428 .mid_rid = 0x21,
429 }, {
430 .slave_id = SHDMA_SLAVE_SCIF0_RX,
431 .addr = 0xe6c40024,
432 .chcr = CHCR_RX(XMIT_SZ_8BIT),
433 .mid_rid = 0x22,
434 }, {
435 .slave_id = SHDMA_SLAVE_SCIF1_TX,
436 .addr = 0xe6c50020,
437 .chcr = CHCR_TX(XMIT_SZ_8BIT),
438 .mid_rid = 0x25,
439 }, {
440 .slave_id = SHDMA_SLAVE_SCIF1_RX,
441 .addr = 0xe6c50024,
442 .chcr = CHCR_RX(XMIT_SZ_8BIT),
443 .mid_rid = 0x26,
444 }, {
445 .slave_id = SHDMA_SLAVE_SCIF2_TX,
446 .addr = 0xe6c60020,
447 .chcr = CHCR_TX(XMIT_SZ_8BIT),
448 .mid_rid = 0x29,
449 }, {
450 .slave_id = SHDMA_SLAVE_SCIF2_RX,
451 .addr = 0xe6c60024,
452 .chcr = CHCR_RX(XMIT_SZ_8BIT),
453 .mid_rid = 0x2a,
454 }, {
455 .slave_id = SHDMA_SLAVE_SCIF3_TX,
456 .addr = 0xe6c70020,
457 .chcr = CHCR_TX(XMIT_SZ_8BIT),
458 .mid_rid = 0x2d,
459 }, {
460 .slave_id = SHDMA_SLAVE_SCIF3_RX,
461 .addr = 0xe6c70024,
462 .chcr = CHCR_RX(XMIT_SZ_8BIT),
463 .mid_rid = 0x2e,
464 }, {
465 .slave_id = SHDMA_SLAVE_SCIF4_TX,
466 .addr = 0xe6c80020,
467 .chcr = CHCR_TX(XMIT_SZ_8BIT),
468 .mid_rid = 0x39,
469 }, {
470 .slave_id = SHDMA_SLAVE_SCIF4_RX,
471 .addr = 0xe6c80024,
472 .chcr = CHCR_RX(XMIT_SZ_8BIT),
473 .mid_rid = 0x3a,
474 }, {
475 .slave_id = SHDMA_SLAVE_SCIF5_TX,
476 .addr = 0xe6cb0020,
477 .chcr = CHCR_TX(XMIT_SZ_8BIT),
478 .mid_rid = 0x35,
479 }, {
480 .slave_id = SHDMA_SLAVE_SCIF5_RX,
481 .addr = 0xe6cb0024,
482 .chcr = CHCR_RX(XMIT_SZ_8BIT),
483 .mid_rid = 0x36,
484 }, {
485 .slave_id = SHDMA_SLAVE_SCIF6_TX,
486 .addr = 0xe6cc0020,
487 .chcr = CHCR_TX(XMIT_SZ_8BIT),
488 .mid_rid = 0x1d,
489 }, {
490 .slave_id = SHDMA_SLAVE_SCIF6_RX,
491 .addr = 0xe6cc0024,
492 .chcr = CHCR_RX(XMIT_SZ_8BIT),
493 .mid_rid = 0x1e,
494 }, {
495 .slave_id = SHDMA_SLAVE_SCIF7_TX,
496 .addr = 0xe6cd0020,
497 .chcr = CHCR_TX(XMIT_SZ_8BIT),
498 .mid_rid = 0x19,
499 }, {
500 .slave_id = SHDMA_SLAVE_SCIF7_RX,
501 .addr = 0xe6cd0024,
502 .chcr = CHCR_RX(XMIT_SZ_8BIT),
503 .mid_rid = 0x1a,
504 }, {
505 .slave_id = SHDMA_SLAVE_SCIF8_TX,
506 .addr = 0xe6c30040,
507 .chcr = CHCR_TX(XMIT_SZ_8BIT),
508 .mid_rid = 0x3d,
509 }, {
510 .slave_id = SHDMA_SLAVE_SCIF8_RX,
511 .addr = 0xe6c30060,
512 .chcr = CHCR_RX(XMIT_SZ_8BIT),
513 .mid_rid = 0x3e,
514 }, {
515 .slave_id = SHDMA_SLAVE_SDHI0_TX,
516 .addr = 0xee100030,
517 .chcr = CHCR_TX(XMIT_SZ_16BIT),
518 .mid_rid = 0xc1,
519 }, {
520 .slave_id = SHDMA_SLAVE_SDHI0_RX,
521 .addr = 0xee100030,
522 .chcr = CHCR_RX(XMIT_SZ_16BIT),
523 .mid_rid = 0xc2,
524 }, {
525 .slave_id = SHDMA_SLAVE_SDHI1_TX,
526 .addr = 0xee120030,
527 .chcr = CHCR_TX(XMIT_SZ_16BIT),
528 .mid_rid = 0xc9,
529 }, {
530 .slave_id = SHDMA_SLAVE_SDHI1_RX,
531 .addr = 0xee120030,
532 .chcr = CHCR_RX(XMIT_SZ_16BIT),
533 .mid_rid = 0xca,
534 }, {
535 .slave_id = SHDMA_SLAVE_SDHI2_TX,
536 .addr = 0xee140030,
537 .chcr = CHCR_TX(XMIT_SZ_16BIT),
538 .mid_rid = 0xcd,
539 }, {
540 .slave_id = SHDMA_SLAVE_SDHI2_RX,
541 .addr = 0xee140030,
542 .chcr = CHCR_RX(XMIT_SZ_16BIT),
543 .mid_rid = 0xce,
544 }, {
545 .slave_id = SHDMA_SLAVE_MMCIF_TX,
546 .addr = 0xe6bd0034,
547 .chcr = CHCR_TX(XMIT_SZ_32BIT),
548 .mid_rid = 0xd1,
549 }, {
550 .slave_id = SHDMA_SLAVE_MMCIF_RX,
551 .addr = 0xe6bd0034,
552 .chcr = CHCR_RX(XMIT_SZ_32BIT),
553 .mid_rid = 0xd2,
554 },
555};
556
557#define DMAE_CHANNEL(_offset) \
558 { \
559 .offset = _offset - 0x20, \
560 .dmars = _offset - 0x20 + 0x40, \
561 }
562
563static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
564 DMAE_CHANNEL(0x8000),
565 DMAE_CHANNEL(0x8080),
566 DMAE_CHANNEL(0x8100),
567 DMAE_CHANNEL(0x8180),
568 DMAE_CHANNEL(0x8200),
569 DMAE_CHANNEL(0x8280),
570 DMAE_CHANNEL(0x8300),
571 DMAE_CHANNEL(0x8380),
572 DMAE_CHANNEL(0x8400),
573 DMAE_CHANNEL(0x8480),
574 DMAE_CHANNEL(0x8500),
575 DMAE_CHANNEL(0x8580),
576 DMAE_CHANNEL(0x8600),
577 DMAE_CHANNEL(0x8680),
578 DMAE_CHANNEL(0x8700),
579 DMAE_CHANNEL(0x8780),
580 DMAE_CHANNEL(0x8800),
581 DMAE_CHANNEL(0x8880),
582 DMAE_CHANNEL(0x8900),
583 DMAE_CHANNEL(0x8980),
584};
585
586static const unsigned int ts_shift[] = TS_SHIFT;
587
588static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
589 .slave = sh73a0_dmae_slaves,
590 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
591 .channel = sh73a0_dmae_channels,
592 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
593 .ts_low_shift = 3,
594 .ts_low_mask = 0x18,
595 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
596 .ts_high_mask = 0x00300000,
597 .ts_shift = ts_shift,
598 .ts_shift_num = ARRAY_SIZE(ts_shift),
599 .dmaor_init = DMAOR_DME,
600};
601
602static struct resource sh73a0_dmae_resources[] = {
603 {
604 /* Registers including DMAOR and channels including DMARSx */
605 .start = 0xfe000020,
606 .end = 0xfe008a00 - 1,
607 .flags = IORESOURCE_MEM,
608 },
609 {
610 /* DMA error IRQ */
611 .start = gic_spi(129),
612 .end = gic_spi(129),
613 .flags = IORESOURCE_IRQ,
614 },
615 {
616 /* IRQ for channels 0-19 */
617 .start = gic_spi(109),
618 .end = gic_spi(128),
619 .flags = IORESOURCE_IRQ,
620 },
621};
622
623static struct platform_device dma0_device = {
624 .name = "sh-dma-engine",
625 .id = 0,
626 .resource = sh73a0_dmae_resources,
627 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
628 .dev = {
629 .platform_data = &sh73a0_dmae_platform_data,
630 },
631};
632
395static struct platform_device *sh73a0_early_devices[] __initdata = { 633static struct platform_device *sh73a0_early_devices[] __initdata = {
396 &scif0_device, 634 &scif0_device,
397 &scif1_device, 635 &scif1_device,
@@ -413,10 +651,16 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
413 &i2c2_device, 651 &i2c2_device,
414 &i2c3_device, 652 &i2c3_device,
415 &i2c4_device, 653 &i2c4_device,
654 &dma0_device,
416}; 655};
417 656
657#define SRCR2 0xe61580b0
658
418void __init sh73a0_add_standard_devices(void) 659void __init sh73a0_add_standard_devices(void)
419{ 660{
661 /* Clear software reset bit on SY-DMAC module */
662 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
663
420 platform_add_devices(sh73a0_early_devices, 664 platform_add_devices(sh73a0_early_devices,
421 ARRAY_SIZE(sh73a0_early_devices)); 665 ARRAY_SIZE(sh73a0_early_devices));
422 platform_add_devices(sh73a0_late_devices, 666 platform_add_devices(sh73a0_late_devices,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 09:57:02 -0500