diff options
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7778.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7778.c | 72 |
1 files changed, 21 insertions, 51 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 0174f059eac3..203becfc6e31 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
@@ -53,7 +53,7 @@ | |||
53 | .irqs = SCIx_IRQ_MUXED(irq), \ | 53 | .irqs = SCIx_IRQ_MUXED(irq), \ |
54 | } | 54 | } |
55 | 55 | ||
56 | static struct plat_sci_port scif_platform_data[] = { | 56 | static struct plat_sci_port scif_platform_data[] __initdata = { |
57 | SCIF_INFO(0xffe40000, gic_iid(0x66)), | 57 | SCIF_INFO(0xffe40000, gic_iid(0x66)), |
58 | SCIF_INFO(0xffe41000, gic_iid(0x67)), | 58 | SCIF_INFO(0xffe41000, gic_iid(0x67)), |
59 | SCIF_INFO(0xffe42000, gic_iid(0x68)), | 59 | SCIF_INFO(0xffe42000, gic_iid(0x68)), |
@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = { | |||
63 | }; | 63 | }; |
64 | 64 | ||
65 | /* TMU */ | 65 | /* TMU */ |
66 | static struct resource sh_tmu0_resources[] = { | 66 | static struct resource sh_tmu0_resources[] __initdata = { |
67 | DEFINE_RES_MEM(0xffd80008, 12), | 67 | DEFINE_RES_MEM(0xffd80008, 12), |
68 | DEFINE_RES_IRQ(gic_iid(0x40)), | 68 | DEFINE_RES_IRQ(gic_iid(0x40)), |
69 | }; | 69 | }; |
70 | 70 | ||
71 | static struct sh_timer_config sh_tmu0_platform_data = { | 71 | static struct sh_timer_config sh_tmu0_platform_data __initdata = { |
72 | .name = "TMU00", | 72 | .name = "TMU00", |
73 | .channel_offset = 0x4, | 73 | .channel_offset = 0x4, |
74 | .timer_bit = 0, | 74 | .timer_bit = 0, |
75 | .clockevent_rating = 200, | 75 | .clockevent_rating = 200, |
76 | }; | 76 | }; |
77 | 77 | ||
78 | static struct resource sh_tmu1_resources[] = { | 78 | static struct resource sh_tmu1_resources[] __initdata = { |
79 | DEFINE_RES_MEM(0xffd80014, 12), | 79 | DEFINE_RES_MEM(0xffd80014, 12), |
80 | DEFINE_RES_IRQ(gic_iid(0x41)), | 80 | DEFINE_RES_IRQ(gic_iid(0x41)), |
81 | }; | 81 | }; |
82 | 82 | ||
83 | static struct sh_timer_config sh_tmu1_platform_data = { | 83 | static struct sh_timer_config sh_tmu1_platform_data __initdata = { |
84 | .name = "TMU01", | 84 | .name = "TMU01", |
85 | .channel_offset = 0x10, | 85 | .channel_offset = 0x10, |
86 | .timer_bit = 1, | 86 | .timer_bit = 1, |
@@ -189,7 +189,7 @@ USB_PLATFORM_INFO(ehci); | |||
189 | USB_PLATFORM_INFO(ohci); | 189 | USB_PLATFORM_INFO(ohci); |
190 | 190 | ||
191 | /* Ether */ | 191 | /* Ether */ |
192 | static struct resource ether_resources[] = { | 192 | static struct resource ether_resources[] __initdata = { |
193 | DEFINE_RES_MEM(0xfde00000, 0x400), | 193 | DEFINE_RES_MEM(0xfde00000, 0x400), |
194 | DEFINE_RES_IRQ(gic_iid(0x89)), | 194 | DEFINE_RES_IRQ(gic_iid(0x89)), |
195 | }; | 195 | }; |
@@ -203,17 +203,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) | |||
203 | } | 203 | } |
204 | 204 | ||
205 | /* PFC/GPIO */ | 205 | /* PFC/GPIO */ |
206 | static struct resource pfc_resources[] = { | 206 | static struct resource pfc_resources[] __initdata = { |
207 | DEFINE_RES_MEM(0xfffc0000, 0x118), | 207 | DEFINE_RES_MEM(0xfffc0000, 0x118), |
208 | }; | 208 | }; |
209 | 209 | ||
210 | #define R8A7778_GPIO(idx) \ | 210 | #define R8A7778_GPIO(idx) \ |
211 | static struct resource r8a7778_gpio##idx##_resources[] = { \ | 211 | static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ |
212 | DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ | 212 | DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ |
213 | DEFINE_RES_IRQ(gic_iid(0x87)), \ | 213 | DEFINE_RES_IRQ(gic_iid(0x87)), \ |
214 | }; \ | 214 | }; \ |
215 | \ | 215 | \ |
216 | static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ | 216 | static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ |
217 | .gpio_base = 32 * (idx), \ | 217 | .gpio_base = 32 * (idx), \ |
218 | .irq_base = GPIO_IRQ_BASE(idx), \ | 218 | .irq_base = GPIO_IRQ_BASE(idx), \ |
219 | .number_of_pins = 32, \ | 219 | .number_of_pins = 32, \ |
@@ -249,7 +249,7 @@ void __init r8a7778_pinmux_init(void) | |||
249 | }; | 249 | }; |
250 | 250 | ||
251 | /* SDHI */ | 251 | /* SDHI */ |
252 | static struct resource sdhi_resources[] = { | 252 | static struct resource sdhi_resources[] __initdata = { |
253 | /* SDHI0 */ | 253 | /* SDHI0 */ |
254 | DEFINE_RES_MEM(0xFFE4C000, 0x100), | 254 | DEFINE_RES_MEM(0xFFE4C000, 0x100), |
255 | DEFINE_RES_IRQ(gic_iid(0x77)), | 255 | DEFINE_RES_IRQ(gic_iid(0x77)), |
@@ -399,12 +399,12 @@ void __init r8a7778_init_late(void) | |||
399 | platform_device_register_full(&ohci_info); | 399 | platform_device_register_full(&ohci_info); |
400 | } | 400 | } |
401 | 401 | ||
402 | static struct renesas_intc_irqpin_config irqpin_platform_data = { | 402 | static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { |
403 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | 403 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
404 | .sense_bitfield_width = 2, | 404 | .sense_bitfield_width = 2, |
405 | }; | 405 | }; |
406 | 406 | ||
407 | static struct resource irqpin_resources[] = { | 407 | static struct resource irqpin_resources[] __initdata = { |
408 | DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ | 408 | DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ |
409 | DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ | 409 | DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ |
410 | DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ | 410 | DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ |
@@ -442,17 +442,25 @@ void __init r8a7778_init_irq_extpin(int irlm) | |||
442 | &irqpin_platform_data, sizeof(irqpin_platform_data)); | 442 | &irqpin_platform_data, sizeof(irqpin_platform_data)); |
443 | } | 443 | } |
444 | 444 | ||
445 | void __init r8a7778_init_delay(void) | ||
446 | { | ||
447 | shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ | ||
448 | } | ||
449 | |||
450 | #ifdef CONFIG_USE_OF | ||
445 | #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ | 451 | #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ |
446 | #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ | 452 | #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ |
447 | 453 | ||
448 | #define INT2NTSR0 0x00018 /* 0xfe700018 */ | 454 | #define INT2NTSR0 0x00018 /* 0xfe700018 */ |
449 | #define INT2NTSR1 0x0002c /* 0xfe70002c */ | 455 | #define INT2NTSR1 0x0002c /* 0xfe70002c */ |
450 | static void __init r8a7778_init_irq_common(void) | 456 | void __init r8a7778_init_irq_dt(void) |
451 | { | 457 | { |
452 | void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); | 458 | void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); |
453 | 459 | ||
454 | BUG_ON(!base); | 460 | BUG_ON(!base); |
455 | 461 | ||
462 | irqchip_init(); | ||
463 | |||
456 | /* route all interrupts to ARM */ | 464 | /* route all interrupts to ARM */ |
457 | __raw_writel(0x73ffffff, base + INT2NTSR0); | 465 | __raw_writel(0x73ffffff, base + INT2NTSR0); |
458 | __raw_writel(0xffffffff, base + INT2NTSR1); | 466 | __raw_writel(0xffffffff, base + INT2NTSR1); |
@@ -464,43 +472,6 @@ static void __init r8a7778_init_irq_common(void) | |||
464 | iounmap(base); | 472 | iounmap(base); |
465 | } | 473 | } |
466 | 474 | ||
467 | void __init r8a7778_init_irq(void) | ||
468 | { | ||
469 | void __iomem *gic_dist_base; | ||
470 | void __iomem *gic_cpu_base; | ||
471 | |||
472 | gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); | ||
473 | gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); | ||
474 | BUG_ON(!gic_dist_base || !gic_cpu_base); | ||
475 | |||
476 | /* use GIC to handle interrupts */ | ||
477 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | ||
478 | |||
479 | r8a7778_init_irq_common(); | ||
480 | } | ||
481 | |||
482 | void __init r8a7778_init_delay(void) | ||
483 | { | ||
484 | shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ | ||
485 | } | ||
486 | |||
487 | #ifdef CONFIG_USE_OF | ||
488 | void __init r8a7778_init_irq_dt(void) | ||
489 | { | ||
490 | irqchip_init(); | ||
491 | r8a7778_init_irq_common(); | ||
492 | } | ||
493 | |||
494 | static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { | ||
495 | {}, | ||
496 | }; | ||
497 | |||
498 | void __init r8a7778_add_standard_devices_dt(void) | ||
499 | { | ||
500 | of_platform_populate(NULL, of_default_bus_match_table, | ||
501 | r8a7778_auxdata_lookup, NULL); | ||
502 | } | ||
503 | |||
504 | static const char *r8a7778_compat_dt[] __initdata = { | 475 | static const char *r8a7778_compat_dt[] __initdata = { |
505 | "renesas,r8a7778", | 476 | "renesas,r8a7778", |
506 | NULL, | 477 | NULL, |
@@ -509,7 +480,6 @@ static const char *r8a7778_compat_dt[] __initdata = { | |||
509 | DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") | 480 | DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") |
510 | .init_early = r8a7778_init_delay, | 481 | .init_early = r8a7778_init_delay, |
511 | .init_irq = r8a7778_init_irq_dt, | 482 | .init_irq = r8a7778_init_irq_dt, |
512 | .init_machine = r8a7778_add_standard_devices_dt, | ||
513 | .init_time = shmobile_timer_init, | 483 | .init_time = shmobile_timer_init, |
514 | .dt_compat = r8a7778_compat_dt, | 484 | .dt_compat = r8a7778_compat_dt, |
515 | .init_late = r8a7778_init_late, | 485 | .init_late = r8a7778_init_late, |