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Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a73a4.c')
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c68
1 files changed, 33 insertions, 35 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b0f2749071be..cd36f8078325 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
40 ARRAY_SIZE(pfc_resources)); 40 ARRAY_SIZE(pfc_resources));
41} 41}
42 42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \ 43#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
44static struct plat_sci_port scif##index##_platform_data = { \
44 .type = scif_type, \ 45 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .scbrr_algo_id = SCBRR_ALGO_4, \ 47 .scscr = _scscr, \
48 .irqs = SCIx_IRQ_MUXED(irq) 48}; \
49 49 \
50#define SCIFA_DATA(index, baseaddr, irq) \ 50static struct resource scif##index##_resources[] = { \
51[index] = { \ 51 DEFINE_RES_MEM(baseaddr, 0x100), \
52 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 52 DEFINE_RES_IRQ(irq), \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54} 53}
55 54
56#define SCIFB_DATA(index, baseaddr, irq) \ 55#define R8A73A4_SCIFA(index, baseaddr, irq) \
57[index] = { \ 56 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ 57 index, baseaddr, irq)
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61 58
62enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; 59#define R8A73A4_SCIFB(index, baseaddr, irq) \
60 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
61 index, baseaddr, irq)
63 62
64static const struct plat_sci_port scif[] = { 63R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
65 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 64R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
66 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 65R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
67 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 66R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
68 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 67R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
69 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 68R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
70 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
71};
72 69
73static inline void r8a73a4_register_scif(int idx) 70#define r8a73a4_register_scif(index) \
74{ 71 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
75 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 72 scif##index##_resources, \
76 sizeof(struct plat_sci_port)); 73 ARRAY_SIZE(scif##index##_resources), \
77} 74 &scif##index##_platform_data, \
75 sizeof(scif##index##_platform_data))
78 76
79static const struct renesas_irqc_config irqc0_data = { 77static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
192 190
193void __init r8a73a4_add_dt_devices(void) 191void __init r8a73a4_add_dt_devices(void)
194{ 192{
195 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(0);
196 r8a73a4_register_scif(SCIFA1); 194 r8a73a4_register_scif(1);
197 r8a73a4_register_scif(SCIFB0); 195 r8a73a4_register_scif(2);
198 r8a73a4_register_scif(SCIFB1); 196 r8a73a4_register_scif(3);
199 r8a73a4_register_scif(SCIFB2); 197 r8a73a4_register_scif(4);
200 r8a73a4_register_scif(SCIFB3); 198 r8a73a4_register_scif(5);
201 r8a7790_register_cmt(10); 199 r8a7790_register_cmt(10);
202} 200}
203 201
@@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = {
275 273
276static struct resource dma_resources[] = { 274static struct resource dma_resources[] = {
277 DEFINE_RES_MEM(0xe6700020, 0x89e0), 275 DEFINE_RES_MEM(0xe6700020, 0x89e0),
278 DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), 276 DEFINE_RES_IRQ(gic_spi(220)),
279 { 277 {
280 /* IRQ for channels 0-19 */ 278 /* IRQ for channels 0-19 */
281 .start = gic_spi(200), 279 .start = gic_spi(200),