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-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c369
1 files changed, 369 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
new file mode 100644
index 000000000000..c57a923f97a6
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -0,0 +1,369 @@
1/*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28enum {
29 UNUSED_INTCA = 0,
30
31 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
33 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
34 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
35 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
36 DIRC,
37 CRYPT_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
40 MFI_MFIM, MFI_MFIS,
41 BBIF1, BBIF2,
42 USBHSDMAC0_USHDMI,
43 _3DG_SGX540,
44 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
45 KEYSC_KEY,
46 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
47 MSIOF2, MSIOF1,
48 SCIFA4, SCIFA5, SCIFB,
49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
50 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
51 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
52 IRREM,
53 IRDA,
54 TPU0,
55 TTI20,
56 DDM,
57 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
58 RWDT0,
59 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
60 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
61 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
62 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
63 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
64 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
65 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
66 HDMI,
67 SPU2_SPU0, SPU2_SPU1,
68 FSI, FMSI,
69 MIPI_HSI,
70 IPMMU_IPMMUD,
71 CEC_1, CEC_2,
72 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
73 MFIS2,
74 CPORTR2S,
75 CMT14, CMT15,
76 MMC_MMC_ERR, MMC_MMC_NOR,
77 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
78 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
79 USB0_USB0I1, USB0_USB0I0,
80 USB1_USB1I1, USB1_USB1I0,
81 USBHSDMAC1_USHDMI,
82
83 /* interrupt groups INTCA */
84 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
85 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
86};
87
88static struct intc_vect intca_vectors[] __initdata = {
89 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
90 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
91 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
92 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
93 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
94 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
95 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
96 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
97 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
98 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
99 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
100 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
101 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
102 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
103 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
104 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
105 INTC_VECT(DIRC, 0x0560),
106 INTC_VECT(CRYPT_STD, 0x0700),
107 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
108 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
109 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
110 INTC_VECT(AP_ARM_COMMRX, 0x0860),
111 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
112 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
114 INTC_VECT(_3DG_SGX540, 0x0a60),
115 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
116 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
117 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
118 INTC_VECT(KEYSC_KEY, 0x0be0),
119 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
120 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
121 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
122 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
123 INTC_VECT(SCIFB, 0x0d60),
124 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
125 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
126 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
127 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
128 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
129 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
130 INTC_VECT(IRREM, 0x0f60),
131 INTC_VECT(IRDA, 0x0480),
132 INTC_VECT(TPU0, 0x04a0),
133 INTC_VECT(TTI20, 0x1100),
134 INTC_VECT(DDM, 0x1140),
135 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
136 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
137 INTC_VECT(RWDT0, 0x1280),
138 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
139 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
140 INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
141 INTC_VECT(DMAC1_2_DADERR, 0x20c0),
142 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
143 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
144 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
145 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
146 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
147 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
148 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
149 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
150 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
151 INTC_VECT(SHWYSTAT_COM, 0x1340),
152 INTC_VECT(HDMI, 0x17e0),
153 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
154 INTC_VECT(FSI, 0x1840),
155 INTC_VECT(FMSI, 0x1860),
156 INTC_VECT(MIPI_HSI, 0x18e0),
157 INTC_VECT(IPMMU_IPMMUD, 0x1920),
158 INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
159 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
160 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
161 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
162 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
163 INTC_VECT(MFIS2, 0x1a00),
164 INTC_VECT(CPORTR2S, 0x1a20),
165 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
166 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
167 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
168 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
169 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
170 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
171 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
172 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
173 INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
174};
175
176static struct intc_group intca_groups[] __initdata = {
177 INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
178 DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
179 INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
180 DMAC1_2_DEI5, DMAC1_2_DADERR),
181 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
182 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
183 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
184 DMAC2_2_DEI5, DMAC2_2_DADERR),
185 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
186 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
187 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
188 DMAC3_2_DEI5, DMAC3_2_DADERR),
189 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
190 INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
191 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
192 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
193 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
194 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
195 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
196 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
197 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
198 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
199 SDHI1_SDHI1I2),
200 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
201 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
202 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
203};
204
205static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
209 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
210 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
211 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
212 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
213 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
214
215 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
216 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
217 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
218 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
219 { 0, CRYPT_STD, DIRC, 0,
220 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
221 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
222 { 0, 0, 0, 0,
223 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
224 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
225 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
226 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
227 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
228 { DDM, 0, 0, 0,
229 0, 0, 0, 0 } },
230 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
231 { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
232 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
233 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
234 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
235 0, 0, MSIOF2, 0 } },
236 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
237 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
238 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
239 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
240 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
241 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
242 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
243 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
244 CMT2, 0, 0, _3DG_SGX540 } },
245 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
246 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
247 0, 0, 0, 0 } },
248 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
249 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
250 0, 0, IRREM, 0 } },
251 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
252 { 0, 0, TPU0, 0,
253 0, 0, 0, 0 } },
254 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
255 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
256 0, CMT3, 0, RWDT0 } },
257 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
258 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
259 0, 0, 0, 0 } },
260 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
261 { 0, 0, 0, 0,
262 0, 0, 0, HDMI } },
263 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
264 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
265 0, 0, 0, MIPI_HSI } },
266 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
267 { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
268 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
269 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
270 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
271 { MFIS2, CPORTR2S, CMT14, CMT15,
272 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
273 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
274 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
275 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
276 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
277 { 0, 0, 0, 0,
278 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
279 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
280 { USBHSDMAC1_USHDMI, 0, 0, 0,
281 0, 0, 0, 0 } },
282};
283
284static struct intc_prio_reg intca_prio_registers[] __initdata = {
285 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
286 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
287 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
288 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
289 { 0xe6900018, 0, 32, 4, /* INTPRI20A */
290 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
291 { 0xe690001c, 0, 32, 4, /* INTPRI30A */
292 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
293
294 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
295 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
296 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
297 CMT1_CMT11, AP_ARM1 } },
298 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
299 CMT1_CMT12, 0 } },
300 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
301 MFI_MFIM, 0 } },
302 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
303 _3DG_SGX540, CMT1_CMT10 } },
304 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
305 SCIFA2, SCIFA3 } },
306 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
307 FLCTL, SDHI0 } },
308 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
309 0/* MSU */, IIC1 } },
310 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
311 0/* MSUG */, TTI20 } },
312 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
313 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
314 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
315 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
316 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
317 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
318 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
319 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
320 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
321 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
322 CEC_1, CEC_2 } },
323 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
324 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
325 CMT14, CMT15 } },
326 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
327 MMC_MMC_ERR, MMC_MMC_NOR } },
328 { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
329 IIC4_WAITI4, IIC4_DTEI4 } },
330 { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
331 IIC3_WAITI3, IIC3_DTEI3 } },
332 { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
333 0/*TXI*/, 0/*TEI*/} },
334 { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
335 USB1_USB1I1, USB1_USB1I0 } },
336 { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
337};
338
339static struct intc_sense_reg intca_sense_registers[] __initdata = {
340 { 0xe6900000, 32, 4, /* ICR1A */
341 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
342 { 0xe6900004, 32, 4, /* ICR2A */
343 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
344 { 0xe6900008, 32, 4, /* ICR3A */
345 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
346 { 0xe690000c, 32, 4, /* ICR4A */
347 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
348};
349
350static struct intc_mask_reg intca_ack_registers[] __initdata = {
351 { 0xe6900020, 0, 8, /* INTREQ00A */
352 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
353 { 0xe6900024, 0, 8, /* INTREQ10A */
354 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
355 { 0xe6900028, 0, 8, /* INTREQ20A */
356 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
357 { 0xe690002c, 0, 8, /* INTREQ30A */
358 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
359};
360
361static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
362 intca_vectors, intca_groups,
363 intca_mask_registers, intca_prio_registers,
364 intca_sense_registers, intca_ack_registers);
365
366void __init sh7372_init_irq(void)
367{
368 register_intc_controller(&intca_desc);
369}
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 07:44:54 -0500