diff options
Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh7367.c')
-rw-r--r-- | arch/arm/mach-shmobile/intc-sh7367.c | 178 |
1 files changed, 174 insertions, 4 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 5ff70cadfc32..1a20c489b20d 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c | |||
@@ -75,7 +75,7 @@ enum { | |||
75 | ETM11, ARM11, USBHS, FLCTL, IIC1 | 75 | ETM11, ARM11, USBHS, FLCTL, IIC1 |
76 | }; | 76 | }; |
77 | 77 | ||
78 | static struct intc_vect intca_vectors[] = { | 78 | static struct intc_vect intca_vectors[] __initdata = { |
79 | INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), | 79 | INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), |
80 | INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), | 80 | INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), |
81 | INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), | 81 | INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), |
@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = { | |||
162 | INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), | 162 | INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), |
163 | }; | 163 | }; |
164 | 164 | ||
165 | static struct intc_mask_reg intca_mask_registers[] = { | 165 | static struct intc_mask_reg intca_mask_registers[] __initdata = { |
166 | { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ | 166 | { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ |
167 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | 167 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, |
168 | { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ | 168 | { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ |
@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = { | |||
211 | MISTY, CMT3, RWDT1, RWDT0 } }, | 211 | MISTY, CMT3, RWDT1, RWDT0 } }, |
212 | }; | 212 | }; |
213 | 213 | ||
214 | static struct intc_prio_reg intca_prio_registers[] = { | 214 | static struct intc_prio_reg intca_prio_registers[] __initdata = { |
215 | { 0xe6900010, 0, 32, 4, /* INTPRI00A */ | 215 | { 0xe6900010, 0, 32, 4, /* INTPRI00A */ |
216 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | 216 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, |
217 | { 0xe6900014, 0, 32, 4, /* INTPRI10A */ | 217 | { 0xe6900014, 0, 32, 4, /* INTPRI10A */ |
@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = { | |||
263 | intca_sense_registers, intca_ack_registers), | 263 | intca_sense_registers, intca_ack_registers), |
264 | }; | 264 | }; |
265 | 265 | ||
266 | enum { | ||
267 | UNUSED_INTCS = 0, | ||
268 | |||
269 | INTCS, | ||
270 | |||
271 | /* interrupt sources INTCS */ | ||
272 | VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3, | ||
273 | VIO3_VOU, | ||
274 | RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, | ||
275 | VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2, | ||
276 | VPU, | ||
277 | SGX530, | ||
278 | _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3, | ||
279 | IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, | ||
280 | IPMMU_IPMMUB, IPMMU_IPMMUS, | ||
281 | RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, | ||
282 | MSIOF, | ||
283 | IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, | ||
284 | TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, | ||
285 | CMT, | ||
286 | TSIF, | ||
287 | IPMMUI, | ||
288 | MVI3, | ||
289 | ICB, | ||
290 | PEP, | ||
291 | ASA, | ||
292 | BEM, | ||
293 | VE2HO, | ||
294 | HQE, | ||
295 | JPEG, | ||
296 | LCDC, | ||
297 | |||
298 | /* interrupt groups INTCS */ | ||
299 | _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, | ||
300 | }; | ||
301 | |||
302 | static struct intc_vect intcs_vectors[] = { | ||
303 | INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720), | ||
304 | INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760), | ||
305 | INTCS_VECT(VIO3_VOU, 0x780), | ||
306 | INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), | ||
307 | INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), | ||
308 | INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0), | ||
309 | INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0), | ||
310 | INTCS_VECT(VPU, 0x980), | ||
311 | INTCS_VECT(SGX530, 0x9e0), | ||
312 | INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20), | ||
313 | INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60), | ||
314 | INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), | ||
315 | INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), | ||
316 | INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60), | ||
317 | INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), | ||
318 | INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), | ||
319 | INTCS_VECT(MSIOF, 0xd20), | ||
320 | INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), | ||
321 | INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), | ||
322 | INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), | ||
323 | INTCS_VECT(TMU_TUNI2, 0xec0), | ||
324 | INTCS_VECT(CMT, 0xf00), | ||
325 | INTCS_VECT(TSIF, 0xf20), | ||
326 | INTCS_VECT(IPMMUI, 0xf60), | ||
327 | INTCS_VECT(MVI3, 0x420), | ||
328 | INTCS_VECT(ICB, 0x480), | ||
329 | INTCS_VECT(PEP, 0x4a0), | ||
330 | INTCS_VECT(ASA, 0x4c0), | ||
331 | INTCS_VECT(BEM, 0x4e0), | ||
332 | INTCS_VECT(VE2HO, 0x520), | ||
333 | INTCS_VECT(HQE, 0x540), | ||
334 | INTCS_VECT(JPEG, 0x560), | ||
335 | INTCS_VECT(LCDC, 0x580), | ||
336 | |||
337 | INTC_VECT(INTCS, 0xf80), | ||
338 | }; | ||
339 | |||
340 | static struct intc_group intcs_groups[] __initdata = { | ||
341 | INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1, | ||
342 | _2DDMAC_2DDM2, _2DDMAC_2DDM3), | ||
343 | INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, | ||
344 | RTDMAC_1_DEI2, RTDMAC_1_DEI3), | ||
345 | INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), | ||
346 | INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3), | ||
347 | INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2), | ||
348 | INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), | ||
349 | INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB), | ||
350 | INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), | ||
351 | }; | ||
352 | |||
353 | static struct intc_mask_reg intcs_mask_registers[] = { | ||
354 | { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ | ||
355 | { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU, | ||
356 | VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } }, | ||
357 | { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ | ||
358 | { VIO3_VOU, 0, VE2HO, VPU, | ||
359 | 0, 0, 0, 0 } }, | ||
360 | { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ | ||
361 | { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0, | ||
362 | BEM, ASA, PEP, ICB } }, | ||
363 | { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ | ||
364 | { 0, 0, MVI3, 0, | ||
365 | JPEG, HQE, 0, LCDC } }, | ||
366 | { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ | ||
367 | { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, | ||
368 | RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, | ||
369 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ | ||
370 | { 0, 0, MSIOF, 0, | ||
371 | SGX530, 0, 0, 0 } }, | ||
372 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ | ||
373 | { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, | ||
374 | 0, 0, 0, 0 } }, | ||
375 | { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ | ||
376 | { 0, 0, 0, CMT, | ||
377 | IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, | ||
378 | { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ | ||
379 | { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0, | ||
380 | 0, 0, 0, 0 } }, | ||
381 | { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ | ||
382 | { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, | ||
383 | 0, 0, IPMMUI, TSIF } }, | ||
384 | { 0xffd20104, 0, 16, /* INTAMASK */ | ||
385 | { 0, 0, 0, 0, 0, 0, 0, 0, | ||
386 | 0, 0, 0, 0, 0, 0, 0, INTCS } }, | ||
387 | }; | ||
388 | |||
389 | /* Priority is needed for INTCA to receive the INTCS interrupt */ | ||
390 | static struct intc_prio_reg intcs_prio_registers[] = { | ||
391 | { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } }, | ||
392 | { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } }, | ||
393 | { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, | ||
394 | { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } }, | ||
395 | { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } }, | ||
396 | { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, | ||
397 | TMU_TUNI2, 0 } }, | ||
398 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } }, | ||
399 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } }, | ||
400 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } }, | ||
401 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } }, | ||
402 | { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } }, | ||
403 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, | ||
404 | }; | ||
405 | |||
406 | static struct resource intcs_resources[] __initdata = { | ||
407 | [0] = { | ||
408 | .start = 0xffd20000, | ||
409 | .end = 0xffd2ffff, | ||
410 | .flags = IORESOURCE_MEM, | ||
411 | } | ||
412 | }; | ||
413 | |||
414 | static struct intc_desc intcs_desc __initdata = { | ||
415 | .name = "sh7367-intcs", | ||
416 | .resource = intcs_resources, | ||
417 | .num_resources = ARRAY_SIZE(intcs_resources), | ||
418 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, | ||
419 | intcs_prio_registers, NULL, NULL), | ||
420 | }; | ||
421 | |||
422 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | ||
423 | { | ||
424 | void __iomem *reg = (void *)get_irq_data(irq); | ||
425 | unsigned int evtcodeas = ioread32(reg); | ||
426 | |||
427 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | ||
428 | } | ||
429 | |||
266 | void __init sh7367_init_irq(void) | 430 | void __init sh7367_init_irq(void) |
267 | { | 431 | { |
268 | /* INTCA */ | 432 | void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); |
433 | |||
269 | register_intc_controller(&intca_desc); | 434 | register_intc_controller(&intca_desc); |
435 | register_intc_controller(&intcs_desc); | ||
436 | |||
437 | /* demux using INTEVTSA */ | ||
438 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | ||
439 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | ||
270 | } | 440 | } |