diff options
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh73a0.c')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh73a0.c | 70 |
1 files changed, 35 insertions, 35 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 7f8da18a8580..516ff7f3e434 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
| @@ -23,43 +23,43 @@ | |||
| 23 | #include <linux/clkdev.h> | 23 | #include <linux/clkdev.h> |
| 24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 25 | 25 | ||
| 26 | #define FRQCRA 0xe6150000 | 26 | #define FRQCRA IOMEM(0xe6150000) |
| 27 | #define FRQCRB 0xe6150004 | 27 | #define FRQCRB IOMEM(0xe6150004) |
| 28 | #define FRQCRD 0xe61500e4 | 28 | #define FRQCRD IOMEM(0xe61500e4) |
| 29 | #define VCLKCR1 0xe6150008 | 29 | #define VCLKCR1 IOMEM(0xe6150008) |
| 30 | #define VCLKCR2 0xe615000C | 30 | #define VCLKCR2 IOMEM(0xe615000C) |
| 31 | #define VCLKCR3 0xe615001C | 31 | #define VCLKCR3 IOMEM(0xe615001C) |
| 32 | #define ZBCKCR 0xe6150010 | 32 | #define ZBCKCR IOMEM(0xe6150010) |
| 33 | #define FLCKCR 0xe6150014 | 33 | #define FLCKCR IOMEM(0xe6150014) |
| 34 | #define SD0CKCR 0xe6150074 | 34 | #define SD0CKCR IOMEM(0xe6150074) |
| 35 | #define SD1CKCR 0xe6150078 | 35 | #define SD1CKCR IOMEM(0xe6150078) |
| 36 | #define SD2CKCR 0xe615007C | 36 | #define SD2CKCR IOMEM(0xe615007C) |
| 37 | #define FSIACKCR 0xe6150018 | 37 | #define FSIACKCR IOMEM(0xe6150018) |
| 38 | #define FSIBCKCR 0xe6150090 | 38 | #define FSIBCKCR IOMEM(0xe6150090) |
| 39 | #define SUBCKCR 0xe6150080 | 39 | #define SUBCKCR IOMEM(0xe6150080) |
| 40 | #define SPUACKCR 0xe6150084 | 40 | #define SPUACKCR IOMEM(0xe6150084) |
| 41 | #define SPUVCKCR 0xe6150094 | 41 | #define SPUVCKCR IOMEM(0xe6150094) |
| 42 | #define MSUCKCR 0xe6150088 | 42 | #define MSUCKCR IOMEM(0xe6150088) |
| 43 | #define HSICKCR 0xe615008C | 43 | #define HSICKCR IOMEM(0xe615008C) |
| 44 | #define MFCK1CR 0xe6150098 | 44 | #define MFCK1CR IOMEM(0xe6150098) |
| 45 | #define MFCK2CR 0xe615009C | 45 | #define MFCK2CR IOMEM(0xe615009C) |
| 46 | #define DSITCKCR 0xe6150060 | 46 | #define DSITCKCR IOMEM(0xe6150060) |
| 47 | #define DSI0PCKCR 0xe6150064 | 47 | #define DSI0PCKCR IOMEM(0xe6150064) |
| 48 | #define DSI1PCKCR 0xe6150068 | 48 | #define DSI1PCKCR IOMEM(0xe6150068) |
| 49 | #define DSI0PHYCR 0xe615006C | 49 | #define DSI0PHYCR 0xe615006C |
| 50 | #define DSI1PHYCR 0xe6150070 | 50 | #define DSI1PHYCR 0xe6150070 |
| 51 | #define PLLECR 0xe61500d0 | 51 | #define PLLECR IOMEM(0xe61500d0) |
| 52 | #define PLL0CR 0xe61500d8 | 52 | #define PLL0CR IOMEM(0xe61500d8) |
| 53 | #define PLL1CR 0xe6150028 | 53 | #define PLL1CR IOMEM(0xe6150028) |
| 54 | #define PLL2CR 0xe615002c | 54 | #define PLL2CR IOMEM(0xe615002c) |
| 55 | #define PLL3CR 0xe61500dc | 55 | #define PLL3CR IOMEM(0xe61500dc) |
| 56 | #define SMSTPCR0 0xe6150130 | 56 | #define SMSTPCR0 IOMEM(0xe6150130) |
| 57 | #define SMSTPCR1 0xe6150134 | 57 | #define SMSTPCR1 IOMEM(0xe6150134) |
| 58 | #define SMSTPCR2 0xe6150138 | 58 | #define SMSTPCR2 IOMEM(0xe6150138) |
| 59 | #define SMSTPCR3 0xe615013c | 59 | #define SMSTPCR3 IOMEM(0xe615013c) |
| 60 | #define SMSTPCR4 0xe6150140 | 60 | #define SMSTPCR4 IOMEM(0xe6150140) |
| 61 | #define SMSTPCR5 0xe6150144 | 61 | #define SMSTPCR5 IOMEM(0xe6150144) |
| 62 | #define CKSCR 0xe61500c0 | 62 | #define CKSCR IOMEM(0xe61500c0) |
| 63 | 63 | ||
| 64 | /* Fixed 32 KHz root clock from EXTALR pin */ | 64 | /* Fixed 32 KHz root clock from EXTALR pin */ |
| 65 | static struct clk r_clk = { | 65 | static struct clk r_clk = { |