diff options
Diffstat (limited to 'arch/arm/mach-shmobile/clock-sh7377.c')
| -rw-r--r-- | arch/arm/mach-shmobile/clock-sh7377.c | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c index 85f2a3ec2c44..b8480d19e1c8 100644 --- a/arch/arm/mach-shmobile/clock-sh7377.c +++ b/arch/arm/mach-shmobile/clock-sh7377.c | |||
| @@ -24,31 +24,31 @@ | |||
| 24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 25 | 25 | ||
| 26 | /* SH7377 registers */ | 26 | /* SH7377 registers */ |
| 27 | #define RTFRQCR 0xe6150000 | 27 | #define RTFRQCR IOMEM(0xe6150000) |
| 28 | #define SYFRQCR 0xe6150004 | 28 | #define SYFRQCR IOMEM(0xe6150004) |
| 29 | #define CMFRQCR 0xe61500E0 | 29 | #define CMFRQCR IOMEM(0xe61500E0) |
| 30 | #define VCLKCR1 0xe6150008 | 30 | #define VCLKCR1 IOMEM(0xe6150008) |
| 31 | #define VCLKCR2 0xe615000C | 31 | #define VCLKCR2 IOMEM(0xe615000C) |
| 32 | #define VCLKCR3 0xe615001C | 32 | #define VCLKCR3 IOMEM(0xe615001C) |
| 33 | #define FMSICKCR 0xe6150010 | 33 | #define FMSICKCR IOMEM(0xe6150010) |
| 34 | #define FMSOCKCR 0xe6150014 | 34 | #define FMSOCKCR IOMEM(0xe6150014) |
| 35 | #define FSICKCR 0xe6150018 | 35 | #define FSICKCR IOMEM(0xe6150018) |
| 36 | #define PLLC1CR 0xe6150028 | 36 | #define PLLC1CR IOMEM(0xe6150028) |
| 37 | #define PLLC2CR 0xe615002C | 37 | #define PLLC2CR IOMEM(0xe615002C) |
| 38 | #define SUBUSBCKCR 0xe6150080 | 38 | #define SUBUSBCKCR IOMEM(0xe6150080) |
| 39 | #define SPUCKCR 0xe6150084 | 39 | #define SPUCKCR IOMEM(0xe6150084) |
| 40 | #define MSUCKCR 0xe6150088 | 40 | #define MSUCKCR IOMEM(0xe6150088) |
| 41 | #define MVI3CKCR 0xe6150090 | 41 | #define MVI3CKCR IOMEM(0xe6150090) |
| 42 | #define HDMICKCR 0xe6150094 | 42 | #define HDMICKCR IOMEM(0xe6150094) |
| 43 | #define MFCK1CR 0xe6150098 | 43 | #define MFCK1CR IOMEM(0xe6150098) |
| 44 | #define MFCK2CR 0xe615009C | 44 | #define MFCK2CR IOMEM(0xe615009C) |
| 45 | #define DSITCKCR 0xe6150060 | 45 | #define DSITCKCR IOMEM(0xe6150060) |
| 46 | #define DSIPCKCR 0xe6150064 | 46 | #define DSIPCKCR IOMEM(0xe6150064) |
| 47 | #define SMSTPCR0 0xe6150130 | 47 | #define SMSTPCR0 IOMEM(0xe6150130) |
| 48 | #define SMSTPCR1 0xe6150134 | 48 | #define SMSTPCR1 IOMEM(0xe6150134) |
| 49 | #define SMSTPCR2 0xe6150138 | 49 | #define SMSTPCR2 IOMEM(0xe6150138) |
| 50 | #define SMSTPCR3 0xe615013C | 50 | #define SMSTPCR3 IOMEM(0xe615013C) |
| 51 | #define SMSTPCR4 0xe6150140 | 51 | #define SMSTPCR4 IOMEM(0xe6150140) |
| 52 | 52 | ||
| 53 | /* Fixed 32 KHz root clock from EXTALR pin */ | 53 | /* Fixed 32 KHz root clock from EXTALR pin */ |
| 54 | static struct clk r_clk = { | 54 | static struct clk r_clk = { |