diff options
Diffstat (limited to 'arch/arm/mach-shmobile/clock-r8a7791.c')
-rw-r--r-- | arch/arm/mach-shmobile/clock-r8a7791.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index 701383fe3267..e2fdfcc14436 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/clkdev.h> | 25 | #include <linux/clkdev.h> |
26 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
27 | #include <mach/common.h> | 27 | #include <mach/common.h> |
28 | #include <mach/rcar-gen2.h> | ||
28 | 29 | ||
29 | /* | 30 | /* |
30 | * MD EXTAL PLL0 PLL1 PLL3 | 31 | * MD EXTAL PLL0 PLL1 PLL3 |
@@ -43,8 +44,6 @@ | |||
43 | * see "p1 / 2" on R8A7791_CLOCK_ROOT() below | 44 | * see "p1 / 2" on R8A7791_CLOCK_ROOT() below |
44 | */ | 45 | */ |
45 | 46 | ||
46 | #define MD(nr) (1 << nr) | ||
47 | |||
48 | #define CPG_BASE 0xe6150000 | 47 | #define CPG_BASE 0xe6150000 |
49 | #define CPG_LEN 0x1000 | 48 | #define CPG_LEN 0x1000 |
50 | 49 | ||
@@ -68,7 +67,6 @@ | |||
68 | #define MSTPSR9 IOMEM(0xe61509a4) | 67 | #define MSTPSR9 IOMEM(0xe61509a4) |
69 | #define MSTPSR11 IOMEM(0xe61509ac) | 68 | #define MSTPSR11 IOMEM(0xe61509ac) |
70 | 69 | ||
71 | #define MODEMR 0xE6160060 | ||
72 | #define SDCKCR 0xE6150074 | 70 | #define SDCKCR 0xE6150074 |
73 | #define SD1CKCR 0xE6150078 | 71 | #define SD1CKCR 0xE6150078 |
74 | #define SD2CKCR 0xE615026c | 72 | #define SD2CKCR 0xE615026c |
@@ -190,12 +188,12 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
190 | [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */ | 188 | [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */ |
191 | [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */ | 189 | [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */ |
192 | [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */ | 190 | [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */ |
193 | [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ | 191 | [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ |
194 | [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ | 192 | [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ |
195 | [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ | 193 | [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ |
196 | [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ | 194 | [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ |
197 | [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */ | 195 | [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */ |
198 | [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */ | 196 | [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */ |
199 | [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ | 197 | [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ |
200 | [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */ | 198 | [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */ |
201 | [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */ | 199 | [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */ |
@@ -266,7 +264,7 @@ static struct clk_lookup lookups[] = { | |||
266 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), | 264 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), |
267 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]), | 265 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]), |
268 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), | 266 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), |
269 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | 267 | CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]), |
270 | CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), | 268 | CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), |
271 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 269 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
272 | CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]), | 270 | CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]), |
@@ -295,14 +293,9 @@ static struct clk_lookup lookups[] = { | |||
295 | 293 | ||
296 | void __init r8a7791_clock_init(void) | 294 | void __init r8a7791_clock_init(void) |
297 | { | 295 | { |
298 | void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); | 296 | u32 mode = rcar_gen2_read_mode_pins(); |
299 | u32 mode; | ||
300 | int k, ret = 0; | 297 | int k, ret = 0; |
301 | 298 | ||
302 | BUG_ON(!modemr); | ||
303 | mode = ioread32(modemr); | ||
304 | iounmap(modemr); | ||
305 | |||
306 | switch (mode & (MD(14) | MD(13))) { | 299 | switch (mode & (MD(14) | MD(13))) { |
307 | case 0: | 300 | case 0: |
308 | R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); | 301 | R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); |