diff options
Diffstat (limited to 'arch/arm/mach-shark/irq.c')
-rw-r--r-- | arch/arm/mach-shark/irq.c | 108 |
1 files changed, 0 insertions, 108 deletions
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c deleted file mode 100644 index 5dce13e429f3..000000000000 --- a/arch/arm/mach-shark/irq.c +++ /dev/null | |||
@@ -1,108 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-shark/irq.c | ||
3 | * | ||
4 | * by Alexander Schulz | ||
5 | * | ||
6 | * derived from linux/arch/ppc/kernel/i8259.c and: | ||
7 | * arch/arm/mach-ebsa110/include/mach/irq.h | ||
8 | * Copyright (C) 1996-1998 Russell King | ||
9 | */ | ||
10 | |||
11 | #include <linux/init.h> | ||
12 | #include <linux/fs.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/io.h> | ||
15 | |||
16 | #include <asm/irq.h> | ||
17 | #include <asm/mach/irq.h> | ||
18 | |||
19 | /* | ||
20 | * 8259A PIC functions to handle ISA devices: | ||
21 | */ | ||
22 | |||
23 | /* | ||
24 | * This contains the irq mask for both 8259A irq controllers, | ||
25 | * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) | ||
26 | */ | ||
27 | static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; | ||
28 | |||
29 | /* | ||
30 | * These have to be protected by the irq controller spinlock | ||
31 | * before being called. | ||
32 | */ | ||
33 | static void shark_disable_8259A_irq(struct irq_data *d) | ||
34 | { | ||
35 | unsigned int mask; | ||
36 | if (d->irq<8) { | ||
37 | mask = 1 << d->irq; | ||
38 | cached_irq_mask[0] |= mask; | ||
39 | outb(cached_irq_mask[1],0xA1); | ||
40 | } else { | ||
41 | mask = 1 << (d->irq-8); | ||
42 | cached_irq_mask[1] |= mask; | ||
43 | outb(cached_irq_mask[0],0x21); | ||
44 | } | ||
45 | } | ||
46 | |||
47 | static void shark_enable_8259A_irq(struct irq_data *d) | ||
48 | { | ||
49 | unsigned int mask; | ||
50 | if (d->irq<8) { | ||
51 | mask = ~(1 << d->irq); | ||
52 | cached_irq_mask[0] &= mask; | ||
53 | outb(cached_irq_mask[0],0x21); | ||
54 | } else { | ||
55 | mask = ~(1 << (d->irq-8)); | ||
56 | cached_irq_mask[1] &= mask; | ||
57 | outb(cached_irq_mask[1],0xA1); | ||
58 | } | ||
59 | } | ||
60 | |||
61 | static void shark_ack_8259A_irq(struct irq_data *d){} | ||
62 | |||
63 | static irqreturn_t bogus_int(int irq, void *dev_id) | ||
64 | { | ||
65 | printk("Got interrupt %i!\n",irq); | ||
66 | return IRQ_NONE; | ||
67 | } | ||
68 | |||
69 | static struct irqaction cascade; | ||
70 | |||
71 | static struct irq_chip fb_chip = { | ||
72 | .name = "XT-PIC", | ||
73 | .irq_ack = shark_ack_8259A_irq, | ||
74 | .irq_mask = shark_disable_8259A_irq, | ||
75 | .irq_unmask = shark_enable_8259A_irq, | ||
76 | }; | ||
77 | |||
78 | void __init shark_init_irq(void) | ||
79 | { | ||
80 | int irq; | ||
81 | |||
82 | for (irq = 0; irq < NR_IRQS; irq++) { | ||
83 | irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); | ||
84 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
85 | } | ||
86 | |||
87 | /* init master interrupt controller */ | ||
88 | outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/ | ||
89 | outb(0x00, 0x21); /* Vector base */ | ||
90 | outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ | ||
91 | outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ | ||
92 | outb(0x0A, 0x20); | ||
93 | /* init slave interrupt controller */ | ||
94 | outb(0x11, 0xA0); /* Start init sequence, edge triggered */ | ||
95 | outb(0x08, 0xA1); /* Vector base */ | ||
96 | outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ | ||
97 | outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ | ||
98 | outb(0x0A, 0xA0); | ||
99 | outb(cached_irq_mask[1],0xA1); | ||
100 | outb(cached_irq_mask[0],0x21); | ||
101 | //request_region(0x20,0x2,"pic1"); | ||
102 | //request_region(0xA0,0x2,"pic2"); | ||
103 | |||
104 | cascade.handler = bogus_int; | ||
105 | cascade.name = "cascade"; | ||
106 | setup_irq(2,&cascade); | ||
107 | } | ||
108 | |||