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-rw-r--r--arch/arm/mach-sa1100/include/mach/assabet.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/cerf.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-sa1100/include/mach/nanoengine.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/simpad.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/system.h9
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c8
8 files changed, 28 insertions, 55 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 28c2cf50c259..307391488c22 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,21 +85,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
85#define ASSABET_BSR_RAD_RI (1 << 31) 85#define ASSABET_BSR_RAD_RI (1 << 31)
86 86
87 87
88/* GPIOs for which the generic definition doesn't say much */ 88/* GPIOs (bitmasks) for which the generic definition doesn't say much */
89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ 89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ 90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ 91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
92#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
93#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
94#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
95#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ 92#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
96#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
97#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ 93#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
98#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ 94#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
99 95
100#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 96/* These are gpiolib GPIO numbers, not bitmasks */
101#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 97#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */
102#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 98#define ASSABET_GPIO_CF_CD 22 /* CF CD */
103#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 99#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */
100#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
104 101
105#endif 102#endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index c3ac3d0f9465..88fd9c006ce0 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,15 +14,10 @@
14#define CERF_ETH_IO 0xf0000000 14#define CERF_ETH_IO 0xf0000000
15#define CERF_ETH_IRQ IRQ_GPIO26 15#define CERF_ETH_IRQ IRQ_GPIO26
16 16
17#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) 17#define CERF_GPIO_CF_BVD2 19
18#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) 18#define CERF_GPIO_CF_BVD1 20
19#define CERF_GPIO_CF_RESET GPIO_GPIO (21) 19#define CERF_GPIO_CF_RESET 21
20#define CERF_GPIO_CF_IRQ GPIO_GPIO (22) 20#define CERF_GPIO_CF_IRQ 22
21#define CERF_GPIO_CF_CD GPIO_GPIO (23) 21#define CERF_GPIO_CF_CD 23
22
23#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19
24#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20
25#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22
26#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23
27 22
28#endif // _INCLUDE_CERF_H_ 23#endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 6aa13c46c5d3..8cf7630bf024 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,17 +8,11 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11 .macro disable_fiq
12 .endm
13
14 .macro get_irqnr_preamble, base, tmp 11 .macro get_irqnr_preamble, base, tmp
15 mov \base, #0xfa000000 @ ICIP = 0xfa050000 12 mov \base, #0xfa000000 @ ICIP = 0xfa050000
16 add \base, \base, #0x00050000 13 add \base, \base, #0x00050000
17 .endm 14 .endm
18 15
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 ldr \irqstat, [\base] @ get irqs 17 ldr \irqstat, [\base] @ get irqs
24 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 18 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 14f8382d0665..5ebd469a31f2 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
16 16
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/ 19#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/
20#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */ 20#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */
21#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */ 21#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */
22#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */ 22#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */
23#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */ 23#define GPIO_PC_RESET0 15 /* reset socket 0 */
24#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */ 24#define GPIO_PC_RESET1 16 /* reset socket 1 */
25 25
26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e12140..019f857a7938 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -23,14 +23,10 @@
23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ 24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
25/* XXX GPIO 23 unaccounted for */ 25/* XXX GPIO 23 unaccounted for */
26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ 26#define SHANNON_GPIO_EJECT_0 24 /* in */
27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 27#define SHANNON_GPIO_EJECT_1 25 /* in */
28#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ 28#define SHANNON_GPIO_RDY_0 26 /* in */
29#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 29#define SHANNON_GPIO_RDY_1 27 /* in */
30#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
31#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
32#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
33#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
34 30
35/* MCP UCB codec GPIO pins... */ 31/* MCP UCB codec GPIO pins... */
36 32
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index db28118103eb..cdea671e8931 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,10 +39,8 @@
39 39
40 40
41/*--- PCMCIA ---*/ 41/*--- PCMCIA ---*/
42#define GPIO_CF_CD GPIO_GPIO24 42#define GPIO_CF_CD 24
43#define GPIO_CF_IRQ GPIO_GPIO1 43#define GPIO_CF_IRQ 1
44#define IRQ_GPIO_CF_IRQ IRQ_GPIO1
45#define IRQ_GPIO_CF_CD IRQ_GPIO24
46 44
47/*--- SmartCard ---*/ 45/*--- SmartCard ---*/
48#define GPIO_SMART_CARD GPIO_GPIO10 46#define GPIO_SMART_CARD GPIO_GPIO10
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
deleted file mode 100644
index e17b208f76d4..000000000000
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * arch/arm/mach-sa1100/include/mach/system.h
3 *
4 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
5 */
6static inline void arch_idle(void)
7{
8 cpu_do_idle();
9}
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index 0d01ca788922..b466bca9c651 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -244,9 +244,11 @@ static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
244 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); 244 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
245 return -EBUSY; 245 return -EBUSY;
246 } 246 }
247 pci_add_resource(&sys->resources, &pci_io_ports); 247 pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
248 pci_add_resource(&sys->resources, &pci_non_prefetchable_memory); 248 pci_add_resource_offset(&sys->resources,
249 pci_add_resource(&sys->resources, &pci_prefetchable_memory); 249 &pci_non_prefetchable_memory, sys->mem_offset);
250 pci_add_resource_offset(&sys->resources,
251 &pci_prefetchable_memory, sys->mem_offset);
250 252
251 return 1; 253 return 1;
252} 254}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 11:39:22 -0500