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-rw-r--r--arch/arm/mach-sa1100/time.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 4852c08cb526..1dea6cfafb31 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -9,6 +9,7 @@
9 * 9 *
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h>
12#include <linux/errno.h> 13#include <linux/errno.h>
13#include <linux/interrupt.h> 14#include <linux/interrupt.h>
14#include <linux/irq.h> 15#include <linux/irq.h>
@@ -20,6 +21,9 @@
20#include <mach/hardware.h> 21#include <mach/hardware.h>
21#include <mach/irqs.h> 22#include <mach/irqs.h>
22 23
24#define SA1100_CLOCK_FREQ 3686400
25#define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ)
26
23static u64 notrace sa1100_read_sched_clock(void) 27static u64 notrace sa1100_read_sched_clock(void)
24{ 28{
25 return readl_relaxed(OSCR); 29 return readl_relaxed(OSCR);
@@ -93,7 +97,7 @@ static void sa1100_timer_resume(struct clock_event_device *cedev)
93 /* 97 /*
94 * OSMR0 is the system timer: make sure OSCR is sufficiently behind 98 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
95 */ 99 */
96 writel_relaxed(OSMR0 - LATCH, OSCR); 100 writel_relaxed(OSMR0 - SA1100_LATCH, OSCR);
97} 101}
98#else 102#else
99#define sa1100_timer_suspend NULL 103#define sa1100_timer_suspend NULL
@@ -128,7 +132,7 @@ void __init sa1100_timer_init(void)
128 132
129 setup_irq(IRQ_OST0, &sa1100_timer_irq); 133 setup_irq(IRQ_OST0, &sa1100_timer_irq);
130 134
131 clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, 135 clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32,
132 clocksource_mmio_readl_up); 136 clocksource_mmio_readl_up);
133 clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, 137 clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
134 MIN_OSCR_DELTA * 2, 0x7fffffff); 138 MIN_OSCR_DELTA * 2, 0x7fffffff);