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-rw-r--r--arch/arm/mach-sa1100/sleep.S52
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 171441f96710..80f31bad707c 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -100,36 +100,36 @@ ENTRY(sa1100_cpu_suspend)
100 ldr r1, =MSC1 100 ldr r1, =MSC1
101 ldr r2, =MSC2 101 ldr r2, =MSC2
102 102
103 ldr r3, [r0] 103 ldr r3, [r0]
104 bic r3, r3, #FMsk(MSC_RT) 104 bic r3, r3, #FMsk(MSC_RT)
105 bic r3, r3, #FMsk(MSC_RT)<<16 105 bic r3, r3, #FMsk(MSC_RT)<<16
106 106
107 ldr r4, [r1] 107 ldr r4, [r1]
108 bic r4, r4, #FMsk(MSC_RT) 108 bic r4, r4, #FMsk(MSC_RT)
109 bic r4, r4, #FMsk(MSC_RT)<<16 109 bic r4, r4, #FMsk(MSC_RT)<<16
110 110
111 ldr r5, [r2] 111 ldr r5, [r2]
112 bic r5, r5, #FMsk(MSC_RT) 112 bic r5, r5, #FMsk(MSC_RT)
113 bic r5, r5, #FMsk(MSC_RT)<<16 113 bic r5, r5, #FMsk(MSC_RT)<<16
114 114
115 ldr r6, =MDREFR 115 ldr r6, =MDREFR
116 116
117 ldr r7, [r6] 117 ldr r7, [r6]
118 bic r7, r7, #0x0000FF00 118bic r7, r7, #0x0000FF00
119 bic r7, r7, #0x000000F0 119bic r7, r7, #0x000000F0
120 orr r8, r7, #MDREFR_SLFRSH 120orr r8, r7, #MDREFR_SLFRSH
121 121
122 ldr r9, =MDCNFG 122 ldr r9, =MDCNFG
123 ldr r10, [r9] 123 ldr r10, [r9]
124 bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) 124 bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
125 bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) 125 bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
126 126
127 bic r11, r8, #MDREFR_SLFRSH 127 bic r11, r8, #MDREFR_SLFRSH
128 bic r11, r11, #MDREFR_E1PIN 128 bic r11, r11, #MDREFR_E1PIN
129 129
130 ldr r12, =PMCR 130 ldr r12, =PMCR
131 131
132 mov r13, #PMCR_SF 132 mov r13, #PMCR_SF
133 133
134 b sa1110_sdram_controller_fix 134 b sa1110_sdram_controller_fix
135 135
@@ -188,10 +188,10 @@ ENTRY(sa1100_cpu_resume)
188 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs 188 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache 189 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
190 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB 190 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
191 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB 191 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
192 192
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID 193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
194 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr 194 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
195 mcr p15, 0, r6, c13, c0, 0 @ PID 195 mcr p15, 0, r6, c13, c0, 0 @ PID
196 b resume_turn_on_mmu @ cache align execution 196 b resume_turn_on_mmu @ cache align execution
197 197
@@ -209,7 +209,7 @@ sleep_save_sp:
209 209
210 .text 210 .text
211resume_after_mmu: 211resume_after_mmu:
212 mcr p15, 0, r1, c15, c1, 2 @ enable clock switching 212 mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
213 ldmfd sp!, {r4 - r12, pc} @ return to caller 213 ldmfd sp!, {r4 - r12, pc} @ return to caller
214 214
215 215