diff options
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
30 files changed, 5237 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h new file mode 100644 index 000000000000..62aaf04a3906 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h | |||
| @@ -0,0 +1,2072 @@ | |||
| 1 | /* | ||
| 2 | * FILE SA-1100.h | ||
| 3 | * | ||
| 4 | * Version 1.2 | ||
| 5 | * Author Copyright (c) Marc A. Viredaz, 1998 | ||
| 6 | * DEC Western Research Laboratory, Palo Alto, CA | ||
| 7 | * Date January 1998 (April 1997) | ||
| 8 | * System StrongARM SA-1100 | ||
| 9 | * Language C or ARM Assembly | ||
| 10 | * Purpose Definition of constants related to the StrongARM | ||
| 11 | * SA-1100 microprocessor (Advanced RISC Machine (ARM) | ||
| 12 | * architecture version 4). This file is based on the | ||
| 13 | * StrongARM SA-1100 data sheet version 2.2. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | /* Be sure that virtual mapping is defined right */ | ||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 20 | #error You must include hardware.h not SA-1100.h | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #include "bitfield.h" | ||
| 24 | |||
| 25 | /* | ||
| 26 | * SA1100 CS line to physical address | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define SA1100_CS0_PHYS 0x00000000 | ||
| 30 | #define SA1100_CS1_PHYS 0x08000000 | ||
| 31 | #define SA1100_CS2_PHYS 0x10000000 | ||
| 32 | #define SA1100_CS3_PHYS 0x18000000 | ||
| 33 | #define SA1100_CS4_PHYS 0x40000000 | ||
| 34 | #define SA1100_CS5_PHYS 0x48000000 | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 41 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 42 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 43 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 44 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 45 | |||
| 46 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 47 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 48 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 49 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 50 | |||
| 51 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 52 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 53 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 54 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 55 | |||
| 56 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 57 | (0x20000000 + (Nb)*PCMCIASp) | ||
| 58 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | ||
| 59 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 60 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | ||
| 61 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 62 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | ||
| 63 | |||
| 64 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | ||
| 65 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | ||
| 66 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | ||
| 67 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | ||
| 68 | |||
| 69 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | ||
| 70 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | ||
| 71 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | ||
| 72 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | ||
| 73 | |||
| 74 | |||
| 75 | /* | ||
| 76 | * Universal Serial Bus (USB) Device Controller (UDC) control registers | ||
| 77 | * | ||
| 78 | * Registers | ||
| 79 | * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device | ||
| 80 | * Controller (UDC) Control Register (read/write). | ||
| 81 | * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device | ||
| 82 | * Controller (UDC) Address Register (read/write). | ||
| 83 | * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device | ||
| 84 | * Controller (UDC) Output Maximum Packet size register | ||
| 85 | * (read/write). | ||
| 86 | * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device | ||
| 87 | * Controller (UDC) Input Maximum Packet size register | ||
| 88 | * (read/write). | ||
| 89 | * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device | ||
| 90 | * Controller (UDC) Control/Status register end-point 0 | ||
| 91 | * (read/write). | ||
| 92 | * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device | ||
| 93 | * Controller (UDC) Control/Status register end-point 1 | ||
| 94 | * (output, read/write). | ||
| 95 | * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device | ||
| 96 | * Controller (UDC) Control/Status register end-point 2 | ||
| 97 | * (input, read/write). | ||
| 98 | * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device | ||
| 99 | * Controller (UDC) Data register end-point 0 | ||
| 100 | * (read/write). | ||
| 101 | * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device | ||
| 102 | * Controller (UDC) Write Count register end-point 0 | ||
| 103 | * (read). | ||
| 104 | * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device | ||
| 105 | * Controller (UDC) Data Register (read/write). | ||
| 106 | * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device | ||
| 107 | * Controller (UDC) Status Register (read/write). | ||
| 108 | */ | ||
| 109 | |||
| 110 | #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ | ||
| 111 | #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ | ||
| 112 | #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ | ||
| 113 | #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ | ||
| 114 | #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ | ||
| 115 | #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ | ||
| 116 | #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ | ||
| 117 | #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ | ||
| 118 | #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ | ||
| 119 | #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ | ||
| 120 | #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ | ||
| 121 | |||
| 122 | #define UDCCR_UDD 0x00000001 /* UDC Disable */ | ||
| 123 | #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ | ||
| 124 | #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ | ||
| 125 | #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ | ||
| 126 | /* (disable) */ | ||
| 127 | #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ | ||
| 128 | /* (disable) */ | ||
| 129 | #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ | ||
| 130 | /* (disable) */ | ||
| 131 | #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ | ||
| 132 | /* (disable) */ | ||
| 133 | #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ | ||
| 134 | #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ | ||
| 135 | |||
| 136 | #define UDCAR_ADD Fld (7, 0) /* function ADDress */ | ||
| 137 | |||
| 138 | #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ | ||
| 139 | /* [byte] */ | ||
| 140 | #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ | ||
| 141 | /* [1..256 byte] */ \ | ||
| 142 | (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) | ||
| 143 | |||
| 144 | #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ | ||
| 145 | /* [byte] */ | ||
| 146 | #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ | ||
| 147 | /* [1..256 byte] */ \ | ||
| 148 | (((Size) - 1) << FShft (UDCIMP_INMAXP)) | ||
| 149 | |||
| 150 | #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ | ||
| 151 | #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ | ||
| 152 | #define UDCCS0_SST 0x00000004 /* Sent STall */ | ||
| 153 | #define UDCCS0_FST 0x00000008 /* Force STall */ | ||
| 154 | #define UDCCS0_DE 0x00000010 /* Data End */ | ||
| 155 | #define UDCCS0_SE 0x00000020 /* Setup End (read) */ | ||
| 156 | #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ | ||
| 157 | /* (write) */ | ||
| 158 | #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ | ||
| 159 | |||
| 160 | #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ | ||
| 161 | /* Service request (read) */ | ||
| 162 | #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ | ||
| 163 | #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ | ||
| 164 | #define UDCCS1_SST 0x00000008 /* Sent STall */ | ||
| 165 | #define UDCCS1_FST 0x00000010 /* Force STall */ | ||
| 166 | #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ | ||
| 167 | |||
| 168 | #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ | ||
| 169 | /* Service request (read) */ | ||
| 170 | #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ | ||
| 171 | #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ | ||
| 172 | #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ | ||
| 173 | #define UDCCS2_SST 0x00000010 /* Sent STall */ | ||
| 174 | #define UDCCS2_FST 0x00000020 /* Force STall */ | ||
| 175 | |||
| 176 | #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 177 | |||
| 178 | #define UDCWC_WC Fld (4, 0) /* Write Count */ | ||
| 179 | |||
| 180 | #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 181 | |||
| 182 | #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ | ||
| 183 | #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ | ||
| 184 | #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ | ||
| 185 | #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ | ||
| 186 | #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ | ||
| 187 | #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ | ||
| 188 | |||
| 189 | |||
| 190 | /* | ||
| 191 | * Universal Asynchronous Receiver/Transmitter (UART) control registers | ||
| 192 | * | ||
| 193 | * Registers | ||
| 194 | * Ser1UTCR0 Serial port 1 Universal Asynchronous | ||
| 195 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 196 | * (read/write). | ||
| 197 | * Ser1UTCR1 Serial port 1 Universal Asynchronous | ||
| 198 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 199 | * (read/write). | ||
| 200 | * Ser1UTCR2 Serial port 1 Universal Asynchronous | ||
| 201 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 202 | * (read/write). | ||
| 203 | * Ser1UTCR3 Serial port 1 Universal Asynchronous | ||
| 204 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 205 | * (read/write). | ||
| 206 | * Ser1UTDR Serial port 1 Universal Asynchronous | ||
| 207 | * Receiver/Transmitter (UART) Data Register | ||
| 208 | * (read/write). | ||
| 209 | * Ser1UTSR0 Serial port 1 Universal Asynchronous | ||
| 210 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 211 | * (read/write). | ||
| 212 | * Ser1UTSR1 Serial port 1 Universal Asynchronous | ||
| 213 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 214 | * | ||
| 215 | * Ser2UTCR0 Serial port 2 Universal Asynchronous | ||
| 216 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 217 | * (read/write). | ||
| 218 | * Ser2UTCR1 Serial port 2 Universal Asynchronous | ||
| 219 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 220 | * (read/write). | ||
| 221 | * Ser2UTCR2 Serial port 2 Universal Asynchronous | ||
| 222 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 223 | * (read/write). | ||
| 224 | * Ser2UTCR3 Serial port 2 Universal Asynchronous | ||
| 225 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 226 | * (read/write). | ||
| 227 | * Ser2UTCR4 Serial port 2 Universal Asynchronous | ||
| 228 | * Receiver/Transmitter (UART) Control Register 4 | ||
| 229 | * (read/write). | ||
| 230 | * Ser2UTDR Serial port 2 Universal Asynchronous | ||
| 231 | * Receiver/Transmitter (UART) Data Register | ||
| 232 | * (read/write). | ||
| 233 | * Ser2UTSR0 Serial port 2 Universal Asynchronous | ||
| 234 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 235 | * (read/write). | ||
| 236 | * Ser2UTSR1 Serial port 2 Universal Asynchronous | ||
| 237 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 238 | * | ||
| 239 | * Ser3UTCR0 Serial port 3 Universal Asynchronous | ||
| 240 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 241 | * (read/write). | ||
| 242 | * Ser3UTCR1 Serial port 3 Universal Asynchronous | ||
| 243 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 244 | * (read/write). | ||
| 245 | * Ser3UTCR2 Serial port 3 Universal Asynchronous | ||
| 246 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 247 | * (read/write). | ||
| 248 | * Ser3UTCR3 Serial port 3 Universal Asynchronous | ||
| 249 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 250 | * (read/write). | ||
| 251 | * Ser3UTDR Serial port 3 Universal Asynchronous | ||
| 252 | * Receiver/Transmitter (UART) Data Register | ||
| 253 | * (read/write). | ||
| 254 | * Ser3UTSR0 Serial port 3 Universal Asynchronous | ||
| 255 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 256 | * (read/write). | ||
| 257 | * Ser3UTSR1 Serial port 3 Universal Asynchronous | ||
| 258 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 259 | * | ||
| 260 | * Clocks | ||
| 261 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 262 | * or 3.5795 MHz). | ||
| 263 | * fua, Tua Frequency, period of the UART communication. | ||
| 264 | */ | ||
| 265 | |||
| 266 | #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ | ||
| 267 | #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ | ||
| 268 | #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ | ||
| 269 | #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ | ||
| 270 | #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ | ||
| 271 | #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ | ||
| 272 | #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ | ||
| 273 | #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ | ||
| 274 | |||
| 275 | #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ | ||
| 276 | #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ | ||
| 277 | #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ | ||
| 278 | #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ | ||
| 279 | #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ | ||
| 280 | #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ | ||
| 281 | #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ | ||
| 282 | |||
| 283 | #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ | ||
| 284 | #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ | ||
| 285 | #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ | ||
| 286 | #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ | ||
| 287 | #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ | ||
| 288 | #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ | ||
| 289 | #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ | ||
| 290 | #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ | ||
| 291 | |||
| 292 | #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ | ||
| 293 | #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ | ||
| 294 | #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ | ||
| 295 | #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ | ||
| 296 | #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ | ||
| 297 | #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ | ||
| 298 | #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ | ||
| 299 | |||
| 300 | /* Those are still used in some places */ | ||
| 301 | #define _Ser1UTCR0 __PREG(Ser1UTCR0) | ||
| 302 | #define _Ser2UTCR0 __PREG(Ser2UTCR0) | ||
| 303 | #define _Ser3UTCR0 __PREG(Ser3UTCR0) | ||
| 304 | |||
| 305 | /* Register offsets */ | ||
| 306 | #define UTCR0 0x00 | ||
| 307 | #define UTCR1 0x04 | ||
| 308 | #define UTCR2 0x08 | ||
| 309 | #define UTCR3 0x0c | ||
| 310 | #define UTDR 0x14 | ||
| 311 | #define UTSR0 0x1c | ||
| 312 | #define UTSR1 0x20 | ||
| 313 | |||
| 314 | #define UTCR0_PE 0x00000001 /* Parity Enable */ | ||
| 315 | #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ | ||
| 316 | #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ | ||
| 317 | #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ | ||
| 318 | #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ | ||
| 319 | #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ | ||
| 320 | #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ | ||
| 321 | #define UTCR0_DSS 0x00000008 /* Data Size Select */ | ||
| 322 | #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ | ||
| 323 | #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ | ||
| 324 | #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ | ||
| 325 | /* (ser. port 1: GPIO [18], */ | ||
| 326 | /* ser. port 3: GPIO [20]) */ | ||
| 327 | #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ | ||
| 328 | #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ | ||
| 329 | #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ | ||
| 330 | #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ | ||
| 331 | #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ | ||
| 332 | #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ | ||
| 333 | #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ | ||
| 334 | (UTCR0_1StpBit + UTCR0_8BitData) | ||
| 335 | |||
| 336 | #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ | ||
| 337 | #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ | ||
| 338 | /* fua = fxtl/(16*(BRD[11:0] + 1)) */ | ||
| 339 | /* Tua = 16*(BRD [11:0] + 1)*Txtl */ | ||
| 340 | #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 341 | (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ | ||
| 342 | FShft (UTCR1_BRD)) | ||
| 343 | #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 344 | (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ | ||
| 345 | FShft (UTCR2_BRD)) | ||
| 346 | /* fua = fxtl/(16*Floor (Div/16)) */ | ||
| 347 | /* Tua = 16*Floor (Div/16)*Txtl */ | ||
| 348 | #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 349 | (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ | ||
| 350 | FShft (UTCR1_BRD)) | ||
| 351 | #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 352 | (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ | ||
| 353 | FShft (UTCR2_BRD)) | ||
| 354 | /* fua = fxtl/(16*Ceil (Div/16)) */ | ||
| 355 | /* Tua = 16*Ceil (Div/16)*Txtl */ | ||
| 356 | |||
| 357 | #define UTCR3_RXE 0x00000001 /* Receive Enable */ | ||
| 358 | #define UTCR3_TXE 0x00000002 /* Transmit Enable */ | ||
| 359 | #define UTCR3_BRK 0x00000004 /* BReaK mode */ | ||
| 360 | #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 361 | /* more Interrupt Enable */ | ||
| 362 | #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 363 | /* Interrupt Enable */ | ||
| 364 | #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ | ||
| 365 | #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ | ||
| 366 | /* TIE, LBM can be set or cleared) */ \ | ||
| 367 | (UTCR3_RXE + UTCR3_TXE) | ||
| 368 | |||
| 369 | #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ | ||
| 370 | /* (HP-SIR) modulation Enable */ | ||
| 371 | #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ | ||
| 372 | #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ | ||
| 373 | #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ | ||
| 374 | #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ | ||
| 375 | #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ | ||
| 376 | |||
| 377 | #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 378 | #if 0 /* Hidden receive FIFO bits */ | ||
| 379 | #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ | ||
| 380 | #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ | ||
| 381 | #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 382 | #endif /* 0 */ | ||
| 383 | |||
| 384 | #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ | ||
| 385 | /* Service request (read) */ | ||
| 386 | #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 387 | /* more Service request (read) */ | ||
| 388 | #define UTSR0_RID 0x00000004 /* Receiver IDle */ | ||
| 389 | #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ | ||
| 390 | #define UTSR0_REB 0x00000010 /* Receive End of Break */ | ||
| 391 | #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ | ||
| 392 | |||
| 393 | #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ | ||
| 394 | #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ | ||
| 395 | #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ | ||
| 396 | #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ | ||
| 397 | #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ | ||
| 398 | #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ | ||
| 399 | |||
| 400 | |||
| 401 | /* | ||
| 402 | * Synchronous Data Link Controller (SDLC) control registers | ||
| 403 | * | ||
| 404 | * Registers | ||
| 405 | * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 406 | * Control Register 0 (read/write). | ||
| 407 | * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 408 | * Control Register 1 (read/write). | ||
| 409 | * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 410 | * Control Register 2 (read/write). | ||
| 411 | * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 412 | * Control Register 3 (read/write). | ||
| 413 | * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 414 | * Control Register 4 (read/write). | ||
| 415 | * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 416 | * Data Register (read/write). | ||
| 417 | * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 418 | * Status Register 0 (read/write). | ||
| 419 | * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 420 | * Status Register 1 (read/write). | ||
| 421 | * | ||
| 422 | * Clocks | ||
| 423 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 424 | * or 3.5795 MHz). | ||
| 425 | * fsd, Tsd Frequency, period of the SDLC communication. | ||
| 426 | */ | ||
| 427 | |||
| 428 | #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ | ||
| 429 | #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ | ||
| 430 | #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ | ||
| 431 | #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ | ||
| 432 | #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ | ||
| 433 | #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ | ||
| 434 | #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ | ||
| 435 | #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ | ||
| 436 | |||
| 437 | #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ | ||
| 438 | #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ | ||
| 439 | #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ | ||
| 440 | #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ | ||
| 441 | #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ | ||
| 442 | #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ | ||
| 443 | #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ | ||
| 444 | #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ | ||
| 445 | #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ | ||
| 446 | #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ | ||
| 447 | #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ | ||
| 448 | #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ | ||
| 449 | /* (GPIO [16]) */ | ||
| 450 | #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ | ||
| 451 | #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ | ||
| 452 | #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ | ||
| 453 | #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ | ||
| 454 | #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ | ||
| 455 | #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ | ||
| 456 | #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ | ||
| 457 | #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ | ||
| 458 | |||
| 459 | #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ | ||
| 460 | /* (GPIO [17]) */ | ||
| 461 | #define SDCR1_TXE 0x00000002 /* Transmit Enable */ | ||
| 462 | #define SDCR1_RXE 0x00000004 /* Receive Enable */ | ||
| 463 | #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 464 | /* more Interrupt Enable */ | ||
| 465 | #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 466 | /* Interrupt Enable */ | ||
| 467 | #define SDCR1_AME 0x00000020 /* Address Match Enable */ | ||
| 468 | #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ | ||
| 469 | #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ | ||
| 470 | #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ | ||
| 471 | #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ | ||
| 472 | |||
| 473 | #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ | ||
| 474 | |||
| 475 | #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ | ||
| 476 | #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ | ||
| 477 | /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ | ||
| 478 | /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ | ||
| 479 | #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 480 | (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ | ||
| 481 | FShft (SDCR3_BRD)) | ||
| 482 | #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 483 | (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ | ||
| 484 | FShft (SDCR4_BRD)) | ||
| 485 | /* fsd = fxtl/(16*Floor (Div/16)) */ | ||
| 486 | /* Tsd = 16*Floor (Div/16)*Txtl */ | ||
| 487 | #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 488 | (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ | ||
| 489 | FShft (SDCR3_BRD)) | ||
| 490 | #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 491 | (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ | ||
| 492 | FShft (SDCR4_BRD)) | ||
| 493 | /* fsd = fxtl/(16*Ceil (Div/16)) */ | ||
| 494 | /* Tsd = 16*Ceil (Div/16)*Txtl */ | ||
| 495 | |||
| 496 | #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 497 | #if 0 /* Hidden receive FIFO bits */ | ||
| 498 | #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ | ||
| 499 | #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ | ||
| 500 | #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 501 | #endif /* 0 */ | ||
| 502 | |||
| 503 | #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ | ||
| 504 | #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ | ||
| 505 | #define SDSR0_RAB 0x00000004 /* Receive ABort */ | ||
| 506 | #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ | ||
| 507 | /* Service request (read) */ | ||
| 508 | #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 509 | /* more Service request (read) */ | ||
| 510 | |||
| 511 | #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ | ||
| 512 | #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ | ||
| 513 | #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 514 | #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ | ||
| 515 | #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ | ||
| 516 | #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ | ||
| 517 | #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ | ||
| 518 | #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ | ||
| 519 | |||
| 520 | |||
| 521 | /* | ||
| 522 | * High-Speed Serial to Parallel controller (HSSP) control registers | ||
| 523 | * | ||
| 524 | * Registers | ||
| 525 | * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel | ||
| 526 | * controller (HSSP) Control Register 0 (read/write). | ||
| 527 | * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel | ||
| 528 | * controller (HSSP) Control Register 1 (read/write). | ||
| 529 | * Ser2HSDR Serial port 2 High-Speed Serial to Parallel | ||
| 530 | * controller (HSSP) Data Register (read/write). | ||
| 531 | * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel | ||
| 532 | * controller (HSSP) Status Register 0 (read/write). | ||
| 533 | * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel | ||
| 534 | * controller (HSSP) Status Register 1 (read). | ||
| 535 | * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel | ||
| 536 | * controller (HSSP) Control Register 2 (read/write). | ||
| 537 | * [The HSCR2 register is only implemented in | ||
| 538 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 539 | * SA-1100.] | ||
| 540 | */ | ||
| 541 | |||
| 542 | #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ | ||
| 543 | #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ | ||
| 544 | #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ | ||
| 545 | #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ | ||
| 546 | #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ | ||
| 547 | #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ | ||
| 548 | |||
| 549 | #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ | ||
| 550 | #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ | ||
| 551 | #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ | ||
| 552 | #define HSCR0_LBM 0x00000002 /* Look-Back Mode */ | ||
| 553 | #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ | ||
| 554 | #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ | ||
| 555 | #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ | ||
| 556 | #define HSCR0_TXE 0x00000008 /* Transmit Enable */ | ||
| 557 | #define HSCR0_RXE 0x00000010 /* Receive Enable */ | ||
| 558 | #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ | ||
| 559 | /* more Interrupt Enable */ | ||
| 560 | #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ | ||
| 561 | /* Interrupt Enable */ | ||
| 562 | #define HSCR0_AME 0x00000080 /* Address Match Enable */ | ||
| 563 | |||
| 564 | #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ | ||
| 565 | |||
| 566 | #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 567 | #if 0 /* Hidden receive FIFO bits */ | ||
| 568 | #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ | ||
| 569 | #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ | ||
| 570 | #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 571 | #endif /* 0 */ | ||
| 572 | |||
| 573 | #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ | ||
| 574 | #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ | ||
| 575 | #define HSSR0_RAB 0x00000004 /* Receive ABort */ | ||
| 576 | #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ | ||
| 577 | /* Service request (read) */ | ||
| 578 | #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ | ||
| 579 | /* more Service request (read) */ | ||
| 580 | #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ | ||
| 581 | |||
| 582 | #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ | ||
| 583 | #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ | ||
| 584 | #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 585 | #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ | ||
| 586 | #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ | ||
| 587 | #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ | ||
| 588 | #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ | ||
| 589 | |||
| 590 | #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ | ||
| 591 | #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ | ||
| 592 | /* (inverted) */ | ||
| 593 | #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ | ||
| 594 | /* (non-inverted) */ | ||
| 595 | #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ | ||
| 596 | #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ | ||
| 597 | /* (inverted) */ | ||
| 598 | #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ | ||
| 599 | /* (non-inverted) */ | ||
| 600 | |||
| 601 | |||
| 602 | /* | ||
| 603 | * Multi-media Communications Port (MCP) control registers | ||
| 604 | * | ||
| 605 | * Registers | ||
| 606 | * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) | ||
| 607 | * Control Register 0 (read/write). | ||
| 608 | * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) | ||
| 609 | * Data Register 0 (audio, read/write). | ||
| 610 | * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) | ||
| 611 | * Data Register 1 (telecom, read/write). | ||
| 612 | * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) | ||
| 613 | * Data Register 2 (CODEC registers, read/write). | ||
| 614 | * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) | ||
| 615 | * Status Register (read/write). | ||
| 616 | * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) | ||
| 617 | * Control Register 1 (read/write). | ||
| 618 | * [The MCCR1 register is only implemented in | ||
| 619 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 620 | * SA-1100.] | ||
| 621 | * | ||
| 622 | * Clocks | ||
| 623 | * fmc, Tmc Frequency, period of the MCP communication (10 MHz, | ||
| 624 | * 12 MHz, or GPIO [21]). | ||
| 625 | * faud, Taud Frequency, period of the audio sampling. | ||
| 626 | * ftcm, Ttcm Frequency, period of the telecom sampling. | ||
| 627 | */ | ||
| 628 | |||
| 629 | #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ | ||
| 630 | #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ | ||
| 631 | #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ | ||
| 632 | #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ | ||
| 633 | #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ | ||
| 634 | #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ | ||
| 635 | |||
| 636 | #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ | ||
| 637 | /* [6..127] */ | ||
| 638 | /* faud = fmc/(32*ASD) */ | ||
| 639 | /* Taud = 32*ASD*Tmc */ | ||
| 640 | #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ | ||
| 641 | /* [192..4064] */ \ | ||
| 642 | ((Div)/32 << FShft (MCCR0_ASD)) | ||
| 643 | /* faud = fmc/(32*Floor (Div/32)) */ | ||
| 644 | /* Taud = 32*Floor (Div/32)*Tmc */ | ||
| 645 | #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ | ||
| 646 | (((Div) + 31)/32 << FShft (MCCR0_ASD)) | ||
| 647 | /* faud = fmc/(32*Ceil (Div/32)) */ | ||
| 648 | /* Taud = 32*Ceil (Div/32)*Tmc */ | ||
| 649 | #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ | ||
| 650 | /* Divisor/32 [16..127] */ | ||
| 651 | /* ftcm = fmc/(32*TSD) */ | ||
| 652 | /* Ttcm = 32*TSD*Tmc */ | ||
| 653 | #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ | ||
| 654 | /* [512..4064] */ \ | ||
| 655 | ((Div)/32 << FShft (MCCR0_TSD)) | ||
| 656 | /* ftcm = fmc/(32*Floor (Div/32)) */ | ||
| 657 | /* Ttcm = 32*Floor (Div/32)*Tmc */ | ||
| 658 | #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ | ||
| 659 | (((Div) + 31)/32 << FShft (MCCR0_TSD)) | ||
| 660 | /* ftcm = fmc/(32*Ceil (Div/32)) */ | ||
| 661 | /* Ttcm = 32*Ceil (Div/32)*Tmc */ | ||
| 662 | #define MCCR0_MCE 0x00010000 /* MCP Enable */ | ||
| 663 | #define MCCR0_ECS 0x00020000 /* External Clock Select */ | ||
| 664 | #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ | ||
| 665 | #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ | ||
| 666 | #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ | ||
| 667 | /* sampling/storing Mode */ | ||
| 668 | #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ | ||
| 669 | #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ | ||
| 670 | #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ | ||
| 671 | /* or less interrupt Enable */ | ||
| 672 | #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ | ||
| 673 | /* or more interrupt Enable */ | ||
| 674 | #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ | ||
| 675 | /* or less interrupt Enable */ | ||
| 676 | #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ | ||
| 677 | /* more interrupt Enable */ | ||
| 678 | #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ | ||
| 679 | #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ | ||
| 680 | #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ | ||
| 681 | (((Div) - 1) << FShft (MCCR0_ECP)) | ||
| 682 | |||
| 683 | #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ | ||
| 684 | /* FIFOs */ | ||
| 685 | |||
| 686 | #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ | ||
| 687 | /* FIFOs */ | ||
| 688 | |||
| 689 | /* receive/transmit CODEC reg. */ | ||
| 690 | /* FIFOs: */ | ||
| 691 | #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ | ||
| 692 | #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ | ||
| 693 | #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ | ||
| 694 | #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ | ||
| 695 | #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ | ||
| 696 | |||
| 697 | #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ | ||
| 698 | /* or less Service request (read) */ | ||
| 699 | #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ | ||
| 700 | /* more Service request (read) */ | ||
| 701 | #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ | ||
| 702 | /* or less Service request (read) */ | ||
| 703 | #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ | ||
| 704 | /* or more Service request (read) */ | ||
| 705 | #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ | ||
| 706 | #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ | ||
| 707 | #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ | ||
| 708 | #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ | ||
| 709 | #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ | ||
| 710 | /* (read) */ | ||
| 711 | #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ | ||
| 712 | /* (read) */ | ||
| 713 | #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ | ||
| 714 | /* (read) */ | ||
| 715 | #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ | ||
| 716 | /* (read) */ | ||
| 717 | #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ | ||
| 718 | /* (read) */ | ||
| 719 | #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ | ||
| 720 | /* (read) */ | ||
| 721 | #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ | ||
| 722 | #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ | ||
| 723 | |||
| 724 | #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ | ||
| 725 | #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ | ||
| 726 | /* (11.981 MHz) */ | ||
| 727 | #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ | ||
| 728 | /* (9.585 MHz) */ | ||
| 729 | |||
| 730 | |||
| 731 | /* | ||
| 732 | * Synchronous Serial Port (SSP) control registers | ||
| 733 | * | ||
| 734 | * Registers | ||
| 735 | * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control | ||
| 736 | * Register 0 (read/write). | ||
| 737 | * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control | ||
| 738 | * Register 1 (read/write). | ||
| 739 | * [Bits SPO and SP are only implemented in versions 2.0 | ||
| 740 | * (rev. = 8) and higher of the StrongARM SA-1100.] | ||
| 741 | * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data | ||
| 742 | * Register (read/write). | ||
| 743 | * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status | ||
| 744 | * Register (read/write). | ||
| 745 | * | ||
| 746 | * Clocks | ||
| 747 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 748 | * or 3.5795 MHz). | ||
| 749 | * fss, Tss Frequency, period of the SSP communication. | ||
| 750 | */ | ||
| 751 | |||
| 752 | #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ | ||
| 753 | #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ | ||
| 754 | #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ | ||
| 755 | #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ | ||
| 756 | |||
| 757 | #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ | ||
| 758 | #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ | ||
| 759 | (((Size) - 1) << FShft (SSCR0_DSS)) | ||
| 760 | #define SSCR0_FRF Fld (2, 4) /* FRame Format */ | ||
| 761 | #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ | ||
| 762 | /* Interface (SPI) format */ \ | ||
| 763 | (0 << FShft (SSCR0_FRF)) | ||
| 764 | #define SSCR0_TI /* Texas Instruments Synchronous */ \ | ||
| 765 | /* Serial format */ \ | ||
| 766 | (1 << FShft (SSCR0_FRF)) | ||
| 767 | #define SSCR0_National /* National Microwire format */ \ | ||
| 768 | (2 << FShft (SSCR0_FRF)) | ||
| 769 | #define SSCR0_SSE 0x00000080 /* SSP Enable */ | ||
| 770 | #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ | ||
| 771 | /* fss = fxtl/(2*(SCR + 1)) */ | ||
| 772 | /* Tss = 2*(SCR + 1)*Txtl */ | ||
| 773 | #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ | ||
| 774 | (((Div) - 2)/2 << FShft (SSCR0_SCR)) | ||
| 775 | /* fss = fxtl/(2*Floor (Div/2)) */ | ||
| 776 | /* Tss = 2*Floor (Div/2)*Txtl */ | ||
| 777 | #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ | ||
| 778 | (((Div) - 1)/2 << FShft (SSCR0_SCR)) | ||
| 779 | /* fss = fxtl/(2*Ceil (Div/2)) */ | ||
| 780 | /* Tss = 2*Ceil (Div/2)*Txtl */ | ||
| 781 | |||
| 782 | #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ | ||
| 783 | /* Interrupt Enable */ | ||
| 784 | #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ | ||
| 785 | /* Interrupt Enable */ | ||
| 786 | #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ | ||
| 787 | #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ | ||
| 788 | #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ | ||
| 789 | #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ | ||
| 790 | #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ | ||
| 791 | #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ | ||
| 792 | /* after frame (SFRM, 1st edge) */ | ||
| 793 | #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ | ||
| 794 | /* after frame (SFRM, 1st edge) */ | ||
| 795 | #define SSCR1_ECS 0x00000020 /* External Clock Select */ | ||
| 796 | #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ | ||
| 797 | #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ | ||
| 798 | |||
| 799 | #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ | ||
| 800 | |||
| 801 | #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ | ||
| 802 | #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 803 | #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ | ||
| 804 | #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 805 | /* Service request (read) */ | ||
| 806 | #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ | ||
| 807 | /* Service request (read) */ | ||
| 808 | #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ | ||
| 809 | |||
| 810 | |||
| 811 | /* | ||
| 812 | * Operating System (OS) timer control registers | ||
| 813 | * | ||
| 814 | * Registers | ||
| 815 | * OSMR0 Operating System (OS) timer Match Register 0 | ||
| 816 | * (read/write). | ||
| 817 | * OSMR1 Operating System (OS) timer Match Register 1 | ||
| 818 | * (read/write). | ||
| 819 | * OSMR2 Operating System (OS) timer Match Register 2 | ||
| 820 | * (read/write). | ||
| 821 | * OSMR3 Operating System (OS) timer Match Register 3 | ||
| 822 | * (read/write). | ||
| 823 | * OSCR Operating System (OS) timer Counter Register | ||
| 824 | * (read/write). | ||
| 825 | * OSSR Operating System (OS) timer Status Register | ||
| 826 | * (read/write). | ||
| 827 | * OWER Operating System (OS) timer Watch-dog Enable Register | ||
| 828 | * (read/write). | ||
| 829 | * OIER Operating System (OS) timer Interrupt Enable Register | ||
| 830 | * (read/write). | ||
| 831 | */ | ||
| 832 | |||
| 833 | #define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */ | ||
| 834 | #define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */ | ||
| 835 | #define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */ | ||
| 836 | #define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */ | ||
| 837 | #define OSCR __REG(0x90000010) /* OS timer Counter Reg. */ | ||
| 838 | #define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */ | ||
| 839 | #define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */ | ||
| 840 | #define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */ | ||
| 841 | |||
| 842 | #define OSSR_M(Nb) /* Match detected [0..3] */ \ | ||
| 843 | (0x00000001 << (Nb)) | ||
| 844 | #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ | ||
| 845 | #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ | ||
| 846 | #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ | ||
| 847 | #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ | ||
| 848 | |||
| 849 | #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ | ||
| 850 | /* (set only) */ | ||
| 851 | |||
| 852 | #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ | ||
| 853 | (0x00000001 << (Nb)) | ||
| 854 | #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ | ||
| 855 | #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ | ||
| 856 | #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ | ||
| 857 | #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ | ||
| 858 | |||
| 859 | |||
| 860 | /* | ||
| 861 | * Real-Time Clock (RTC) control registers | ||
| 862 | * | ||
| 863 | * Registers | ||
| 864 | * RTAR Real-Time Clock (RTC) Alarm Register (read/write). | ||
| 865 | * RCNR Real-Time Clock (RTC) CouNt Register (read/write). | ||
| 866 | * RTTR Real-Time Clock (RTC) Trim Register (read/write). | ||
| 867 | * RTSR Real-Time Clock (RTC) Status Register (read/write). | ||
| 868 | * | ||
| 869 | * Clocks | ||
| 870 | * frtx, Trtx Frequency, period of the real-time clock crystal | ||
| 871 | * (32.768 kHz nominal). | ||
| 872 | * frtc, Trtc Frequency, period of the real-time clock counter | ||
| 873 | * (1 Hz nominal). | ||
| 874 | */ | ||
| 875 | |||
| 876 | #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */ | ||
| 877 | #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */ | ||
| 878 | #define RTTR __REG(0x90010008) /* RTC Trim Reg. */ | ||
| 879 | #define RTSR __REG(0x90010010) /* RTC Status Reg. */ | ||
| 880 | |||
| 881 | #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ | ||
| 882 | #define RTTR_D Fld (10, 16) /* trim Delete count */ | ||
| 883 | /* frtc = (1023*(C + 1) - D)*frtx/ */ | ||
| 884 | /* (1023*(C + 1)^2) */ | ||
| 885 | /* Trtc = (1023*(C + 1)^2)*Trtx/ */ | ||
| 886 | /* (1023*(C + 1) - D) */ | ||
| 887 | |||
| 888 | #define RTSR_AL 0x00000001 /* ALarm detected */ | ||
| 889 | #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ | ||
| 890 | #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ | ||
| 891 | #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ | ||
| 892 | |||
| 893 | |||
| 894 | /* | ||
| 895 | * Power Manager (PM) control registers | ||
| 896 | * | ||
| 897 | * Registers | ||
| 898 | * PMCR Power Manager (PM) Control Register (read/write). | ||
| 899 | * PSSR Power Manager (PM) Sleep Status Register (read/write). | ||
| 900 | * PSPR Power Manager (PM) Scratch-Pad Register (read/write). | ||
| 901 | * PWER Power Manager (PM) Wake-up Enable Register | ||
| 902 | * (read/write). | ||
| 903 | * PCFR Power Manager (PM) general ConFiguration Register | ||
| 904 | * (read/write). | ||
| 905 | * PPCR Power Manager (PM) Phase-Locked Loop (PLL) | ||
| 906 | * Configuration Register (read/write). | ||
| 907 | * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) | ||
| 908 | * Sleep state Register (read/write, see GPIO pins). | ||
| 909 | * POSR Power Manager (PM) Oscillator Status Register (read). | ||
| 910 | * | ||
| 911 | * Clocks | ||
| 912 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 913 | * or 3.5795 MHz). | ||
| 914 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 915 | */ | ||
| 916 | |||
| 917 | #define PMCR __REG(0x90020000) /* PM Control Reg. */ | ||
| 918 | #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ | ||
| 919 | #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ | ||
| 920 | #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ | ||
| 921 | #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ | ||
| 922 | #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ | ||
| 923 | #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ | ||
| 924 | #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ | ||
| 925 | |||
| 926 | #define PMCR_SF 0x00000001 /* Sleep Force (set only) */ | ||
| 927 | |||
| 928 | #define PSSR_SS 0x00000001 /* Software Sleep */ | ||
| 929 | #define PSSR_BFS 0x00000002 /* Battery Fault Status */ | ||
| 930 | /* (BATT_FAULT) */ | ||
| 931 | #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ | ||
| 932 | #define PSSR_DH 0x00000008 /* DRAM control Hold */ | ||
| 933 | #define PSSR_PH 0x00000010 /* Peripheral control Hold */ | ||
| 934 | |||
| 935 | #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ | ||
| 936 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ | ||
| 937 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ | ||
| 938 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ | ||
| 939 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ | ||
| 940 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ | ||
| 941 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ | ||
| 942 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ | ||
| 943 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ | ||
| 944 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ | ||
| 945 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ | ||
| 946 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ | ||
| 947 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ | ||
| 948 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ | ||
| 949 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ | ||
| 950 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ | ||
| 951 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ | ||
| 952 | #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ | ||
| 953 | #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ | ||
| 954 | #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ | ||
| 955 | #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ | ||
| 956 | #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ | ||
| 957 | #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ | ||
| 958 | #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ | ||
| 959 | #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ | ||
| 960 | #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ | ||
| 961 | #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ | ||
| 962 | #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ | ||
| 963 | #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ | ||
| 964 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ | ||
| 965 | |||
| 966 | #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ | ||
| 967 | #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ | ||
| 968 | #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ | ||
| 969 | #define PCFR_FP 0x00000002 /* Float PCMCIA pins */ | ||
| 970 | #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ | ||
| 971 | #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ | ||
| 972 | #define PCFR_FS 0x00000004 /* Float Static memory pins */ | ||
| 973 | #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ | ||
| 974 | #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ | ||
| 975 | #define PCFR_FO 0x00000008 /* Force RTC oscillator */ | ||
| 976 | /* (32.768 kHz) enable On */ | ||
| 977 | |||
| 978 | #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ | ||
| 979 | #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ | ||
| 980 | (0x00 << FShft (PPCR_CCF)) | ||
| 981 | #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ | ||
| 982 | (0x01 << FShft (PPCR_CCF)) | ||
| 983 | #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ | ||
| 984 | (0x02 << FShft (PPCR_CCF)) | ||
| 985 | #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ | ||
| 986 | (0x03 << FShft (PPCR_CCF)) | ||
| 987 | #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ | ||
| 988 | (0x04 << FShft (PPCR_CCF)) | ||
| 989 | #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ | ||
| 990 | (0x05 << FShft (PPCR_CCF)) | ||
| 991 | #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ | ||
| 992 | (0x06 << FShft (PPCR_CCF)) | ||
| 993 | #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ | ||
| 994 | (0x07 << FShft (PPCR_CCF)) | ||
| 995 | #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ | ||
| 996 | (0x08 << FShft (PPCR_CCF)) | ||
| 997 | #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ | ||
| 998 | (0x09 << FShft (PPCR_CCF)) | ||
| 999 | #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ | ||
| 1000 | (0x0A << FShft (PPCR_CCF)) | ||
| 1001 | #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ | ||
| 1002 | (0x0B << FShft (PPCR_CCF)) | ||
| 1003 | #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ | ||
| 1004 | (0x0C << FShft (PPCR_CCF)) | ||
| 1005 | #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ | ||
| 1006 | (0x0D << FShft (PPCR_CCF)) | ||
| 1007 | #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ | ||
| 1008 | (0x0E << FShft (PPCR_CCF)) | ||
| 1009 | #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ | ||
| 1010 | (0x0F << FShft (PPCR_CCF)) | ||
| 1011 | /* 3.6864 MHz crystal (fxtl): */ | ||
| 1012 | #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ | ||
| 1013 | #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ | ||
| 1014 | #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ | ||
| 1015 | #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ | ||
| 1016 | #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ | ||
| 1017 | #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ | ||
| 1018 | #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ | ||
| 1019 | #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ | ||
| 1020 | #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ | ||
| 1021 | #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ | ||
| 1022 | #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ | ||
| 1023 | #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ | ||
| 1024 | #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ | ||
| 1025 | #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ | ||
| 1026 | #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ | ||
| 1027 | #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ | ||
| 1028 | /* 3.5795 MHz crystal (fxtl): */ | ||
| 1029 | #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ | ||
| 1030 | #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ | ||
| 1031 | #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ | ||
| 1032 | #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ | ||
| 1033 | #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ | ||
| 1034 | #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ | ||
| 1035 | #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ | ||
| 1036 | #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ | ||
| 1037 | #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ | ||
| 1038 | #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ | ||
| 1039 | #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ | ||
| 1040 | #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ | ||
| 1041 | #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ | ||
| 1042 | #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ | ||
| 1043 | #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ | ||
| 1044 | #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ | ||
| 1045 | |||
| 1046 | #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ | ||
| 1047 | |||
| 1048 | |||
| 1049 | /* | ||
| 1050 | * Reset Controller (RC) control registers | ||
| 1051 | * | ||
| 1052 | * Registers | ||
| 1053 | * RSRR Reset Controller (RC) Software Reset Register | ||
| 1054 | * (read/write). | ||
| 1055 | * RCSR Reset Controller (RC) Status Register (read/write). | ||
| 1056 | */ | ||
| 1057 | |||
| 1058 | #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ | ||
| 1059 | #define RCSR __REG(0x90030004) /* RC Status Reg. */ | ||
| 1060 | |||
| 1061 | #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ | ||
| 1062 | |||
| 1063 | #define RCSR_HWR 0x00000001 /* HardWare Reset */ | ||
| 1064 | #define RCSR_SWR 0x00000002 /* SoftWare Reset */ | ||
| 1065 | #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ | ||
| 1066 | #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ | ||
| 1067 | |||
| 1068 | |||
| 1069 | /* | ||
| 1070 | * Test unit control registers | ||
| 1071 | * | ||
| 1072 | * Registers | ||
| 1073 | * TUCR Test Unit Control Register (read/write). | ||
| 1074 | */ | ||
| 1075 | |||
| 1076 | #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ | ||
| 1077 | |||
| 1078 | #define TUCR_TIC 0x00000040 /* TIC mode */ | ||
| 1079 | #define TUCR_TTST 0x00000080 /* Trim TeST mode */ | ||
| 1080 | #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ | ||
| 1081 | /* Check */ | ||
| 1082 | #define TUCR_PMD 0x00000200 /* Power Management Disable */ | ||
| 1083 | #define TUCR_MR 0x00000400 /* Memory Request mode */ | ||
| 1084 | #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ | ||
| 1085 | #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ | ||
| 1086 | /* grant (MBGNT) on GPIO [22:21] */ | ||
| 1087 | #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ | ||
| 1088 | #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ | ||
| 1089 | #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ | ||
| 1090 | #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ | ||
| 1091 | #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ | ||
| 1092 | #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ | ||
| 1093 | #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ | ||
| 1094 | (0 << FShft (TUCR_TSEL)) | ||
| 1095 | #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ | ||
| 1096 | (1 << FShft (TUCR_TSEL)) | ||
| 1097 | #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ | ||
| 1098 | (2 << FShft (TUCR_TSEL)) | ||
| 1099 | #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ | ||
| 1100 | (3 << FShft (TUCR_TSEL)) | ||
| 1101 | #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ | ||
| 1102 | /* Clocks on GPIO [26:27] */ \ | ||
| 1103 | (4 << FShft (TUCR_TSEL)) | ||
| 1104 | #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ | ||
| 1105 | /* (Alternative) */ \ | ||
| 1106 | (5 << FShft (TUCR_TSEL)) | ||
| 1107 | #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ | ||
| 1108 | (6 << FShft (TUCR_TSEL)) | ||
| 1109 | #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ | ||
| 1110 | (7 << FShft (TUCR_TSEL)) | ||
| 1111 | |||
| 1112 | |||
| 1113 | /* | ||
| 1114 | * General-Purpose Input/Output (GPIO) control registers | ||
| 1115 | * | ||
| 1116 | * Registers | ||
| 1117 | * GPLR General-Purpose Input/Output (GPIO) Pin Level | ||
| 1118 | * Register (read). | ||
| 1119 | * GPDR General-Purpose Input/Output (GPIO) Pin Direction | ||
| 1120 | * Register (read/write). | ||
| 1121 | * GPSR General-Purpose Input/Output (GPIO) Pin output Set | ||
| 1122 | * Register (write). | ||
| 1123 | * GPCR General-Purpose Input/Output (GPIO) Pin output Clear | ||
| 1124 | * Register (write). | ||
| 1125 | * GRER General-Purpose Input/Output (GPIO) Rising-Edge | ||
| 1126 | * detect Register (read/write). | ||
| 1127 | * GFER General-Purpose Input/Output (GPIO) Falling-Edge | ||
| 1128 | * detect Register (read/write). | ||
| 1129 | * GEDR General-Purpose Input/Output (GPIO) Edge Detect | ||
| 1130 | * status Register (read/write). | ||
| 1131 | * GAFR General-Purpose Input/Output (GPIO) Alternate | ||
| 1132 | * Function Register (read/write). | ||
| 1133 | * | ||
| 1134 | * Clock | ||
| 1135 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1136 | */ | ||
| 1137 | |||
| 1138 | #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ | ||
| 1139 | #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ | ||
| 1140 | #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ | ||
| 1141 | #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ | ||
| 1142 | #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ | ||
| 1143 | #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ | ||
| 1144 | #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ | ||
| 1145 | #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ | ||
| 1146 | |||
| 1147 | #define GPIO_MIN (0) | ||
| 1148 | #define GPIO_MAX (27) | ||
| 1149 | |||
| 1150 | #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ | ||
| 1151 | (0x00000001 << (Nb)) | ||
| 1152 | #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ | ||
| 1153 | #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ | ||
| 1154 | #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ | ||
| 1155 | #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ | ||
| 1156 | #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ | ||
| 1157 | #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ | ||
| 1158 | #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ | ||
| 1159 | #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ | ||
| 1160 | #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ | ||
| 1161 | #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ | ||
| 1162 | #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ | ||
| 1163 | #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ | ||
| 1164 | #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ | ||
| 1165 | #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ | ||
| 1166 | #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ | ||
| 1167 | #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ | ||
| 1168 | #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ | ||
| 1169 | #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ | ||
| 1170 | #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ | ||
| 1171 | #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ | ||
| 1172 | #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ | ||
| 1173 | #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ | ||
| 1174 | #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ | ||
| 1175 | #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ | ||
| 1176 | #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ | ||
| 1177 | #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ | ||
| 1178 | #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ | ||
| 1179 | #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ | ||
| 1180 | |||
| 1181 | #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ | ||
| 1182 | GPIO_GPIO ((Nb) - 6) | ||
| 1183 | #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ | ||
| 1184 | #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ | ||
| 1185 | #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ | ||
| 1186 | #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ | ||
| 1187 | #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ | ||
| 1188 | #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ | ||
| 1189 | #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ | ||
| 1190 | #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ | ||
| 1191 | /* ser. port 4: */ | ||
| 1192 | #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ | ||
| 1193 | #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ | ||
| 1194 | #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ | ||
| 1195 | #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ | ||
| 1196 | /* ser. port 1: */ | ||
| 1197 | #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ | ||
| 1198 | #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ | ||
| 1199 | #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ | ||
| 1200 | #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ | ||
| 1201 | #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ | ||
| 1202 | /* ser. port 4: */ | ||
| 1203 | #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ | ||
| 1204 | /* ser. port 3: */ | ||
| 1205 | #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ | ||
| 1206 | /* ser. port 4: */ | ||
| 1207 | #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ | ||
| 1208 | /* test controller: */ | ||
| 1209 | #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ | ||
| 1210 | #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ | ||
| 1211 | #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ | ||
| 1212 | #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ | ||
| 1213 | #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ | ||
| 1214 | #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ | ||
| 1215 | #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ | ||
| 1216 | #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ | ||
| 1217 | |||
| 1218 | #define GPDR_In 0 /* Input */ | ||
| 1219 | #define GPDR_Out 1 /* Output */ | ||
| 1220 | |||
| 1221 | |||
| 1222 | /* | ||
| 1223 | * Interrupt Controller (IC) control registers | ||
| 1224 | * | ||
| 1225 | * Registers | ||
| 1226 | * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) | ||
| 1227 | * Pending register (read). | ||
| 1228 | * ICMR Interrupt Controller (IC) Mask Register (read/write). | ||
| 1229 | * ICLR Interrupt Controller (IC) Level Register (read/write). | ||
| 1230 | * ICCR Interrupt Controller (IC) Control Register | ||
| 1231 | * (read/write). | ||
| 1232 | * [The ICCR register is only implemented in versions 2.0 | ||
| 1233 | * (rev. = 8) and higher of the StrongARM SA-1100.] | ||
| 1234 | * ICFP Interrupt Controller (IC) Fast Interrupt reQuest | ||
| 1235 | * (FIQ) Pending register (read). | ||
| 1236 | * ICPR Interrupt Controller (IC) Pending Register (read). | ||
| 1237 | * [The ICPR register is active low (inverted) in | ||
| 1238 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1239 | * StrongARM SA-1100, it is active high (non-inverted) in | ||
| 1240 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1241 | */ | ||
| 1242 | |||
| 1243 | #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ | ||
| 1244 | #define ICMR __REG(0x90050004) /* IC Mask Reg. */ | ||
| 1245 | #define ICLR __REG(0x90050008) /* IC Level Reg. */ | ||
| 1246 | #define ICCR __REG(0x9005000C) /* IC Control Reg. */ | ||
| 1247 | #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ | ||
| 1248 | #define ICPR __REG(0x90050020) /* IC Pending Reg. */ | ||
| 1249 | |||
| 1250 | #define IC_GPIO(Nb) /* GPIO [0..10] */ \ | ||
| 1251 | (0x00000001 << (Nb)) | ||
| 1252 | #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ | ||
| 1253 | #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ | ||
| 1254 | #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ | ||
| 1255 | #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ | ||
| 1256 | #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ | ||
| 1257 | #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ | ||
| 1258 | #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ | ||
| 1259 | #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ | ||
| 1260 | #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ | ||
| 1261 | #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ | ||
| 1262 | #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ | ||
| 1263 | #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ | ||
| 1264 | #define IC_LCD 0x00001000 /* LCD controller */ | ||
| 1265 | #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ | ||
| 1266 | #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ | ||
| 1267 | #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ | ||
| 1268 | #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ | ||
| 1269 | #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ | ||
| 1270 | #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ | ||
| 1271 | #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ | ||
| 1272 | #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ | ||
| 1273 | (0x00100000 << (Nb)) | ||
| 1274 | #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ | ||
| 1275 | #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ | ||
| 1276 | #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ | ||
| 1277 | #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ | ||
| 1278 | #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ | ||
| 1279 | #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ | ||
| 1280 | #define IC_OST(Nb) /* OS Timer match [0..3] */ \ | ||
| 1281 | (0x04000000 << (Nb)) | ||
| 1282 | #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ | ||
| 1283 | #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ | ||
| 1284 | #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ | ||
| 1285 | #define IC_OST3 IC_OST (3) /* OS Timer match 3 */ | ||
| 1286 | #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ | ||
| 1287 | #define IC_RTCAlrm 0x80000000 /* RTC Alarm */ | ||
| 1288 | |||
| 1289 | #define ICLR_IRQ 0 /* Interrupt ReQuest */ | ||
| 1290 | #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ | ||
| 1291 | |||
| 1292 | #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ | ||
| 1293 | /* Mask */ | ||
| 1294 | #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ | ||
| 1295 | /* (ICMR ignored) */ | ||
| 1296 | #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ | ||
| 1297 | /* enable (ICMR used) */ | ||
| 1298 | |||
| 1299 | |||
| 1300 | /* | ||
| 1301 | * Peripheral Pin Controller (PPC) control registers | ||
| 1302 | * | ||
| 1303 | * Registers | ||
| 1304 | * PPDR Peripheral Pin Controller (PPC) Pin Direction | ||
| 1305 | * Register (read/write). | ||
| 1306 | * PPSR Peripheral Pin Controller (PPC) Pin State Register | ||
| 1307 | * (read/write). | ||
| 1308 | * PPAR Peripheral Pin Controller (PPC) Pin Assignment | ||
| 1309 | * Register (read/write). | ||
| 1310 | * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin | ||
| 1311 | * Direction Register (read/write). | ||
| 1312 | * PPFR Peripheral Pin Controller (PPC) Pin Flag Register | ||
| 1313 | * (read). | ||
| 1314 | */ | ||
| 1315 | |||
| 1316 | #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ | ||
| 1317 | #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ | ||
| 1318 | #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ | ||
| 1319 | #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ | ||
| 1320 | #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ | ||
| 1321 | |||
| 1322 | #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ | ||
| 1323 | (0x00000001 << (Nb)) | ||
| 1324 | #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ | ||
| 1325 | #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ | ||
| 1326 | #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ | ||
| 1327 | #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ | ||
| 1328 | #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ | ||
| 1329 | #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ | ||
| 1330 | #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ | ||
| 1331 | #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ | ||
| 1332 | #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ | ||
| 1333 | #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ | ||
| 1334 | #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ | ||
| 1335 | #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ | ||
| 1336 | /* ser. port 1: */ | ||
| 1337 | #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ | ||
| 1338 | #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ | ||
| 1339 | /* ser. port 2: */ | ||
| 1340 | #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ | ||
| 1341 | #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ | ||
| 1342 | /* ser. port 3: */ | ||
| 1343 | #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ | ||
| 1344 | #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ | ||
| 1345 | /* ser. port 4: */ | ||
| 1346 | #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ | ||
| 1347 | #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ | ||
| 1348 | #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ | ||
| 1349 | #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ | ||
| 1350 | |||
| 1351 | #define PPDR_In 0 /* Input */ | ||
| 1352 | #define PPDR_Out 1 /* Output */ | ||
| 1353 | |||
| 1354 | /* ser. port 1: */ | ||
| 1355 | #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ | ||
| 1356 | #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ | ||
| 1357 | #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ | ||
| 1358 | /* ser. port 4: */ | ||
| 1359 | #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ | ||
| 1360 | #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ | ||
| 1361 | /* & SFRM_C */ | ||
| 1362 | #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ | ||
| 1363 | |||
| 1364 | #define PSDR_OutL 0 /* Output Low in sleep mode */ | ||
| 1365 | #define PSDR_Flt 1 /* Floating (input) in sleep mode */ | ||
| 1366 | |||
| 1367 | #define PPFR_LCD 0x00000001 /* LCD controller */ | ||
| 1368 | #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ | ||
| 1369 | #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ | ||
| 1370 | #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ | ||
| 1371 | #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ | ||
| 1372 | #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ | ||
| 1373 | #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ | ||
| 1374 | #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ | ||
| 1375 | #define PPFR_PerEn 0 /* Peripheral Enabled */ | ||
| 1376 | #define PPFR_PPCEn 1 /* PPC Enabled */ | ||
| 1377 | |||
| 1378 | |||
| 1379 | /* | ||
| 1380 | * Dynamic Random-Access Memory (DRAM) control registers | ||
| 1381 | * | ||
| 1382 | * Registers | ||
| 1383 | * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1384 | * CoNFiGuration register (read/write). | ||
| 1385 | * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1386 | * Column Address Strobe (CAS) shift register 0 | ||
| 1387 | * (read/write). | ||
| 1388 | * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1389 | * Column Address Strobe (CAS) shift register 1 | ||
| 1390 | * (read/write). | ||
| 1391 | * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1392 | * Column Address Strobe (CAS) shift register 2 | ||
| 1393 | * (read/write). | ||
| 1394 | * | ||
| 1395 | * Clocks | ||
| 1396 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1397 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1398 | * fcas, Tcas Frequency, period of the DRAM CAS shift registers. | ||
| 1399 | */ | ||
| 1400 | |||
| 1401 | #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ | ||
| 1402 | #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ | ||
| 1403 | #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ | ||
| 1404 | #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ | ||
| 1405 | |||
| 1406 | /* SA1100 MDCNFG values */ | ||
| 1407 | #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ | ||
| 1408 | (0x00000001 << (Nb)) | ||
| 1409 | #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ | ||
| 1410 | #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ | ||
| 1411 | #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ | ||
| 1412 | #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ | ||
| 1413 | #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ | ||
| 1414 | #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ | ||
| 1415 | (((Add) - 9) << FShft (MDCNFG_DRAC)) | ||
| 1416 | #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ | ||
| 1417 | /* (fcas = fcpu/2) */ | ||
| 1418 | #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ | ||
| 1419 | #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ | ||
| 1420 | (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) | ||
| 1421 | #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ | ||
| 1422 | (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) | ||
| 1423 | #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ | ||
| 1424 | #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ | ||
| 1425 | (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) | ||
| 1426 | #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ | ||
| 1427 | (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) | ||
| 1428 | #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ | ||
| 1429 | #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ | ||
| 1430 | ((Tcpu) << FShft (MDCNFG_TDL)) | ||
| 1431 | #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ | ||
| 1432 | /* [Tmem] */ | ||
| 1433 | #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ | ||
| 1434 | /* [0..262136 Tcpu] */ \ | ||
| 1435 | ((Tcpu)/8 << FShft (MDCNFG_DRI)) | ||
| 1436 | |||
| 1437 | /* SA1110 MDCNFG values */ | ||
| 1438 | #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ | ||
| 1439 | #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ | ||
| 1440 | #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ | ||
| 1441 | #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ | ||
| 1442 | #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ | ||
| 1443 | /* bank 0/1 */ | ||
| 1444 | #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ | ||
| 1445 | #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ | ||
| 1446 | #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ | ||
| 1447 | /* deassertion 0/1 */ | ||
| 1448 | #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ | ||
| 1449 | #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ | ||
| 1450 | #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ | ||
| 1451 | #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ | ||
| 1452 | #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ | ||
| 1453 | #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ | ||
| 1454 | /* bank 0/1 */ | ||
| 1455 | #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ | ||
| 1456 | #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ | ||
| 1457 | #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ | ||
| 1458 | /* deassertion 0/1 */ | ||
| 1459 | #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ | ||
| 1460 | |||
| 1461 | |||
| 1462 | /* | ||
| 1463 | * Static memory control registers | ||
| 1464 | * | ||
| 1465 | * Registers | ||
| 1466 | * MSC0 Memory system: Static memory Control register 0 | ||
| 1467 | * (read/write). | ||
| 1468 | * MSC1 Memory system: Static memory Control register 1 | ||
| 1469 | * (read/write). | ||
| 1470 | * | ||
| 1471 | * Clocks | ||
| 1472 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1473 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1474 | */ | ||
| 1475 | |||
| 1476 | #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ | ||
| 1477 | #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ | ||
| 1478 | #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ | ||
| 1479 | |||
| 1480 | #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ | ||
| 1481 | Fld (16, ((Nb) Modulo 2)*16) | ||
| 1482 | #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ | ||
| 1483 | #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ | ||
| 1484 | #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ | ||
| 1485 | #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ | ||
| 1486 | |||
| 1487 | #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ | ||
| 1488 | #define MSC_NonBrst /* Non-Burst static memory */ \ | ||
| 1489 | (0 << FShft (MSC_RT)) | ||
| 1490 | #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ | ||
| 1491 | (1 << FShft (MSC_RT)) | ||
| 1492 | #define MSC_Brst4 /* Burst-of-4 static memory */ \ | ||
| 1493 | (2 << FShft (MSC_RT)) | ||
| 1494 | #define MSC_Brst8 /* Burst-of-8 static memory */ \ | ||
| 1495 | (3 << FShft (MSC_RT)) | ||
| 1496 | #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ | ||
| 1497 | #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ | ||
| 1498 | #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ | ||
| 1499 | #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ | ||
| 1500 | /* First access - 1(.5) [Tmem] */ | ||
| 1501 | #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ | ||
| 1502 | /* static memory) [3..65 Tcpu] */ \ | ||
| 1503 | ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) | ||
| 1504 | #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ | ||
| 1505 | ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) | ||
| 1506 | #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ | ||
| 1507 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1508 | ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) | ||
| 1509 | #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ | ||
| 1510 | ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) | ||
| 1511 | #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ | ||
| 1512 | /* Next access - 1 [Tmem] */ | ||
| 1513 | #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ | ||
| 1514 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1515 | ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) | ||
| 1516 | #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ | ||
| 1517 | ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) | ||
| 1518 | #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ | ||
| 1519 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1520 | ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) | ||
| 1521 | #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ | ||
| 1522 | ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) | ||
| 1523 | #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ | ||
| 1524 | /* time/2 [Tmem] */ | ||
| 1525 | #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ | ||
| 1526 | (((Tcpu)/4) << FShft (MSC_RRR)) | ||
| 1527 | #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ | ||
| 1528 | ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) | ||
| 1529 | |||
| 1530 | |||
| 1531 | /* | ||
| 1532 | * Personal Computer Memory Card International Association (PCMCIA) control | ||
| 1533 | * register | ||
| 1534 | * | ||
| 1535 | * Register | ||
| 1536 | * MECR Memory system: Expansion memory bus (PCMCIA) | ||
| 1537 | * Configuration Register (read/write). | ||
| 1538 | * | ||
| 1539 | * Clocks | ||
| 1540 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1541 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1542 | * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). | ||
| 1543 | */ | ||
| 1544 | |||
| 1545 | /* Memory system: */ | ||
| 1546 | #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ | ||
| 1547 | |||
| 1548 | #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 1549 | Fld (15, (Nb)*16) | ||
| 1550 | #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ | ||
| 1551 | #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ | ||
| 1552 | |||
| 1553 | #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ | ||
| 1554 | #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ | ||
| 1555 | ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) | ||
| 1556 | #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ | ||
| 1557 | ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) | ||
| 1558 | #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ | ||
| 1559 | /* [Tmem] */ | ||
| 1560 | #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ | ||
| 1561 | ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) | ||
| 1562 | #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ | ||
| 1563 | ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) | ||
| 1564 | #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ | ||
| 1565 | #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ | ||
| 1566 | ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) | ||
| 1567 | #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ | ||
| 1568 | ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) | ||
| 1569 | |||
| 1570 | /* | ||
| 1571 | * On SA1110 only | ||
| 1572 | */ | ||
| 1573 | |||
| 1574 | #define MDREFR __REG(0xA000001C) | ||
| 1575 | |||
| 1576 | #define MDREFR_TRASR Fld (4, 0) | ||
| 1577 | #define MDREFR_DRI Fld (12, 4) | ||
| 1578 | #define MDREFR_E0PIN (1 << 16) | ||
| 1579 | #define MDREFR_K0RUN (1 << 17) | ||
| 1580 | #define MDREFR_K0DB2 (1 << 18) | ||
| 1581 | #define MDREFR_E1PIN (1 << 20) | ||
| 1582 | #define MDREFR_K1RUN (1 << 21) | ||
| 1583 | #define MDREFR_K1DB2 (1 << 22) | ||
| 1584 | #define MDREFR_K2RUN (1 << 25) | ||
| 1585 | #define MDREFR_K2DB2 (1 << 26) | ||
| 1586 | #define MDREFR_EAPD (1 << 28) | ||
| 1587 | #define MDREFR_KAPD (1 << 29) | ||
| 1588 | #define MDREFR_SLFRSH (1 << 31) | ||
| 1589 | |||
| 1590 | |||
| 1591 | /* | ||
| 1592 | * Direct Memory Access (DMA) control registers | ||
| 1593 | * | ||
| 1594 | * Registers | ||
| 1595 | * DDAR0 Direct Memory Access (DMA) Device Address Register | ||
| 1596 | * channel 0 (read/write). | ||
| 1597 | * DCSR0 Direct Memory Access (DMA) Control and Status | ||
| 1598 | * Register channel 0 (read/write). | ||
| 1599 | * DBSA0 Direct Memory Access (DMA) Buffer Start address | ||
| 1600 | * register A channel 0 (read/write). | ||
| 1601 | * DBTA0 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1602 | * register A channel 0 (read/write). | ||
| 1603 | * DBSB0 Direct Memory Access (DMA) Buffer Start address | ||
| 1604 | * register B channel 0 (read/write). | ||
| 1605 | * DBTB0 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1606 | * register B channel 0 (read/write). | ||
| 1607 | * | ||
| 1608 | * DDAR1 Direct Memory Access (DMA) Device Address Register | ||
| 1609 | * channel 1 (read/write). | ||
| 1610 | * DCSR1 Direct Memory Access (DMA) Control and Status | ||
| 1611 | * Register channel 1 (read/write). | ||
| 1612 | * DBSA1 Direct Memory Access (DMA) Buffer Start address | ||
| 1613 | * register A channel 1 (read/write). | ||
| 1614 | * DBTA1 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1615 | * register A channel 1 (read/write). | ||
| 1616 | * DBSB1 Direct Memory Access (DMA) Buffer Start address | ||
| 1617 | * register B channel 1 (read/write). | ||
| 1618 | * DBTB1 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1619 | * register B channel 1 (read/write). | ||
| 1620 | * | ||
| 1621 | * DDAR2 Direct Memory Access (DMA) Device Address Register | ||
| 1622 | * channel 2 (read/write). | ||
| 1623 | * DCSR2 Direct Memory Access (DMA) Control and Status | ||
| 1624 | * Register channel 2 (read/write). | ||
| 1625 | * DBSA2 Direct Memory Access (DMA) Buffer Start address | ||
| 1626 | * register A channel 2 (read/write). | ||
| 1627 | * DBTA2 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1628 | * register A channel 2 (read/write). | ||
| 1629 | * DBSB2 Direct Memory Access (DMA) Buffer Start address | ||
| 1630 | * register B channel 2 (read/write). | ||
| 1631 | * DBTB2 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1632 | * register B channel 2 (read/write). | ||
| 1633 | * | ||
| 1634 | * DDAR3 Direct Memory Access (DMA) Device Address Register | ||
| 1635 | * channel 3 (read/write). | ||
| 1636 | * DCSR3 Direct Memory Access (DMA) Control and Status | ||
| 1637 | * Register channel 3 (read/write). | ||
| 1638 | * DBSA3 Direct Memory Access (DMA) Buffer Start address | ||
| 1639 | * register A channel 3 (read/write). | ||
| 1640 | * DBTA3 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1641 | * register A channel 3 (read/write). | ||
| 1642 | * DBSB3 Direct Memory Access (DMA) Buffer Start address | ||
| 1643 | * register B channel 3 (read/write). | ||
| 1644 | * DBTB3 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1645 | * register B channel 3 (read/write). | ||
| 1646 | * | ||
| 1647 | * DDAR4 Direct Memory Access (DMA) Device Address Register | ||
| 1648 | * channel 4 (read/write). | ||
| 1649 | * DCSR4 Direct Memory Access (DMA) Control and Status | ||
| 1650 | * Register channel 4 (read/write). | ||
| 1651 | * DBSA4 Direct Memory Access (DMA) Buffer Start address | ||
| 1652 | * register A channel 4 (read/write). | ||
| 1653 | * DBTA4 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1654 | * register A channel 4 (read/write). | ||
| 1655 | * DBSB4 Direct Memory Access (DMA) Buffer Start address | ||
| 1656 | * register B channel 4 (read/write). | ||
| 1657 | * DBTB4 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1658 | * register B channel 4 (read/write). | ||
| 1659 | * | ||
| 1660 | * DDAR5 Direct Memory Access (DMA) Device Address Register | ||
| 1661 | * channel 5 (read/write). | ||
| 1662 | * DCSR5 Direct Memory Access (DMA) Control and Status | ||
| 1663 | * Register channel 5 (read/write). | ||
| 1664 | * DBSA5 Direct Memory Access (DMA) Buffer Start address | ||
| 1665 | * register A channel 5 (read/write). | ||
| 1666 | * DBTA5 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1667 | * register A channel 5 (read/write). | ||
| 1668 | * DBSB5 Direct Memory Access (DMA) Buffer Start address | ||
| 1669 | * register B channel 5 (read/write). | ||
| 1670 | * DBTB5 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1671 | * register B channel 5 (read/write). | ||
| 1672 | */ | ||
| 1673 | |||
| 1674 | #define DMASp 0x00000020 /* DMA control reg. Space [byte] */ | ||
| 1675 | |||
| 1676 | #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ | ||
| 1677 | #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */ | ||
| 1678 | #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */ | ||
| 1679 | #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */ | ||
| 1680 | #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */ | ||
| 1681 | #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */ | ||
| 1682 | #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */ | ||
| 1683 | #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */ | ||
| 1684 | |||
| 1685 | #define DDAR_RW 0x00000001 /* device data Read/Write */ | ||
| 1686 | #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ | ||
| 1687 | /* (memory -> device) */ | ||
| 1688 | #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ | ||
| 1689 | /* (device -> memory) */ | ||
| 1690 | #define DDAR_E 0x00000002 /* big/little Endian device */ | ||
| 1691 | #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ | ||
| 1692 | #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ | ||
| 1693 | #define DDAR_BS 0x00000004 /* device Burst Size */ | ||
| 1694 | #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ | ||
| 1695 | #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ | ||
| 1696 | #define DDAR_DW 0x00000008 /* device Data Width */ | ||
| 1697 | #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ | ||
| 1698 | #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ | ||
| 1699 | #define DDAR_DS Fld (4, 4) /* Device Select */ | ||
| 1700 | #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ | ||
| 1701 | (0x0 << FShft (DDAR_DS)) | ||
| 1702 | #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ | ||
| 1703 | (0x1 << FShft (DDAR_DS)) | ||
| 1704 | #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ | ||
| 1705 | (0x2 << FShft (DDAR_DS)) | ||
| 1706 | #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ | ||
| 1707 | (0x3 << FShft (DDAR_DS)) | ||
| 1708 | #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ | ||
| 1709 | (0x4 << FShft (DDAR_DS)) | ||
| 1710 | #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ | ||
| 1711 | (0x5 << FShft (DDAR_DS)) | ||
| 1712 | #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ | ||
| 1713 | (0x6 << FShft (DDAR_DS)) | ||
| 1714 | #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ | ||
| 1715 | (0x7 << FShft (DDAR_DS)) | ||
| 1716 | #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ | ||
| 1717 | (0x8 << FShft (DDAR_DS)) | ||
| 1718 | #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ | ||
| 1719 | (0x9 << FShft (DDAR_DS)) | ||
| 1720 | #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ | ||
| 1721 | /* (audio) */ \ | ||
| 1722 | (0xA << FShft (DDAR_DS)) | ||
| 1723 | #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ | ||
| 1724 | /* (audio) */ \ | ||
| 1725 | (0xB << FShft (DDAR_DS)) | ||
| 1726 | #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ | ||
| 1727 | /* (telecom) */ \ | ||
| 1728 | (0xC << FShft (DDAR_DS)) | ||
| 1729 | #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ | ||
| 1730 | /* (telecom) */ \ | ||
| 1731 | (0xD << FShft (DDAR_DS)) | ||
| 1732 | #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ | ||
| 1733 | (0xE << FShft (DDAR_DS)) | ||
| 1734 | #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ | ||
| 1735 | (0xF << FShft (DDAR_DS)) | ||
| 1736 | #define DDAR_DA Fld (24, 8) /* Device Address */ | ||
| 1737 | #define DDAR_DevAdd(Add) /* Device Address */ \ | ||
| 1738 | (((Add) & 0xF0000000) | \ | ||
| 1739 | (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) | ||
| 1740 | #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ | ||
| 1741 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1742 | DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
| 1743 | #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ | ||
| 1744 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1745 | DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
| 1746 | #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ | ||
| 1747 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1748 | DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
| 1749 | #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ | ||
| 1750 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1751 | DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
| 1752 | #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ | ||
| 1753 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1754 | DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
| 1755 | #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ | ||
| 1756 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1757 | DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
| 1758 | #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ | ||
| 1759 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1760 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
| 1761 | #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ | ||
| 1762 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1763 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
| 1764 | #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ | ||
| 1765 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1766 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
| 1767 | #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ | ||
| 1768 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1769 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
| 1770 | #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ | ||
| 1771 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1772 | DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
| 1773 | #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ | ||
| 1774 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1775 | DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
| 1776 | #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ | ||
| 1777 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1778 | DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
| 1779 | #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ | ||
| 1780 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1781 | DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
| 1782 | #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ | ||
| 1783 | /* (telecom) */ \ | ||
| 1784 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1785 | DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
| 1786 | #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ | ||
| 1787 | /* (telecom) */ \ | ||
| 1788 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1789 | DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
| 1790 | #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ | ||
| 1791 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1792 | DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
| 1793 | #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ | ||
| 1794 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1795 | DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
| 1796 | |||
| 1797 | #define DCSR_RUN 0x00000001 /* DMA RUNing */ | ||
| 1798 | #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ | ||
| 1799 | #define DCSR_ERROR 0x00000004 /* DMA ERROR */ | ||
| 1800 | #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ | ||
| 1801 | #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ | ||
| 1802 | #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ | ||
| 1803 | #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ | ||
| 1804 | #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ | ||
| 1805 | #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ | ||
| 1806 | #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ | ||
| 1807 | |||
| 1808 | #define DBT_TC Fld (13, 0) /* Transfer Count */ | ||
| 1809 | #define DBTA_TCA DBT_TC /* Transfer Count buffer A */ | ||
| 1810 | #define DBTB_TCB DBT_TC /* Transfer Count buffer B */ | ||
| 1811 | |||
| 1812 | |||
| 1813 | /* | ||
| 1814 | * Liquid Crystal Display (LCD) control registers | ||
| 1815 | * | ||
| 1816 | * Registers | ||
| 1817 | * LCCR0 Liquid Crystal Display (LCD) Control Register 0 | ||
| 1818 | * (read/write). | ||
| 1819 | * [Bits LDM, BAM, and ERM are only implemented in | ||
| 1820 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 1821 | * SA-1100.] | ||
| 1822 | * LCSR Liquid Crystal Display (LCD) Status Register | ||
| 1823 | * (read/write). | ||
| 1824 | * [Bit LDD can be only read in versions 1.0 (rev. = 1) | ||
| 1825 | * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be | ||
| 1826 | * read and written (cleared) in versions 2.0 (rev. = 8) | ||
| 1827 | * and higher.] | ||
| 1828 | * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1829 | * (DMA) Base Address Register channel 1 (read/write). | ||
| 1830 | * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1831 | * (DMA) Current Address Register channel 1 (read). | ||
| 1832 | * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1833 | * (DMA) Base Address Register channel 2 (read/write). | ||
| 1834 | * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1835 | * (DMA) Current Address Register channel 2 (read). | ||
| 1836 | * LCCR1 Liquid Crystal Display (LCD) Control Register 1 | ||
| 1837 | * (read/write). | ||
| 1838 | * [The LCCR1 register can be only written in | ||
| 1839 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1840 | * StrongARM SA-1100, it can be written and read in | ||
| 1841 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1842 | * LCCR2 Liquid Crystal Display (LCD) Control Register 2 | ||
| 1843 | * (read/write). | ||
| 1844 | * [The LCCR1 register can be only written in | ||
| 1845 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1846 | * StrongARM SA-1100, it can be written and read in | ||
| 1847 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1848 | * LCCR3 Liquid Crystal Display (LCD) Control Register 3 | ||
| 1849 | * (read/write). | ||
| 1850 | * [The LCCR1 register can be only written in | ||
| 1851 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1852 | * StrongARM SA-1100, it can be written and read in | ||
| 1853 | * versions 2.0 (rev. = 8) and higher. Bit PCP is only | ||
| 1854 | * implemented in versions 2.0 (rev. = 8) and higher of | ||
| 1855 | * the StrongARM SA-1100.] | ||
| 1856 | * | ||
| 1857 | * Clocks | ||
| 1858 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1859 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1860 | * fpix, Tpix Frequency, period of the pixel clock. | ||
| 1861 | * fln, Tln Frequency, period of the line clock. | ||
| 1862 | * fac, Tac Frequency, period of the AC bias clock. | ||
| 1863 | */ | ||
| 1864 | |||
| 1865 | #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ | ||
| 1866 | #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ | ||
| 1867 | /* [byte] */ \ | ||
| 1868 | (16*LCD_PEntrySp) | ||
| 1869 | #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ | ||
| 1870 | /* [byte] */ \ | ||
| 1871 | (256*LCD_PEntrySp) | ||
| 1872 | #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ | ||
| 1873 | /* dummy-Palette Space [byte] */ \ | ||
| 1874 | (16*LCD_PEntrySp) | ||
| 1875 | |||
| 1876 | #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ | ||
| 1877 | #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ | ||
| 1878 | #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ | ||
| 1879 | #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ | ||
| 1880 | #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ | ||
| 1881 | #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ | ||
| 1882 | (0 << FShft (LCD_PBS)) | ||
| 1883 | #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ | ||
| 1884 | (1 << FShft (LCD_PBS)) | ||
| 1885 | #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ | ||
| 1886 | (2 << FShft (LCD_PBS)) | ||
| 1887 | |||
| 1888 | #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ | ||
| 1889 | #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ | ||
| 1890 | #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ | ||
| 1891 | #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ | ||
| 1892 | #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ | ||
| 1893 | #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ | ||
| 1894 | #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ | ||
| 1895 | #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ | ||
| 1896 | #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ | ||
| 1897 | #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ | ||
| 1898 | #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ | ||
| 1899 | #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ | ||
| 1900 | #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ | ||
| 1901 | #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ | ||
| 1902 | #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ | ||
| 1903 | #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ | ||
| 1904 | /* (Alternative) */ | ||
| 1905 | |||
| 1906 | #define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */ | ||
| 1907 | #define LCSR __REG(0xB0100004) /* LCD Status Reg. */ | ||
| 1908 | #define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */ | ||
| 1909 | #define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */ | ||
| 1910 | #define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */ | ||
| 1911 | #define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */ | ||
| 1912 | #define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */ | ||
| 1913 | #define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */ | ||
| 1914 | #define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */ | ||
| 1915 | |||
| 1916 | #define LCCR0_LEN 0x00000001 /* LCD ENable */ | ||
| 1917 | #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ | ||
| 1918 | #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ | ||
| 1919 | #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ | ||
| 1920 | #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ | ||
| 1921 | /* Select */ | ||
| 1922 | #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ | ||
| 1923 | #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ | ||
| 1924 | #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ | ||
| 1925 | /* interrupt Mask (disable) */ | ||
| 1926 | #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ | ||
| 1927 | /* interrupt Mask (disable) */ | ||
| 1928 | #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ | ||
| 1929 | /* IUU, OOL, OUL, OOU, and OUU) */ | ||
| 1930 | /* interrupt Mask (disable) */ | ||
| 1931 | #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ | ||
| 1932 | #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ | ||
| 1933 | #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ | ||
| 1934 | #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ | ||
| 1935 | #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ | ||
| 1936 | #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ | ||
| 1937 | #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ | ||
| 1938 | /* display mode) */ | ||
| 1939 | #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ | ||
| 1940 | /* display */ | ||
| 1941 | #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ | ||
| 1942 | /* display */ | ||
| 1943 | #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ | ||
| 1944 | /* [Tmem] */ | ||
| 1945 | #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ | ||
| 1946 | /* [0..510 Tcpu] */ \ | ||
| 1947 | ((Tcpu)/2 << FShft (LCCR0_PDD)) | ||
| 1948 | |||
| 1949 | #define LCSR_LDD 0x00000001 /* LCD Disable Done */ | ||
| 1950 | #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ | ||
| 1951 | #define LCSR_BER 0x00000004 /* Bus ERror */ | ||
| 1952 | #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ | ||
| 1953 | #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ | ||
| 1954 | /* panel */ | ||
| 1955 | #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ | ||
| 1956 | /* panel */ | ||
| 1957 | #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ | ||
| 1958 | /* panel */ | ||
| 1959 | #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ | ||
| 1960 | /* panel */ | ||
| 1961 | #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ | ||
| 1962 | /* panel */ | ||
| 1963 | #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ | ||
| 1964 | /* panel */ | ||
| 1965 | #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ | ||
| 1966 | /* panel */ | ||
| 1967 | #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ | ||
| 1968 | /* panel */ | ||
| 1969 | |||
| 1970 | #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ | ||
| 1971 | #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ | ||
| 1972 | (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) | ||
| 1973 | #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ | ||
| 1974 | /* pulse Width - 1 [Tpix] (L_LCLK) */ | ||
| 1975 | #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ | ||
| 1976 | /* pulse Width [1..64 Tpix] */ \ | ||
| 1977 | (((Tpix) - 1) << FShft (LCCR1_HSW)) | ||
| 1978 | #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ | ||
| 1979 | /* count - 1 [Tpix] */ | ||
| 1980 | #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ | ||
| 1981 | /* [1..256 Tpix] */ \ | ||
| 1982 | (((Tpix) - 1) << FShft (LCCR1_ELW)) | ||
| 1983 | #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ | ||
| 1984 | /* Wait count - 1 [Tpix] */ | ||
| 1985 | #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ | ||
| 1986 | /* [1..256 Tpix] */ \ | ||
| 1987 | (((Tpix) - 1) << FShft (LCCR1_BLW)) | ||
| 1988 | |||
| 1989 | #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ | ||
| 1990 | #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ | ||
| 1991 | (((Line) - 1) << FShft (LCCR2_LPP)) | ||
| 1992 | #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ | ||
| 1993 | /* Width - 1 [Tln] (L_FCLK) */ | ||
| 1994 | #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ | ||
| 1995 | /* Width [1..64 Tln] */ \ | ||
| 1996 | (((Tln) - 1) << FShft (LCCR2_VSW)) | ||
| 1997 | #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ | ||
| 1998 | /* count [Tln] */ | ||
| 1999 | #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ | ||
| 2000 | /* [0..255 Tln] */ \ | ||
| 2001 | ((Tln) << FShft (LCCR2_EFW)) | ||
| 2002 | #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ | ||
| 2003 | /* Wait count [Tln] */ | ||
| 2004 | #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ | ||
| 2005 | /* [0..255 Tln] */ \ | ||
| 2006 | ((Tln) << FShft (LCCR2_BFW)) | ||
| 2007 | |||
| 2008 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ | ||
| 2009 | /* [1..255] (L_PCLK) */ | ||
| 2010 | /* fpix = fcpu/(2*(PCD + 2)) */ | ||
| 2011 | /* Tpix = 2*(PCD + 2)*Tcpu */ | ||
| 2012 | #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ | ||
| 2013 | (((Div) - 4)/2 << FShft (LCCR3_PCD)) | ||
| 2014 | /* fpix = fcpu/(2*Floor (Div/2)) */ | ||
| 2015 | /* Tpix = 2*Floor (Div/2)*Tcpu */ | ||
| 2016 | #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ | ||
| 2017 | (((Div) - 3)/2 << FShft (LCCR3_PCD)) | ||
| 2018 | /* fpix = fcpu/(2*Ceil (Div/2)) */ | ||
| 2019 | /* Tpix = 2*Ceil (Div/2)*Tcpu */ | ||
| 2020 | #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ | ||
| 2021 | /* [Tln] (L_BIAS) */ | ||
| 2022 | #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ | ||
| 2023 | (((Div) - 2)/2 << FShft (LCCR3_ACB)) | ||
| 2024 | /* fac = fln/(2*Floor (Div/2)) */ | ||
| 2025 | /* Tac = 2*Floor (Div/2)*Tln */ | ||
| 2026 | #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ | ||
| 2027 | (((Div) - 1)/2 << FShft (LCCR3_ACB)) | ||
| 2028 | /* fac = fln/(2*Ceil (Div/2)) */ | ||
| 2029 | /* Tac = 2*Ceil (Div/2)*Tln */ | ||
| 2030 | #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ | ||
| 2031 | /* Interrupt */ | ||
| 2032 | #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ | ||
| 2033 | /* Off */ \ | ||
| 2034 | (0 << FShft (LCCR3_API)) | ||
| 2035 | #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ | ||
| 2036 | /* [1..15] */ \ | ||
| 2037 | ((Trans) << FShft (LCCR3_API)) | ||
| 2038 | #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ | ||
| 2039 | /* Polarity (L_FCLK) */ | ||
| 2040 | #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ | ||
| 2041 | /* active High */ | ||
| 2042 | #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ | ||
| 2043 | /* active Low */ | ||
| 2044 | #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ | ||
| 2045 | /* pulse Polarity (L_LCLK) */ | ||
| 2046 | #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ | ||
| 2047 | /* pulse active High */ | ||
| 2048 | #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ | ||
| 2049 | /* pulse active Low */ | ||
| 2050 | #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ | ||
| 2051 | #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ | ||
| 2052 | #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ | ||
| 2053 | #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ | ||
| 2054 | /* active display mode) */ | ||
| 2055 | #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ | ||
| 2056 | #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ | ||
| 2057 | |||
| 2058 | #ifndef __ASSEMBLY__ | ||
| 2059 | extern unsigned int processor_id; | ||
| 2060 | #endif | ||
| 2061 | |||
| 2062 | #define CPU_REVISION (processor_id & 15) | ||
| 2063 | #define CPU_SA1110_A0 (0) | ||
| 2064 | #define CPU_SA1110_B0 (4) | ||
| 2065 | #define CPU_SA1110_B1 (5) | ||
| 2066 | #define CPU_SA1110_B2 (6) | ||
| 2067 | #define CPU_SA1110_B4 (8) | ||
| 2068 | |||
| 2069 | #define CPU_SA1100_ID (0x4401a110) | ||
| 2070 | #define CPU_SA1100_MASK (0xfffffff0) | ||
| 2071 | #define CPU_SA1110_ID (0x6901b110) | ||
| 2072 | #define CPU_SA1110_MASK (0xfffffff0) | ||
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1101.h b/arch/arm/mach-sa1100/include/mach/SA-1101.h new file mode 100644 index 000000000000..5d2ad7db991c --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/SA-1101.h | |||
| @@ -0,0 +1,925 @@ | |||
| 1 | /* | ||
| 2 | * SA-1101.h | ||
| 3 | * | ||
| 4 | * Copyright (c) Peter Danielsson 1999 | ||
| 5 | * | ||
| 6 | * Definition of constants related to the sa1101 | ||
| 7 | * support chip for the sa1100 | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | /* Be sure that virtual mapping is defined right */ | ||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #error You must include hardware.h not SA-1101.h | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #ifndef SA1101_BASE | ||
| 18 | #error You must define SA-1101 physical base address | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #ifndef LANGUAGE | ||
| 22 | # ifdef __ASSEMBLY__ | ||
| 23 | # define LANGUAGE Assembly | ||
| 24 | # else | ||
| 25 | # define LANGUAGE C | ||
| 26 | # endif | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* | ||
| 30 | * We have mapped the sa1101 depending on the value of SA1101_BASE. | ||
| 31 | * It then appears from 0xf4000000. | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000) | ||
| 35 | #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE) | ||
| 36 | |||
| 37 | #ifndef SA1101_p2v | ||
| 38 | #define SA1101_p2v(PhAdd) (PhAdd) | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #include <mach/bitfield.h> | ||
| 42 | |||
| 43 | #define C 0 | ||
| 44 | #define Assembly 1 | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * Memory map | ||
| 49 | */ | ||
| 50 | |||
| 51 | #define __SHMEM_CONTROL0 0x00000000 | ||
| 52 | #define __SYSTEM_CONTROL1 0x00000400 | ||
| 53 | #define __ARBITER 0x00020000 | ||
| 54 | #define __SYSTEM_CONTROL2 0x00040000 | ||
| 55 | #define __SYSTEM_CONTROL3 0x00060000 | ||
| 56 | #define __PARALLEL_PORT 0x00080000 | ||
| 57 | #define __VIDMEM_CONTROL 0x00100000 | ||
| 58 | #define __UPDATE_FIFO 0x00120000 | ||
| 59 | #define __SHMEM_CONTROL1 0x00140000 | ||
| 60 | #define __INTERRUPT_CONTROL 0x00160000 | ||
| 61 | #define __USB_CONTROL 0x00180000 | ||
| 62 | #define __TRACK_INTERFACE 0x001a0000 | ||
| 63 | #define __MOUSE_INTERFACE 0x001b0000 | ||
| 64 | #define __KEYPAD_INTERFACE 0x001c0000 | ||
| 65 | #define __PCMCIA_INTERFACE 0x001e0000 | ||
| 66 | #define __VGA_CONTROL 0x00200000 | ||
| 67 | #define __GPIO_INTERFACE 0x00300000 | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Macro that calculates real address for registers in the SA-1101 | ||
| 71 | */ | ||
| 72 | |||
| 73 | #define _SA1101( x ) ((x) + SA1101_BASE) | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Interface and shared memory controller registers | ||
| 77 | * | ||
| 78 | * Registers | ||
| 79 | * SKCR SA-1101 control register (read/write) | ||
| 80 | * SMCR Shared Memory Controller Register | ||
| 81 | * SNPR Snoop Register | ||
| 82 | */ | ||
| 83 | |||
| 84 | #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ | ||
| 85 | #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ | ||
| 86 | #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ | ||
| 87 | |||
| 88 | #if LANGUAGE == C | ||
| 89 | #define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) | ||
| 90 | #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) | ||
| 91 | #define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) | ||
| 92 | |||
| 93 | #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ | ||
| 94 | #define SKCR_BCLKEn 0x0002 /* Enables BCLK */ | ||
| 95 | #define SKCR_Sleep 0x0004 /* Sleep Mode */ | ||
| 96 | #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ | ||
| 97 | #define SKCR_VCOON 0x0010 /* VCO bias */ | ||
| 98 | #define SKCR_ScanTestEn 0x0020 /* Enables scan test */ | ||
| 99 | #define SKCR_ClockTestEn 0x0040 /* Enables clock test */ | ||
| 100 | |||
| 101 | #define SMCR_DCAC Fld(2,0) /* Number of column address bits */ | ||
| 102 | #define SMCR_DRAC Fld(2,2) /* Number of row address bits */ | ||
| 103 | #define SMCR_ArbiterBias 0x0008 /* favor video or USB */ | ||
| 104 | #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ | ||
| 105 | |||
| 106 | #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ | ||
| 107 | (( (x) - 8 ) << FShft (SMCR_DCAC)) | ||
| 108 | #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ | ||
| 109 | (( (x) - 9 ) << FShft (SMCR_DRAC)) | ||
| 110 | |||
| 111 | #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ | ||
| 112 | #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ | ||
| 113 | #define SNPR_WholeBank (1 << 23) /* Whole bank bit */ | ||
| 114 | #define SNPR_BankSelect Fld(2,27) /* Bank select */ | ||
| 115 | #define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ | ||
| 116 | |||
| 117 | #define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ | ||
| 118 | ( (x) << FShft (SNPR_VFBsize)) | ||
| 119 | #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ | ||
| 120 | (( (x) + 1 ) << FShft (SNPR_BankSelect )) | ||
| 121 | |||
| 122 | #endif /* LANGUAGE == C */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Video Memory Controller | ||
| 126 | * | ||
| 127 | * Registers | ||
| 128 | * VMCCR Configuration register | ||
| 129 | * VMCAR VMC address register | ||
| 130 | * VMCDR VMC data register | ||
| 131 | * | ||
| 132 | */ | ||
| 133 | |||
| 134 | #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ | ||
| 135 | #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ | ||
| 136 | #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ | ||
| 137 | |||
| 138 | #if LANGUAGE == C | ||
| 139 | #define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) | ||
| 140 | #define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) | ||
| 141 | #define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) | ||
| 142 | |||
| 143 | #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ | ||
| 144 | #define VMCCR_Config 0x0001 /* DRAM size */ | ||
| 145 | #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ | ||
| 146 | #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ | ||
| 147 | #define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ | ||
| 148 | #define VMCCR_RefTest (1<<10) /* refresh test */ | ||
| 149 | #define VMCCR_RefLow Fld(6,11) /* refresh low counter */ | ||
| 150 | #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ | ||
| 151 | #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ | ||
| 152 | #define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ | ||
| 153 | |||
| 154 | #endif LANGUAGE == C | ||
| 155 | |||
| 156 | |||
| 157 | /* Update FIFO | ||
| 158 | * | ||
| 159 | * Registers | ||
| 160 | * UFCR Update FIFO Control Register | ||
| 161 | * UFSR Update FIFO Status Register | ||
| 162 | * UFLVLR update FIFO level register | ||
| 163 | * UFDR update FIFO data register | ||
| 164 | */ | ||
| 165 | |||
| 166 | #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ | ||
| 167 | #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ | ||
| 168 | #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ | ||
| 169 | #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ | ||
| 170 | |||
| 171 | #if LANGUAGE == C | ||
| 172 | |||
| 173 | #define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) | ||
| 174 | #define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) | ||
| 175 | #define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) | ||
| 176 | #define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) | ||
| 177 | |||
| 178 | |||
| 179 | #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ | ||
| 180 | |||
| 181 | #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ | ||
| 182 | |||
| 183 | #endif /* LANGUAGE == C */ | ||
| 184 | |||
| 185 | /* System Controller | ||
| 186 | * | ||
| 187 | * Registers | ||
| 188 | * SKPCR Power Control Register | ||
| 189 | * SKCDR Clock Divider Register | ||
| 190 | * DACDR1 DAC1 Data register | ||
| 191 | * DACDR2 DAC2 Data register | ||
| 192 | */ | ||
| 193 | |||
| 194 | #define _SKPCR _SA1101(0x00000400) | ||
| 195 | #define _SKCDR _SA1101(0x00040000) | ||
| 196 | #define _DACDR1 _SA1101(0x00060000) | ||
| 197 | #define _DACDR2 _SA1101(0x00060400) | ||
| 198 | |||
| 199 | #if LANGUAGE == C | ||
| 200 | #define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) | ||
| 201 | #define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) | ||
| 202 | #define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) | ||
| 203 | #define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) | ||
| 204 | |||
| 205 | #define SKPCR_UCLKEn 0x01 /* USB Enable */ | ||
| 206 | #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ | ||
| 207 | #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ | ||
| 208 | #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ | ||
| 209 | #define SKPCR_PICLKEn 0x10 /* parallel port Enable */ | ||
| 210 | #define SKPCR_DCLKEn 0x20 /* DACs Enable */ | ||
| 211 | #define SKPCR_nKPADEn 0x40 /* Multiplexer */ | ||
| 212 | |||
| 213 | #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ | ||
| 214 | #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ | ||
| 215 | #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ | ||
| 216 | #define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ | ||
| 217 | #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ | ||
| 218 | #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ | ||
| 219 | #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ | ||
| 220 | #define SKDCR_ChargePump (1<<25) /* Charge pump control */ | ||
| 221 | #define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ | ||
| 222 | #define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ | ||
| 223 | #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ | ||
| 224 | |||
| 225 | #define DACDR_DACCount Fld(8,0) /* Count value */ | ||
| 226 | #define DACDR1_DACCount DACDR_DACCount | ||
| 227 | #define DACDR2_DACCount DACDR_DACCount | ||
| 228 | |||
| 229 | #endif /* LANGUAGE == C */ | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Parallel Port Interface | ||
| 233 | * | ||
| 234 | * Registers | ||
| 235 | * IEEE_Config IEEE mode selection and programmable attributes | ||
| 236 | * IEEE_Control Controls the states of IEEE port control outputs | ||
| 237 | * IEEE_Data Forward transfer data register | ||
| 238 | * IEEE_Addr Forward transfer address register | ||
| 239 | * IEEE_Status Port IO signal status register | ||
| 240 | * IEEE_IntStatus Port interrupts status register | ||
| 241 | * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels | ||
| 242 | * IEEE_InitTime Forward timeout counter initial value | ||
| 243 | * IEEE_TimerStatus Forward timeout counter current value | ||
| 244 | * IEEE_FifoReset Reset forward transfer FIFO | ||
| 245 | * IEEE_ReloadValue Counter reload value | ||
| 246 | * IEEE_TestControl Control testmode | ||
| 247 | * IEEE_TestDataIn Test data register | ||
| 248 | * IEEE_TestDataInEn Enable test data | ||
| 249 | * IEEE_TestCtrlIn Test control signals | ||
| 250 | * IEEE_TestCtrlInEn Enable test control signals | ||
| 251 | * IEEE_TestDataStat Current data bus value | ||
| 252 | * | ||
| 253 | */ | ||
| 254 | |||
| 255 | /* | ||
| 256 | * The control registers are defined as offsets from a base address | ||
| 257 | */ | ||
| 258 | |||
| 259 | #define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) | ||
| 260 | |||
| 261 | #define _IEEE_Config _IEEE( 0x0000 ) | ||
| 262 | #define _IEEE_Control _IEEE( 0x0400 ) | ||
| 263 | #define _IEEE_Data _IEEE( 0x4000 ) | ||
| 264 | #define _IEEE_Addr _IEEE( 0x0800 ) | ||
| 265 | #define _IEEE_Status _IEEE( 0x0c00 ) | ||
| 266 | #define _IEEE_IntStatus _IEEE( 0x1000 ) | ||
| 267 | #define _IEEE_FifoLevels _IEEE( 0x1400 ) | ||
| 268 | #define _IEEE_InitTime _IEEE( 0x1800 ) | ||
| 269 | #define _IEEE_TimerStatus _IEEE( 0x1c00 ) | ||
| 270 | #define _IEEE_FifoReset _IEEE( 0x2000 ) | ||
| 271 | #define _IEEE_ReloadValue _IEEE( 0x3c00 ) | ||
| 272 | #define _IEEE_TestControl _IEEE( 0x2400 ) | ||
| 273 | #define _IEEE_TestDataIn _IEEE( 0x2800 ) | ||
| 274 | #define _IEEE_TestDataInEn _IEEE( 0x2c00 ) | ||
| 275 | #define _IEEE_TestCtrlIn _IEEE( 0x3000 ) | ||
| 276 | #define _IEEE_TestCtrlInEn _IEEE( 0x3400 ) | ||
| 277 | #define _IEEE_TestDataStat _IEEE( 0x3800 ) | ||
| 278 | |||
| 279 | |||
| 280 | #if LANGUAGE == C | ||
| 281 | #define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config))) | ||
| 282 | #define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control))) | ||
| 283 | #define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data))) | ||
| 284 | #define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr))) | ||
| 285 | #define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status))) | ||
| 286 | #define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus))) | ||
| 287 | #define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels))) | ||
| 288 | #define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime))) | ||
| 289 | #define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus))) | ||
| 290 | #define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset))) | ||
| 291 | #define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue))) | ||
| 292 | #define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl))) | ||
| 293 | #define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn))) | ||
| 294 | #define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn))) | ||
| 295 | #define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn))) | ||
| 296 | #define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn))) | ||
| 297 | #define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat))) | ||
| 298 | |||
| 299 | |||
| 300 | #define IEEE_Config_M Fld(3,0) /* Mode select */ | ||
| 301 | #define IEEE_Config_D 0x04 /* FIFO access enable */ | ||
| 302 | #define IEEE_Config_B 0x08 /* 9-bit word enable */ | ||
| 303 | #define IEEE_Config_T 0x10 /* Data transfer enable */ | ||
| 304 | #define IEEE_Config_A 0x20 /* Data transfer direction */ | ||
| 305 | #define IEEE_Config_E 0x40 /* Timer enable */ | ||
| 306 | #define IEEE_Control_A 0x08 /* AutoFd output */ | ||
| 307 | #define IEEE_Control_E 0x04 /* Selectin output */ | ||
| 308 | #define IEEE_Control_T 0x02 /* Strobe output */ | ||
| 309 | #define IEEE_Control_I 0x01 /* Port init output */ | ||
| 310 | #define IEEE_Data_C (1<<31) /* Byte count */ | ||
| 311 | #define IEEE_Data_Db Fld(9,16) /* Data byte 2 */ | ||
| 312 | #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */ | ||
| 313 | #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */ | ||
| 314 | #define IEEE_Status_A 0x0100 /* nAutoFd port output status */ | ||
| 315 | #define IEEE_Status_E 0x0080 /* nSelectIn port output status */ | ||
| 316 | #define IEEE_Status_T 0x0040 /* nStrobe port output status */ | ||
| 317 | #define IEEE_Status_I 0x0020 /* nInit port output status */ | ||
| 318 | #define IEEE_Status_B 0x0010 /* Busy port inout status */ | ||
| 319 | #define IEEE_Status_S 0x0008 /* Select port input status */ | ||
| 320 | #define IEEE_Status_K 0x0004 /* nAck port input status */ | ||
| 321 | #define IEEE_Status_F 0x0002 /* nFault port input status */ | ||
| 322 | #define IEEE_Status_R 0x0001 /* pError port input status */ | ||
| 323 | |||
| 324 | #define IEEE_IntStatus_IntReqDat 0x0100 | ||
| 325 | #define IEEE_IntStatus_IntReqEmp 0x0080 | ||
| 326 | #define IEEE_IntStatus_IntReqInt 0x0040 | ||
| 327 | #define IEEE_IntStatus_IntReqRav 0x0020 | ||
| 328 | #define IEEE_IntStatus_IntReqTim 0x0010 | ||
| 329 | #define IEEE_IntStatus_RevAddrComp 0x0008 | ||
| 330 | #define IEEE_IntStatus_RevDataComp 0x0004 | ||
| 331 | #define IEEE_IntStatus_FwdAddrComp 0x0002 | ||
| 332 | #define IEEE_IntStatus_FwdDataComp 0x0001 | ||
| 333 | #define IEEE_FifoLevels_RevFifoLevel 2 | ||
| 334 | #define IEEE_FifoLevels_FwdFifoLevel 1 | ||
| 335 | #define IEEE_InitTime_TimValInit Fld(22,0) | ||
| 336 | #define IEEE_TimerStatus_TimValStat Fld(22,0) | ||
| 337 | #define IEEE_ReloadValue_Reload Fld(4,0) | ||
| 338 | |||
| 339 | #define IEEE_TestControl_RegClk 0x04 | ||
| 340 | #define IEEE_TestControl_ClockSelect Fld(2,1) | ||
| 341 | #define IEEE_TestControl_TimerTestModeEn 0x01 | ||
| 342 | #define IEEE_TestCtrlIn_PError 0x10 | ||
| 343 | #define IEEE_TestCtrlIn_nFault 0x08 | ||
| 344 | #define IEEE_TestCtrlIn_nAck 0x04 | ||
| 345 | #define IEEE_TestCtrlIn_PSel 0x02 | ||
| 346 | #define IEEE_TestCtrlIn_Busy 0x01 | ||
| 347 | |||
| 348 | #endif /* LANGUAGE == C */ | ||
| 349 | |||
| 350 | /* | ||
| 351 | * VGA Controller | ||
| 352 | * | ||
| 353 | * Registers | ||
| 354 | * VideoControl Video Control Register | ||
| 355 | * VgaTiming0 VGA Timing Register 0 | ||
| 356 | * VgaTiming1 VGA Timing Register 1 | ||
| 357 | * VgaTiming2 VGA Timing Register 2 | ||
| 358 | * VgaTiming3 VGA Timing Register 3 | ||
| 359 | * VgaBorder VGA Border Color Register | ||
| 360 | * VgaDBAR VGADMA Base Address Register | ||
| 361 | * VgaDCAR VGADMA Channel Current Address Register | ||
| 362 | * VgaStatus VGA Status Register | ||
| 363 | * VgaInterruptMask VGA Interrupt Mask Register | ||
| 364 | * VgaPalette VGA Palette Registers | ||
| 365 | * DacControl DAC Control Register | ||
| 366 | * VgaTest VGA Controller Test Register | ||
| 367 | */ | ||
| 368 | |||
| 369 | #define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL ) | ||
| 370 | |||
| 371 | #define _VideoControl _VGA( 0x0000 ) | ||
| 372 | #define _VgaTiming0 _VGA( 0x0400 ) | ||
| 373 | #define _VgaTiming1 _VGA( 0x0800 ) | ||
| 374 | #define _VgaTiming2 _VGA( 0x0c00 ) | ||
| 375 | #define _VgaTiming3 _VGA( 0x1000 ) | ||
| 376 | #define _VgaBorder _VGA( 0x1400 ) | ||
| 377 | #define _VgaDBAR _VGA( 0x1800 ) | ||
| 378 | #define _VgaDCAR _VGA( 0x1c00 ) | ||
| 379 | #define _VgaStatus _VGA( 0x2000 ) | ||
| 380 | #define _VgaInterruptMask _VGA( 0x2400 ) | ||
| 381 | #define _VgaPalette _VGA( 0x40000 ) | ||
| 382 | #define _DacControl _VGA( 0x3000 ) | ||
| 383 | #define _VgaTest _VGA( 0x2c00 ) | ||
| 384 | |||
| 385 | #if (LANGUAGE == C) | ||
| 386 | #define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl))) | ||
| 387 | #define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0))) | ||
| 388 | #define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1))) | ||
| 389 | #define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2))) | ||
| 390 | #define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3))) | ||
| 391 | #define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder))) | ||
| 392 | #define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR))) | ||
| 393 | #define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR))) | ||
| 394 | #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) | ||
| 395 | #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) | ||
| 396 | #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) | ||
| 397 | #define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))) | ||
| 398 | #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) | ||
| 399 | |||
| 400 | #define VideoControl_VgaEn 0x00000000 | ||
| 401 | #define VideoControl_BGR 0x00000001 | ||
| 402 | #define VideoControl_VCompVal Fld(2,2) | ||
| 403 | #define VideoControl_VgaReq Fld(4,4) | ||
| 404 | #define VideoControl_VBurstL Fld(4,8) | ||
| 405 | #define VideoControl_VMode (1<<12) | ||
| 406 | #define VideoControl_PalRead (1<<13) | ||
| 407 | |||
| 408 | #define VgaTiming0_PPL Fld(6,2) | ||
| 409 | #define VgaTiming0_HSW Fld(8,8) | ||
| 410 | #define VgaTiming0_HFP Fld(8,16) | ||
| 411 | #define VgaTiming0_HBP Fld(8,24) | ||
| 412 | |||
| 413 | #define VgaTiming1_LPS Fld(10,0) | ||
| 414 | #define VgaTiming1_VSW Fld(6,10) | ||
| 415 | #define VgaTiming1_VFP Fld(8,16) | ||
| 416 | #define VgaTiming1_VBP Fld(8,24) | ||
| 417 | |||
| 418 | #define VgaTiming2_IVS 0x01 | ||
| 419 | #define VgaTiming2_IHS 0x02 | ||
| 420 | #define VgaTiming2_CVS 0x04 | ||
| 421 | #define VgaTiming2_CHS 0x08 | ||
| 422 | |||
| 423 | #define VgaTiming3_HBS Fld(8,0) | ||
| 424 | #define VgaTiming3_HBE Fld(8,8) | ||
| 425 | #define VgaTiming3_VBS Fld(8,16) | ||
| 426 | #define VgaTiming3_VBE Fld(8,24) | ||
| 427 | |||
| 428 | #define VgaBorder_BCOL Fld(24,0) | ||
| 429 | |||
| 430 | #define VgaStatus_VFUF 0x01 | ||
| 431 | #define VgaStatus_VNext 0x02 | ||
| 432 | #define VgaStatus_VComp 0x04 | ||
| 433 | |||
| 434 | #define VgaInterruptMask_VFUFMask 0x00 | ||
| 435 | #define VgaInterruptMask_VNextMask 0x01 | ||
| 436 | #define VgaInterruptMask_VCompMask 0x02 | ||
| 437 | |||
| 438 | #define VgaPalette_R Fld(8,0) | ||
| 439 | #define VgaPalette_G Fld(8,8) | ||
| 440 | #define VgaPalette_B Fld(8,16) | ||
| 441 | |||
| 442 | #define DacControl_DACON 0x0001 | ||
| 443 | #define DacControl_COMPON 0x0002 | ||
| 444 | #define DacControl_PEDON 0x0004 | ||
| 445 | #define DacControl_RTrim Fld(5,4) | ||
| 446 | #define DacControl_GTrim Fld(5,9) | ||
| 447 | #define DacControl_BTrim Fld(5,14) | ||
| 448 | |||
| 449 | #define VgaTest_TDAC 0x00 | ||
| 450 | #define VgaTest_Datatest Fld(4,1) | ||
| 451 | #define VgaTest_DACTESTDAC 0x10 | ||
| 452 | #define VgaTest_DACTESTOUT Fld(3,5) | ||
| 453 | |||
| 454 | #endif /* LANGUAGE == C */ | ||
| 455 | |||
| 456 | /* | ||
| 457 | * USB Host Interface Controller | ||
| 458 | * | ||
| 459 | * Registers | ||
| 460 | * Revision | ||
| 461 | * Control | ||
| 462 | * CommandStatus | ||
| 463 | * InterruptStatus | ||
| 464 | * InterruptEnable | ||
| 465 | * HCCA | ||
| 466 | * PeriodCurrentED | ||
| 467 | * ControlHeadED | ||
| 468 | * BulkHeadED | ||
| 469 | * BulkCurrentED | ||
| 470 | * DoneHead | ||
| 471 | * FmInterval | ||
| 472 | * FmRemaining | ||
| 473 | * FmNumber | ||
| 474 | * PeriodicStart | ||
| 475 | * LSThreshold | ||
| 476 | * RhDescriptorA | ||
| 477 | * RhDescriptorB | ||
| 478 | * RhStatus | ||
| 479 | * RhPortStatus | ||
| 480 | * USBStatus | ||
| 481 | * USBReset | ||
| 482 | * USTAR | ||
| 483 | * USWER | ||
| 484 | * USRFR | ||
| 485 | * USNFR | ||
| 486 | * USTCSR | ||
| 487 | * USSR | ||
| 488 | * | ||
| 489 | */ | ||
| 490 | |||
| 491 | #define _USB( x ) _SA1101( ( x ) + __USB_CONTROL ) | ||
| 492 | |||
| 493 | |||
| 494 | #define _Revision _USB( 0x0000 ) | ||
| 495 | #define _Control _USB( 0x0888 ) | ||
| 496 | #define _CommandStatus _USB( 0x0c00 ) | ||
| 497 | #define _InterruptStatus _USB( 0x1000 ) | ||
| 498 | #define _InterruptEnable _USB( 0x1400 ) | ||
| 499 | #define _HCCA _USB( 0x1800 ) | ||
| 500 | #define _PeriodCurrentED _USB( 0x1c00 ) | ||
| 501 | #define _ControlHeadED _USB( 0x2000 ) | ||
| 502 | #define _BulkHeadED _USB( 0x2800 ) | ||
| 503 | #define _BulkCurrentED _USB( 0x2c00 ) | ||
| 504 | #define _DoneHead _USB( 0x3000 ) | ||
| 505 | #define _FmInterval _USB( 0x3400 ) | ||
| 506 | #define _FmRemaining _USB( 0x3800 ) | ||
| 507 | #define _FmNumber _USB( 0x3c00 ) | ||
| 508 | #define _PeriodicStart _USB( 0x4000 ) | ||
| 509 | #define _LSThreshold _USB( 0x4400 ) | ||
| 510 | #define _RhDescriptorA _USB( 0x4800 ) | ||
| 511 | #define _RhDescriptorB _USB( 0x4c00 ) | ||
| 512 | #define _RhStatus _USB( 0x5000 ) | ||
| 513 | #define _RhPortStatus _USB( 0x5400 ) | ||
| 514 | #define _USBStatus _USB( 0x11800 ) | ||
| 515 | #define _USBReset _USB( 0x11c00 ) | ||
| 516 | |||
| 517 | #define _USTAR _USB( 0x10400 ) | ||
| 518 | #define _USWER _USB( 0x10800 ) | ||
| 519 | #define _USRFR _USB( 0x10c00 ) | ||
| 520 | #define _USNFR _USB( 0x11000 ) | ||
| 521 | #define _USTCSR _USB( 0x11400 ) | ||
| 522 | #define _USSR _USB( 0x11800 ) | ||
| 523 | |||
| 524 | |||
| 525 | #if (LANGUAGE == C) | ||
| 526 | |||
| 527 | #define Revision (*((volatile Word *) SA1101_p2v (_Revision))) | ||
| 528 | #define Control (*((volatile Word *) SA1101_p2v (_Control))) | ||
| 529 | #define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus))) | ||
| 530 | #define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus))) | ||
| 531 | #define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable))) | ||
| 532 | #define HCCA (*((volatile Word *) SA1101_p2v (_HCCA))) | ||
| 533 | #define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED))) | ||
| 534 | #define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED))) | ||
| 535 | #define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED))) | ||
| 536 | #define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED))) | ||
| 537 | #define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead))) | ||
| 538 | #define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval))) | ||
| 539 | #define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining))) | ||
| 540 | #define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber))) | ||
| 541 | #define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart))) | ||
| 542 | #define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold))) | ||
| 543 | #define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA))) | ||
| 544 | #define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB))) | ||
| 545 | #define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus))) | ||
| 546 | #define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus))) | ||
| 547 | #define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus))) | ||
| 548 | #define USBReset (*((volatile Word *) SA1101_p2v (_USBReset))) | ||
| 549 | #define USTAR (*((volatile Word *) SA1101_p2v (_USTAR))) | ||
| 550 | #define USWER (*((volatile Word *) SA1101_p2v (_USWER))) | ||
| 551 | #define USRFR (*((volatile Word *) SA1101_p2v (_USRFR))) | ||
| 552 | #define USNFR (*((volatile Word *) SA1101_p2v (_USNFR))) | ||
| 553 | #define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR))) | ||
| 554 | #define USSR (*((volatile Word *) SA1101_p2v (_USSR))) | ||
| 555 | |||
| 556 | |||
| 557 | #define USBStatus_IrqHciRmtWkp (1<<7) | ||
| 558 | #define USBStatus_IrqHciBuffAcc (1<<8) | ||
| 559 | #define USBStatus_nIrqHciM (1<<9) | ||
| 560 | #define USBStatus_nHciMFClr (1<<10) | ||
| 561 | |||
| 562 | #define USBReset_ForceIfReset 0x01 | ||
| 563 | #define USBReset_ForceHcReset 0x02 | ||
| 564 | #define USBReset_ClkGenReset 0x04 | ||
| 565 | |||
| 566 | #define USTCR_RdBstCntrl Fld(3,0) | ||
| 567 | #define USTCR_ByteEnable Fld(4,3) | ||
| 568 | #define USTCR_WriteEn (1<<7) | ||
| 569 | #define USTCR_FifoCir (1<<8) | ||
| 570 | #define USTCR_TestXferSel (1<<9) | ||
| 571 | #define USTCR_FifoCirAtEnd (1<<10) | ||
| 572 | #define USTCR_nSimScaleDownClk (1<<11) | ||
| 573 | |||
| 574 | #define USSR_nAppMDEmpty 0x01 | ||
| 575 | #define USSR_nAppMDFirst 0x02 | ||
| 576 | #define USSR_nAppMDLast 0x04 | ||
| 577 | #define USSR_nAppMDFull 0x08 | ||
| 578 | #define USSR_nAppMAFull 0x10 | ||
| 579 | #define USSR_XferReq 0x20 | ||
| 580 | #define USSR_XferEnd 0x40 | ||
| 581 | |||
| 582 | #endif /* LANGUAGE == C */ | ||
| 583 | |||
| 584 | |||
| 585 | /* | ||
| 586 | * Interrupt Controller | ||
| 587 | * | ||
| 588 | * Registers | ||
| 589 | * INTTEST0 Test register 0 | ||
| 590 | * INTTEST1 Test register 1 | ||
| 591 | * INTENABLE0 Interrupt Enable register 0 | ||
| 592 | * INTENABLE1 Interrupt Enable register 1 | ||
| 593 | * INTPOL0 Interrupt Polarity selection 0 | ||
| 594 | * INTPOL1 Interrupt Polarity selection 1 | ||
| 595 | * INTTSTSEL Interrupt source selection | ||
| 596 | * INTSTATCLR0 Interrupt Status 0 | ||
| 597 | * INTSTATCLR1 Interrupt Status 1 | ||
| 598 | * INTSET0 Interrupt Set 0 | ||
| 599 | * INTSET1 Interrupt Set 1 | ||
| 600 | */ | ||
| 601 | |||
| 602 | #define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL) | ||
| 603 | |||
| 604 | #define _INTTEST0 _INT( 0x1000 ) | ||
| 605 | #define _INTTEST1 _INT( 0x1400 ) | ||
| 606 | #define _INTENABLE0 _INT( 0x2000 ) | ||
| 607 | #define _INTENABLE1 _INT( 0x2400 ) | ||
| 608 | #define _INTPOL0 _INT( 0x3000 ) | ||
| 609 | #define _INTPOL1 _INT( 0x3400 ) | ||
| 610 | #define _INTTSTSEL _INT( 0x5000 ) | ||
| 611 | #define _INTSTATCLR0 _INT( 0x6000 ) | ||
| 612 | #define _INTSTATCLR1 _INT( 0x6400 ) | ||
| 613 | #define _INTSET0 _INT( 0x7000 ) | ||
| 614 | #define _INTSET1 _INT( 0x7400 ) | ||
| 615 | |||
| 616 | #if ( LANGUAGE == C ) | ||
| 617 | #define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0))) | ||
| 618 | #define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1))) | ||
| 619 | #define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0))) | ||
| 620 | #define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1))) | ||
| 621 | #define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0))) | ||
| 622 | #define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1))) | ||
| 623 | #define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL))) | ||
| 624 | #define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0))) | ||
| 625 | #define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1))) | ||
| 626 | #define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0))) | ||
| 627 | #define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1))) | ||
| 628 | |||
| 629 | #endif /* LANGUAGE == C */ | ||
| 630 | |||
| 631 | /* | ||
| 632 | * PS/2 Trackpad and Mouse Interfaces | ||
| 633 | * | ||
| 634 | * Registers (prefix kbd applies to trackpad interface, mse to mouse) | ||
| 635 | * KBDCR Control Register | ||
| 636 | * KBDSTAT Status Register | ||
| 637 | * KBDDATA Transmit/Receive Data register | ||
| 638 | * KBDCLKDIV Clock Division Register | ||
| 639 | * KBDPRECNT Clock Precount Register | ||
| 640 | * KBDTEST1 Test register 1 | ||
| 641 | * KBDTEST2 Test register 2 | ||
| 642 | * KBDTEST3 Test register 3 | ||
| 643 | * KBDTEST4 Test register 4 | ||
| 644 | * MSECR | ||
| 645 | * MSESTAT | ||
| 646 | * MSEDATA | ||
| 647 | * MSECLKDIV | ||
| 648 | * MSEPRECNT | ||
| 649 | * MSETEST1 | ||
| 650 | * MSETEST2 | ||
| 651 | * MSETEST3 | ||
| 652 | * MSETEST4 | ||
| 653 | * | ||
| 654 | */ | ||
| 655 | |||
| 656 | #define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE ) | ||
| 657 | #define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE ) | ||
| 658 | |||
| 659 | #define _KBDCR _KBD( 0x0000 ) | ||
| 660 | #define _KBDSTAT _KBD( 0x0400 ) | ||
| 661 | #define _KBDDATA _KBD( 0x0800 ) | ||
| 662 | #define _KBDCLKDIV _KBD( 0x0c00 ) | ||
| 663 | #define _KBDPRECNT _KBD( 0x1000 ) | ||
| 664 | #define _KBDTEST1 _KBD( 0x2000 ) | ||
| 665 | #define _KBDTEST2 _KBD( 0x2400 ) | ||
| 666 | #define _KBDTEST3 _KBD( 0x2800 ) | ||
| 667 | #define _KBDTEST4 _KBD( 0x2c00 ) | ||
| 668 | #define _MSECR _MSE( 0x0000 ) | ||
| 669 | #define _MSESTAT _MSE( 0x0400 ) | ||
| 670 | #define _MSEDATA _MSE( 0x0800 ) | ||
| 671 | #define _MSECLKDIV _MSE( 0x0c00 ) | ||
| 672 | #define _MSEPRECNT _MSE( 0x1000 ) | ||
| 673 | #define _MSETEST1 _MSE( 0x2000 ) | ||
| 674 | #define _MSETEST2 _MSE( 0x2400 ) | ||
| 675 | #define _MSETEST3 _MSE( 0x2800 ) | ||
| 676 | #define _MSETEST4 _MSE( 0x2c00 ) | ||
| 677 | |||
| 678 | #if ( LANGUAGE == C ) | ||
| 679 | |||
| 680 | #define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR))) | ||
| 681 | #define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT))) | ||
| 682 | #define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA))) | ||
| 683 | #define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV))) | ||
| 684 | #define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT))) | ||
| 685 | #define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1))) | ||
| 686 | #define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2))) | ||
| 687 | #define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3))) | ||
| 688 | #define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4))) | ||
| 689 | #define MSECR (*((volatile Word *) SA1101_p2v (_MSECR))) | ||
| 690 | #define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT))) | ||
| 691 | #define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA))) | ||
| 692 | #define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV))) | ||
| 693 | #define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT))) | ||
| 694 | #define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1))) | ||
| 695 | #define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2))) | ||
| 696 | #define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3))) | ||
| 697 | #define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4))) | ||
| 698 | |||
| 699 | |||
| 700 | #define KBDCR_ENA 0x08 | ||
| 701 | #define KBDCR_FKD 0x02 | ||
| 702 | #define KBDCR_FKC 0x01 | ||
| 703 | |||
| 704 | #define KBDSTAT_TXE 0x80 | ||
| 705 | #define KBDSTAT_TXB 0x40 | ||
| 706 | #define KBDSTAT_RXF 0x20 | ||
| 707 | #define KBDSTAT_RXB 0x10 | ||
| 708 | #define KBDSTAT_ENA 0x08 | ||
| 709 | #define KBDSTAT_RXP 0x04 | ||
| 710 | #define KBDSTAT_KBD 0x02 | ||
| 711 | #define KBDSTAT_KBC 0x01 | ||
| 712 | |||
| 713 | #define KBDCLKDIV_DivVal Fld(4,0) | ||
| 714 | |||
| 715 | #define MSECR_ENA 0x08 | ||
| 716 | #define MSECR_FKD 0x02 | ||
| 717 | #define MSECR_FKC 0x01 | ||
| 718 | |||
| 719 | #define MSESTAT_TXE 0x80 | ||
| 720 | #define MSESTAT_TXB 0x40 | ||
| 721 | #define MSESTAT_RXF 0x20 | ||
| 722 | #define MSESTAT_RXB 0x10 | ||
| 723 | #define MSESTAT_ENA 0x08 | ||
| 724 | #define MSESTAT_RXP 0x04 | ||
| 725 | #define MSESTAT_MSD 0x02 | ||
| 726 | #define MSESTAT_MSC 0x01 | ||
| 727 | |||
| 728 | #define MSECLKDIV_DivVal Fld(4,0) | ||
| 729 | |||
| 730 | #define KBDTEST1_CD 0x80 | ||
| 731 | #define KBDTEST1_RC1 0x40 | ||
| 732 | #define KBDTEST1_MC 0x20 | ||
| 733 | #define KBDTEST1_C Fld(2,3) | ||
| 734 | #define KBDTEST1_T2 0x40 | ||
| 735 | #define KBDTEST1_T1 0x20 | ||
| 736 | #define KBDTEST1_T0 0x10 | ||
| 737 | #define KBDTEST2_TICBnRES 0x08 | ||
| 738 | #define KBDTEST2_RKC 0x04 | ||
| 739 | #define KBDTEST2_RKD 0x02 | ||
| 740 | #define KBDTEST2_SEL 0x01 | ||
| 741 | #define KBDTEST3_ms_16 0x80 | ||
| 742 | #define KBDTEST3_us_64 0x40 | ||
| 743 | #define KBDTEST3_us_16 0x20 | ||
| 744 | #define KBDTEST3_DIV8 0x10 | ||
| 745 | #define KBDTEST3_DIn 0x08 | ||
| 746 | #define KBDTEST3_CIn 0x04 | ||
| 747 | #define KBDTEST3_KD 0x02 | ||
| 748 | #define KBDTEST3_KC 0x01 | ||
| 749 | #define KBDTEST4_BC12 0x80 | ||
| 750 | #define KBDTEST4_BC11 0x40 | ||
| 751 | #define KBDTEST4_TRES 0x20 | ||
| 752 | #define KBDTEST4_CLKOE 0x10 | ||
| 753 | #define KBDTEST4_CRES 0x08 | ||
| 754 | #define KBDTEST4_RXB 0x04 | ||
| 755 | #define KBDTEST4_TXB 0x02 | ||
| 756 | #define KBDTEST4_SRX 0x01 | ||
| 757 | |||
| 758 | #define MSETEST1_CD 0x80 | ||
| 759 | #define MSETEST1_RC1 0x40 | ||
| 760 | #define MSETEST1_MC 0x20 | ||
| 761 | #define MSETEST1_C Fld(2,3) | ||
| 762 | #define MSETEST1_T2 0x40 | ||
| 763 | #define MSETEST1_T1 0x20 | ||
| 764 | #define MSETEST1_T0 0x10 | ||
| 765 | #define MSETEST2_TICBnRES 0x08 | ||
| 766 | #define MSETEST2_RKC 0x04 | ||
| 767 | #define MSETEST2_RKD 0x02 | ||
| 768 | #define MSETEST2_SEL 0x01 | ||
| 769 | #define MSETEST3_ms_16 0x80 | ||
| 770 | #define MSETEST3_us_64 0x40 | ||
| 771 | #define MSETEST3_us_16 0x20 | ||
| 772 | #define MSETEST3_DIV8 0x10 | ||
| 773 | #define MSETEST3_DIn 0x08 | ||
| 774 | #define MSETEST3_CIn 0x04 | ||
| 775 | #define MSETEST3_KD 0x02 | ||
| 776 | #define MSETEST3_KC 0x01 | ||
| 777 | #define MSETEST4_BC12 0x80 | ||
| 778 | #define MSETEST4_BC11 0x40 | ||
| 779 | #define MSETEST4_TRES 0x20 | ||
| 780 | #define MSETEST4_CLKOE 0x10 | ||
| 781 | #define MSETEST4_CRES 0x08 | ||
| 782 | #define MSETEST4_RXB 0x04 | ||
| 783 | #define MSETEST4_TXB 0x02 | ||
| 784 | #define MSETEST4_SRX 0x01 | ||
| 785 | |||
| 786 | #endif /* LANGUAGE == C */ | ||
| 787 | |||
| 788 | |||
| 789 | /* | ||
| 790 | * General-Purpose I/O Interface | ||
| 791 | * | ||
| 792 | * Registers | ||
| 793 | * PADWR Port A Data Write Register | ||
| 794 | * PBDWR Port B Data Write Register | ||
| 795 | * PADRR Port A Data Read Register | ||
| 796 | * PBDRR Port B Data Read Register | ||
| 797 | * PADDR Port A Data Direction Register | ||
| 798 | * PBDDR Port B Data Direction Register | ||
| 799 | * PASSR Port A Sleep State Register | ||
| 800 | * PBSSR Port B Sleep State Register | ||
| 801 | * | ||
| 802 | */ | ||
| 803 | |||
| 804 | #define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE ) | ||
| 805 | |||
| 806 | #define _PADWR _PIO( 0x0000 ) | ||
| 807 | #define _PBDWR _PIO( 0x0400 ) | ||
| 808 | #define _PADRR _PIO( 0x0000 ) | ||
| 809 | #define _PBDRR _PIO( 0x0400 ) | ||
| 810 | #define _PADDR _PIO( 0x0800 ) | ||
| 811 | #define _PBDDR _PIO( 0x0c00 ) | ||
| 812 | #define _PASSR _PIO( 0x1000 ) | ||
| 813 | #define _PBSSR _PIO( 0x1400 ) | ||
| 814 | |||
| 815 | |||
| 816 | #if ( LANGUAGE == C ) | ||
| 817 | |||
| 818 | |||
| 819 | #define PADWR (*((volatile Word *) SA1101_p2v (_PADWR))) | ||
| 820 | #define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR))) | ||
| 821 | #define PADRR (*((volatile Word *) SA1101_p2v (_PADRR))) | ||
| 822 | #define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR))) | ||
| 823 | #define PADDR (*((volatile Word *) SA1101_p2v (_PADDR))) | ||
| 824 | #define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR))) | ||
| 825 | #define PASSR (*((volatile Word *) SA1101_p2v (_PASSR))) | ||
| 826 | #define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR))) | ||
| 827 | |||
| 828 | #endif | ||
| 829 | |||
| 830 | |||
| 831 | |||
| 832 | /* | ||
| 833 | * Keypad Interface | ||
| 834 | * | ||
| 835 | * Registers | ||
| 836 | * PXDWR | ||
| 837 | * PXDRR | ||
| 838 | * PYDWR | ||
| 839 | * PYDRR | ||
| 840 | * | ||
| 841 | */ | ||
| 842 | |||
| 843 | #define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) | ||
| 844 | |||
| 845 | #define _PXDWR _KEYPAD( 0x0000 ) | ||
| 846 | #define _PXDRR _KEYPAD( 0x0000 ) | ||
| 847 | #define _PYDWR _KEYPAD( 0x0400 ) | ||
| 848 | #define _PYDRR _KEYPAD( 0x0400 ) | ||
| 849 | |||
| 850 | #if ( LANGUAGE == C ) | ||
| 851 | |||
| 852 | |||
| 853 | #define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR))) | ||
| 854 | #define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR))) | ||
| 855 | #define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR))) | ||
| 856 | #define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR))) | ||
| 857 | |||
| 858 | #endif | ||
| 859 | |||
| 860 | |||
| 861 | |||
| 862 | /* | ||
| 863 | * PCMCIA Interface | ||
| 864 | * | ||
| 865 | * Registers | ||
| 866 | * PCSR Status Register | ||
| 867 | * PCCR Control Register | ||
| 868 | * PCSSR Sleep State Register | ||
| 869 | * | ||
| 870 | */ | ||
| 871 | |||
| 872 | #define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE ) | ||
| 873 | |||
| 874 | #define _PCSR _CARD( 0x0000 ) | ||
| 875 | #define _PCCR _CARD( 0x0400 ) | ||
| 876 | #define _PCSSR _CARD( 0x0800 ) | ||
| 877 | |||
| 878 | #if ( LANGUAGE == C ) | ||
| 879 | #define PCSR (*((volatile Word *) SA1101_p2v (_PCSR))) | ||
| 880 | #define PCCR (*((volatile Word *) SA1101_p2v (_PCCR))) | ||
| 881 | #define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR))) | ||
| 882 | |||
| 883 | #define PCSR_S0_ready 0x0001 | ||
| 884 | #define PCSR_S1_ready 0x0002 | ||
| 885 | #define PCSR_S0_detected 0x0004 | ||
| 886 | #define PCSR_S1_detected 0x0008 | ||
| 887 | #define PCSR_S0_VS1 0x0010 | ||
| 888 | #define PCSR_S0_VS2 0x0020 | ||
| 889 | #define PCSR_S1_VS1 0x0040 | ||
| 890 | #define PCSR_S1_VS2 0x0080 | ||
| 891 | #define PCSR_S0_WP 0x0100 | ||
| 892 | #define PCSR_S1_WP 0x0200 | ||
| 893 | #define PCSR_S0_BVD1_nSTSCHG 0x0400 | ||
| 894 | #define PCSR_S0_BVD2_nSPKR 0x0800 | ||
| 895 | #define PCSR_S1_BVD1_nSTSCHG 0x1000 | ||
| 896 | #define PCSR_S1_BVD2_nSPKR 0x2000 | ||
| 897 | |||
| 898 | #define PCCR_S0_VPP0 0x0001 | ||
| 899 | #define PCCR_S0_VPP1 0x0002 | ||
| 900 | #define PCCR_S0_VCC0 0x0004 | ||
| 901 | #define PCCR_S0_VCC1 0x0008 | ||
| 902 | #define PCCR_S1_VPP0 0x0010 | ||
| 903 | #define PCCR_S1_VPP1 0x0020 | ||
| 904 | #define PCCR_S1_VCC0 0x0040 | ||
| 905 | #define PCCR_S1_VCC1 0x0080 | ||
| 906 | #define PCCR_S0_reset 0x0100 | ||
| 907 | #define PCCR_S1_reset 0x0200 | ||
| 908 | #define PCCR_S0_float 0x0400 | ||
| 909 | #define PCCR_S1_float 0x0800 | ||
| 910 | |||
| 911 | #define PCSSR_S0_VCC0 0x0001 | ||
| 912 | #define PCSSR_S0_VCC1 0x0002 | ||
| 913 | #define PCSSR_S0_VPP0 0x0004 | ||
| 914 | #define PCSSR_S0_VPP1 0x0008 | ||
| 915 | #define PCSSR_S0_control 0x0010 | ||
| 916 | #define PCSSR_S1_VCC0 0x0020 | ||
| 917 | #define PCSSR_S1_VCC1 0x0040 | ||
| 918 | #define PCSSR_S1_VPP0 0x0080 | ||
| 919 | #define PCSSR_S1_VPP1 0x0100 | ||
| 920 | #define PCSSR_S1_control 0x0200 | ||
| 921 | |||
| 922 | #endif | ||
| 923 | |||
| 924 | #undef C | ||
| 925 | #undef Assembly | ||
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1111.h b/arch/arm/mach-sa1100/include/mach/SA-1111.h new file mode 100644 index 000000000000..c38f60915cb6 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/SA-1111.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | /* | ||
| 2 | * Moved to new location | ||
| 3 | */ | ||
| 4 | #warning using old SA-1111.h - update to <asm/hardware/sa1111.h> | ||
| 5 | #include <asm/hardware/sa1111.h> | ||
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h new file mode 100644 index 000000000000..3959b20d5d1c --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/assabet.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/assabet.h | ||
| 3 | * | ||
| 4 | * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for Assabet | ||
| 7 | * Only include this file from SA1100-specific files. | ||
| 8 | * | ||
| 9 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 10 | * Definitions for Neponset added. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_ASSABET_H | ||
| 13 | #define __ASM_ARCH_ASSABET_H | ||
| 14 | |||
| 15 | |||
| 16 | /* System Configuration Register flags */ | ||
| 17 | |||
| 18 | #define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ | ||
| 19 | #define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ | ||
| 20 | #define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ | ||
| 21 | #define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ | ||
| 22 | #define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ | ||
| 23 | #define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ | ||
| 24 | |||
| 25 | #define ASSABET_SCR_INIT -1 | ||
| 26 | |||
| 27 | extern unsigned long SCR_value; | ||
| 28 | |||
| 29 | #ifdef CONFIG_ASSABET_NEPONSET | ||
| 30 | #define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) | ||
| 31 | #else | ||
| 32 | #define machine_has_neponset() (0) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | /* Board Control Register */ | ||
| 36 | |||
| 37 | #define ASSABET_BCR_BASE 0xf1000000 | ||
| 38 | #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) | ||
| 39 | |||
| 40 | #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ | ||
| 41 | #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ | ||
| 42 | #define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ | ||
| 43 | #define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ | ||
| 44 | #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ | ||
| 45 | #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ | ||
| 46 | #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ | ||
| 47 | #define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ | ||
| 48 | #define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ | ||
| 49 | #define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ | ||
| 50 | #define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ | ||
| 51 | #define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ | ||
| 52 | #define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ | ||
| 53 | #define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ | ||
| 54 | #define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ | ||
| 55 | #define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ | ||
| 56 | #define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ | ||
| 57 | #define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ | ||
| 58 | #define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ | ||
| 59 | #define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ | ||
| 60 | #define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ | ||
| 61 | #define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ | ||
| 62 | #define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ | ||
| 63 | #define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ | ||
| 64 | #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ | ||
| 65 | |||
| 66 | #ifdef CONFIG_SA1100_ASSABET | ||
| 67 | extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); | ||
| 68 | #else | ||
| 69 | #define ASSABET_BCR_frob(x,y) do { } while (0) | ||
| 70 | #endif | ||
| 71 | |||
| 72 | #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) | ||
| 73 | #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) | ||
| 74 | |||
| 75 | #define ASSABET_BSR_BASE 0xf1000000 | ||
| 76 | #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) | ||
| 77 | |||
| 78 | #define ASSABET_BSR_RS232_VALID (1 << 24) | ||
| 79 | #define ASSABET_BSR_COM_DCD (1 << 25) | ||
| 80 | #define ASSABET_BSR_COM_CTS (1 << 26) | ||
| 81 | #define ASSABET_BSR_COM_DSR (1 << 27) | ||
| 82 | #define ASSABET_BSR_RAD_CTS (1 << 28) | ||
| 83 | #define ASSABET_BSR_RAD_DSR (1 << 29) | ||
| 84 | #define ASSABET_BSR_RAD_DCD (1 << 30) | ||
| 85 | #define ASSABET_BSR_RAD_RI (1 << 31) | ||
| 86 | |||
| 87 | |||
| 88 | /* GPIOs for which the generic definition doesn't say much */ | ||
| 89 | #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ | ||
| 90 | #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ | ||
| 91 | #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ | ||
| 92 | #define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ | ||
| 93 | #define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ | ||
| 94 | #define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ | ||
| 95 | #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ | ||
| 96 | #define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ | ||
| 97 | #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ | ||
| 98 | #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ | ||
| 99 | |||
| 100 | #define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 | ||
| 101 | #define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 | ||
| 102 | #define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 | ||
| 103 | #define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 | ||
| 104 | |||
| 105 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/badge4.h b/arch/arm/mach-sa1100/include/mach/badge4.h new file mode 100644 index 000000000000..44d2e1bfc04b --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/badge4.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/badge4.h | ||
| 3 | * | ||
| 4 | * Tim Connors <connors@hpl.hp.com> | ||
| 5 | * Christopher Hoover <ch@hpl.hp.com> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2002 Hewlett-Packard Company | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 16 | #error "include <mach/hardware.h> instead" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define BADGE4_SA1111_BASE (0x48000000) | ||
| 20 | |||
| 21 | /* GPIOs on the BadgePAD 4 */ | ||
| 22 | #define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */ | ||
| 23 | |||
| 24 | #define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */ | ||
| 25 | #define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */ | ||
| 26 | #define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */ | ||
| 27 | #define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */ | ||
| 28 | #define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */ | ||
| 29 | #define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */ | ||
| 30 | #define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */ | ||
| 31 | #define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */ | ||
| 32 | #define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */ | ||
| 33 | #define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */ | ||
| 34 | #define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */ | ||
| 35 | #define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */ | ||
| 36 | |||
| 37 | #define BADGE4_GPIO_UART_HS1 GPIO_GPIO13 | ||
| 38 | #define BADGE4_GPIO_UART_HS2 GPIO_GPIO14 | ||
| 39 | |||
| 40 | #define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15 | ||
| 41 | #define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16 | ||
| 42 | |||
| 43 | #define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */ | ||
| 44 | #define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */ | ||
| 45 | #define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */ | ||
| 46 | #define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */ | ||
| 47 | |||
| 48 | #define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */ | ||
| 49 | #define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */ | ||
| 50 | |||
| 51 | #define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23 | ||
| 52 | |||
| 53 | #define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */ | ||
| 54 | |||
| 55 | #define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */ | ||
| 56 | |||
| 57 | #define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26 | ||
| 58 | |||
| 59 | #define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */ | ||
| 60 | |||
| 61 | /* Interrupts on the BadgePAD 4 */ | ||
| 62 | #define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */ | ||
| 63 | |||
| 64 | |||
| 65 | /* PCM5ENV Usage tracking */ | ||
| 66 | |||
| 67 | #define BADGE4_5V_PCMCIA_SOCK0 (1<<0) | ||
| 68 | #define BADGE4_5V_PCMCIA_SOCK1 (1<<1) | ||
| 69 | #define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n)) | ||
| 70 | #define BADGE4_5V_USB (1<<2) | ||
| 71 | #define BADGE4_5V_INITIALLY (1<<3) | ||
| 72 | |||
| 73 | #ifndef __ASSEMBLY__ | ||
| 74 | extern void badge4_set_5V(unsigned subsystem, int on); | ||
| 75 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/bitfield.h b/arch/arm/mach-sa1100/include/mach/bitfield.h new file mode 100644 index 000000000000..f1f0e3387d9c --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/bitfield.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | * FILE bitfield.h | ||
| 3 | * | ||
| 4 | * Version 1.1 | ||
| 5 | * Author Copyright (c) Marc A. Viredaz, 1998 | ||
| 6 | * DEC Western Research Laboratory, Palo Alto, CA | ||
| 7 | * Date April 1998 (April 1997) | ||
| 8 | * System Advanced RISC Machine (ARM) | ||
| 9 | * Language C or ARM Assembly | ||
| 10 | * Purpose Definition of macros to operate on bit fields. | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | #ifndef __BITFIELD_H | ||
| 16 | #define __BITFIELD_H | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #define UData(Data) ((unsigned long) (Data)) | ||
| 20 | #else | ||
| 21 | #define UData(Data) (Data) | ||
| 22 | #endif | ||
| 23 | |||
| 24 | |||
| 25 | /* | ||
| 26 | * MACRO: Fld | ||
| 27 | * | ||
| 28 | * Purpose | ||
| 29 | * The macro "Fld" encodes a bit field, given its size and its shift value | ||
| 30 | * with respect to bit 0. | ||
| 31 | * | ||
| 32 | * Note | ||
| 33 | * A more intuitive way to encode bit fields would have been to use their | ||
| 34 | * mask. However, extracting size and shift value information from a bit | ||
| 35 | * field's mask is cumbersome and might break the assembler (255-character | ||
| 36 | * line-size limit). | ||
| 37 | * | ||
| 38 | * Input | ||
| 39 | * Size Size of the bit field, in number of bits. | ||
| 40 | * Shft Shift value of the bit field with respect to bit 0. | ||
| 41 | * | ||
| 42 | * Output | ||
| 43 | * Fld Encoded bit field. | ||
| 44 | */ | ||
| 45 | |||
| 46 | #define Fld(Size, Shft) (((Size) << 16) + (Shft)) | ||
| 47 | |||
| 48 | |||
| 49 | /* | ||
| 50 | * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit | ||
| 51 | * | ||
| 52 | * Purpose | ||
| 53 | * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return | ||
| 54 | * the size, shift value, mask, aligned mask, and first bit of a | ||
| 55 | * bit field. | ||
| 56 | * | ||
| 57 | * Input | ||
| 58 | * Field Encoded bit field (using the macro "Fld"). | ||
| 59 | * | ||
| 60 | * Output | ||
| 61 | * FSize Size of the bit field, in number of bits. | ||
| 62 | * FShft Shift value of the bit field with respect to bit 0. | ||
| 63 | * FMsk Mask for the bit field. | ||
| 64 | * FAlnMsk Mask for the bit field, aligned on bit 0. | ||
| 65 | * F1stBit First bit of the bit field. | ||
| 66 | */ | ||
| 67 | |||
| 68 | #define FSize(Field) ((Field) >> 16) | ||
| 69 | #define FShft(Field) ((Field) & 0x0000FFFF) | ||
| 70 | #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) | ||
| 71 | #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) | ||
| 72 | #define F1stBit(Field) (UData (1) << FShft (Field)) | ||
| 73 | |||
| 74 | |||
| 75 | /* | ||
| 76 | * MACRO: FInsrt | ||
| 77 | * | ||
| 78 | * Purpose | ||
| 79 | * The macro "FInsrt" inserts a value into a bit field by shifting the | ||
| 80 | * former appropriately. | ||
| 81 | * | ||
| 82 | * Input | ||
| 83 | * Value Bit-field value. | ||
| 84 | * Field Encoded bit field (using the macro "Fld"). | ||
| 85 | * | ||
| 86 | * Output | ||
| 87 | * FInsrt Bit-field value positioned appropriately. | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define FInsrt(Value, Field) \ | ||
| 91 | (UData (Value) << FShft (Field)) | ||
| 92 | |||
| 93 | |||
| 94 | /* | ||
| 95 | * MACRO: FExtr | ||
| 96 | * | ||
| 97 | * Purpose | ||
| 98 | * The macro "FExtr" extracts the value of a bit field by masking and | ||
| 99 | * shifting it appropriately. | ||
| 100 | * | ||
| 101 | * Input | ||
| 102 | * Data Data containing the bit-field to be extracted. | ||
| 103 | * Field Encoded bit field (using the macro "Fld"). | ||
| 104 | * | ||
| 105 | * Output | ||
| 106 | * FExtr Bit-field value. | ||
| 107 | */ | ||
| 108 | |||
| 109 | #define FExtr(Data, Field) \ | ||
| 110 | ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) | ||
| 111 | |||
| 112 | |||
| 113 | #endif /* __BITFIELD_H */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h new file mode 100644 index 000000000000..c3ac3d0f9465 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/cerf.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/cerf.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * Apr-2003 : Removed some old PDA crud [FB] | ||
| 9 | */ | ||
| 10 | #ifndef _INCLUDE_CERF_H_ | ||
| 11 | #define _INCLUDE_CERF_H_ | ||
| 12 | |||
| 13 | |||
| 14 | #define CERF_ETH_IO 0xf0000000 | ||
| 15 | #define CERF_ETH_IRQ IRQ_GPIO26 | ||
| 16 | |||
| 17 | #define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) | ||
| 18 | #define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) | ||
| 19 | #define CERF_GPIO_CF_RESET GPIO_GPIO (21) | ||
| 20 | #define CERF_GPIO_CF_IRQ GPIO_GPIO (22) | ||
| 21 | #define CERF_GPIO_CF_CD GPIO_GPIO (23) | ||
| 22 | |||
| 23 | #define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19 | ||
| 24 | #define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20 | ||
| 25 | #define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22 | ||
| 26 | #define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23 | ||
| 27 | |||
| 28 | #endif // _INCLUDE_CERF_H_ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h new file mode 100644 index 000000000000..69e962416e3f --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/collie.h | |||
| @@ -0,0 +1,88 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/collie.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware specific definitions for Assabet | ||
| 5 | * Only include this file from SA1100-specific files. | ||
| 6 | * | ||
| 7 | * ChangeLog: | ||
| 8 | * 04-06-2001 Lineo Japan, Inc. | ||
| 9 | * 04-16-2001 SHARP Corporation | ||
| 10 | * 07-07-2002 Chris Larson <clarson@digi.com> | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARCH_COLLIE_H | ||
| 14 | #define __ASM_ARCH_COLLIE_H | ||
| 15 | |||
| 16 | |||
| 17 | #define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 | ||
| 18 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 | ||
| 19 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 | ||
| 20 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 | ||
| 21 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 | ||
| 22 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 | ||
| 23 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 | ||
| 24 | #define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 | ||
| 25 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 | ||
| 26 | |||
| 27 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ | ||
| 28 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ | ||
| 29 | COLLIE_SCP_LB_VOL_CHG ) | ||
| 30 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ | ||
| 31 | COLLIE_SCP_CHARGE_ON ) | ||
| 32 | |||
| 33 | /* GPIOs for which the generic definition doesn't say much */ | ||
| 34 | |||
| 35 | #define COLLIE_GPIO_ON_KEY GPIO_GPIO (0) | ||
| 36 | #define COLLIE_GPIO_AC_IN GPIO_GPIO (1) | ||
| 37 | #define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11) | ||
| 38 | #define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14) | ||
| 39 | #define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15) | ||
| 40 | #define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16) | ||
| 41 | #define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17) | ||
| 42 | #define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18) | ||
| 43 | #define COLLIE_GPIO_CO GPIO_GPIO (20) | ||
| 44 | #define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21) | ||
| 45 | #define COLLIE_GPIO_CF_CD GPIO_GPIO (22) | ||
| 46 | #define COLLIE_GPIO_UCB1x00_IRQ GPIO_GPIO (23) | ||
| 47 | #define COLLIE_GPIO_WAKEUP GPIO_GPIO (24) | ||
| 48 | #define COLLIE_GPIO_GA_INT GPIO_GPIO (25) | ||
| 49 | #define COLLIE_GPIO_MAIN_BAT_LOW GPIO_GPIO (26) | ||
| 50 | |||
| 51 | /* Interrupts */ | ||
| 52 | |||
| 53 | #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 | ||
| 54 | #define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1 | ||
| 55 | #define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11 | ||
| 56 | #define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14 | ||
| 57 | #define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15 | ||
| 58 | #define COLLIE_IRQ_GPIO_CO IRQ_GPIO20 | ||
| 59 | #define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22 | ||
| 60 | #define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23 | ||
| 61 | #define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24 | ||
| 62 | #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 | ||
| 63 | #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 | ||
| 64 | |||
| 65 | #define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0 | ||
| 66 | #define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1 | ||
| 67 | #define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2 | ||
| 68 | #define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3 | ||
| 69 | #define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 | ||
| 70 | #define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 | ||
| 71 | |||
| 72 | /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ | ||
| 73 | #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */ | ||
| 74 | #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */ | ||
| 75 | #define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 /* GPIO2=VPNE_ON */ | ||
| 76 | #define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 /* GPIO3=IR_ON */ | ||
| 77 | #define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 /* GPIO4=AMP_ON */ | ||
| 78 | #define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 /* GPIO5=Version */ | ||
| 79 | #define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 /* GPIO5=fs 8k LPF */ | ||
| 80 | #define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 /* GPIO6=BUZZER BIAS */ | ||
| 81 | #define COLLIE_TC35143_GPIO_MBAT_ON UCB_IO_7 /* GPIO7=MBAT_ON */ | ||
| 82 | #define COLLIE_TC35143_GPIO_BBAT_ON UCB_IO_8 /* GPIO8=BBAT_ON */ | ||
| 83 | #define COLLIE_TC35143_GPIO_TMP_ON UCB_IO_9 /* GPIO9=TMP_ON */ | ||
| 84 | #define COLLIE_TC35143_GPIO_IN ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 ) | ||
| 85 | #define COLLIE_TC35143_GPIO_OUT ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \ | ||
| 86 | UCB_IO_7 | UCB_IO_8 | UCB_IO_9 ) | ||
| 87 | |||
| 88 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S new file mode 100644 index 000000000000..1f0634d92702 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* arch/arm/mach-sa1100/include/mach/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #include <mach/hardware.h> | ||
| 14 | |||
| 15 | .macro addruart,rx | ||
| 16 | mrc p15, 0, \rx, c1, c0 | ||
| 17 | tst \rx, #1 @ MMU enabled? | ||
| 18 | moveq \rx, #0x80000000 @ physical base address | ||
| 19 | movne \rx, #0xf8000000 @ virtual address | ||
| 20 | |||
| 21 | @ We probe for the active serial port here, coherently with | ||
| 22 | @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. | ||
| 23 | @ We assume r1 can be clobbered. | ||
| 24 | |||
| 25 | @ see if Ser3 is active | ||
| 26 | add \rx, \rx, #0x00050000 | ||
| 27 | ldr r1, [\rx, #UTCR3] | ||
| 28 | tst r1, #UTCR3_TXE | ||
| 29 | |||
| 30 | @ if Ser3 is inactive, then try Ser1 | ||
| 31 | addeq \rx, \rx, #(0x00010000 - 0x00050000) | ||
| 32 | ldreq r1, [\rx, #UTCR3] | ||
| 33 | tsteq r1, #UTCR3_TXE | ||
| 34 | |||
| 35 | @ if Ser1 is inactive, then try Ser2 | ||
| 36 | addeq \rx, \rx, #(0x00030000 - 0x00010000) | ||
| 37 | ldreq r1, [\rx, #UTCR3] | ||
| 38 | tsteq r1, #UTCR3_TXE | ||
| 39 | |||
| 40 | @ if all ports are inactive, then there is nothing we can do | ||
| 41 | moveq pc, lr | ||
| 42 | .endm | ||
| 43 | |||
| 44 | .macro senduart,rd,rx | ||
| 45 | str \rd, [\rx, #UTDR] | ||
| 46 | .endm | ||
| 47 | |||
| 48 | .macro waituart,rd,rx | ||
| 49 | 1001: ldr \rd, [\rx, #UTSR1] | ||
| 50 | tst \rd, #UTSR1_TNF | ||
| 51 | beq 1001b | ||
| 52 | .endm | ||
| 53 | |||
| 54 | .macro busyuart,rd,rx | ||
| 55 | 1001: ldr \rd, [\rx, #UTSR1] | ||
| 56 | tst \rd, #UTSR1_TBY | ||
| 57 | bne 1001b | ||
| 58 | .endm | ||
diff --git a/arch/arm/mach-sa1100/include/mach/dma.h b/arch/arm/mach-sa1100/include/mach/dma.h new file mode 100644 index 000000000000..dda1b351310d --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/dma.h | |||
| @@ -0,0 +1,117 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/dma.h | ||
| 3 | * | ||
| 4 | * Generic SA1100 DMA support | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Nicolas Pitre | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_DMA_H | ||
| 11 | #define __ASM_ARCH_DMA_H | ||
| 12 | |||
| 13 | #include "hardware.h" | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * The SA1100 has six internal DMA channels. | ||
| 18 | */ | ||
| 19 | #define SA1100_DMA_CHANNELS 6 | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Maximum physical DMA buffer size | ||
| 23 | */ | ||
| 24 | #define MAX_DMA_SIZE 0x1fff | ||
| 25 | #define CUT_DMA_SIZE 0x1000 | ||
| 26 | |||
| 27 | /* | ||
| 28 | * All possible SA1100 devices a DMA channel can be attached to. | ||
| 29 | */ | ||
| 30 | typedef enum { | ||
| 31 | DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ | ||
| 32 | DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ | ||
| 33 | DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ | ||
| 34 | DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ | ||
| 35 | DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ | ||
| 36 | DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ | ||
| 37 | DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ | ||
| 38 | DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ | ||
| 39 | DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ | ||
| 40 | DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ | ||
| 41 | DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ | ||
| 42 | DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ | ||
| 43 | DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ | ||
| 44 | DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ | ||
| 45 | DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ | ||
| 46 | DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ | ||
| 47 | DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ | ||
| 48 | DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ | ||
| 49 | } dma_device_t; | ||
| 50 | |||
| 51 | typedef struct { | ||
| 52 | volatile u_long DDAR; | ||
| 53 | volatile u_long SetDCSR; | ||
| 54 | volatile u_long ClrDCSR; | ||
| 55 | volatile u_long RdDCSR; | ||
| 56 | volatile dma_addr_t DBSA; | ||
| 57 | volatile u_long DBTA; | ||
| 58 | volatile dma_addr_t DBSB; | ||
| 59 | volatile u_long DBTB; | ||
| 60 | } dma_regs_t; | ||
| 61 | |||
| 62 | typedef void (*dma_callback_t)(void *data); | ||
| 63 | |||
| 64 | /* | ||
| 65 | * DMA function prototypes | ||
| 66 | */ | ||
| 67 | |||
| 68 | extern int sa1100_request_dma( dma_device_t device, const char *device_id, | ||
| 69 | dma_callback_t callback, void *data, | ||
| 70 | dma_regs_t **regs ); | ||
| 71 | extern void sa1100_free_dma( dma_regs_t *regs ); | ||
| 72 | extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); | ||
| 73 | extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); | ||
| 74 | extern void sa1100_reset_dma(dma_regs_t *regs); | ||
| 75 | |||
| 76 | /** | ||
| 77 | * sa1100_stop_dma - stop DMA in progress | ||
| 78 | * @regs: identifier for the channel to use | ||
| 79 | * | ||
| 80 | * This stops DMA without clearing buffer pointers. Unlike | ||
| 81 | * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() | ||
| 82 | * or sa1100_get_dma_pos(). | ||
| 83 | * | ||
| 84 | * The @regs identifier is provided by a successful call to | ||
| 85 | * sa1100_request_dma(). | ||
| 86 | **/ | ||
| 87 | |||
| 88 | #define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) | ||
| 89 | |||
| 90 | /** | ||
| 91 | * sa1100_resume_dma - resume DMA on a stopped channel | ||
| 92 | * @regs: identifier for the channel to use | ||
| 93 | * | ||
| 94 | * This resumes DMA on a channel previously stopped with | ||
| 95 | * sa1100_stop_dma(). | ||
| 96 | * | ||
| 97 | * The @regs identifier is provided by a successful call to | ||
| 98 | * sa1100_request_dma(). | ||
| 99 | **/ | ||
| 100 | |||
| 101 | #define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) | ||
| 102 | |||
| 103 | /** | ||
| 104 | * sa1100_clear_dma - clear DMA pointers | ||
| 105 | * @regs: identifier for the channel to use | ||
| 106 | * | ||
| 107 | * This clear any DMA state so the DMA engine is ready to restart | ||
| 108 | * with new buffers through sa1100_start_dma(). Any buffers in flight | ||
| 109 | * are discarded. | ||
| 110 | * | ||
| 111 | * The @regs identifier is provided by a successful call to | ||
| 112 | * sa1100_request_dma(). | ||
| 113 | **/ | ||
| 114 | |||
| 115 | #define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) | ||
| 116 | |||
| 117 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S new file mode 100644 index 000000000000..6aa13c46c5d3 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for SA1100-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | .macro disable_fiq | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | mov \base, #0xfa000000 @ ICIP = 0xfa050000 | ||
| 16 | add \base, \base, #0x00050000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 23 | ldr \irqstat, [\base] @ get irqs | ||
| 24 | ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 | ||
| 25 | ands \irqstat, \irqstat, \irqnr | ||
| 26 | mov \irqnr, #0 | ||
| 27 | beq 1001f | ||
| 28 | tst \irqstat, #0xff | ||
| 29 | moveq \irqstat, \irqstat, lsr #8 | ||
| 30 | addeq \irqnr, \irqnr, #8 | ||
| 31 | tsteq \irqstat, #0xff | ||
| 32 | moveq \irqstat, \irqstat, lsr #8 | ||
| 33 | addeq \irqnr, \irqnr, #8 | ||
| 34 | tsteq \irqstat, #0xff | ||
| 35 | moveq \irqstat, \irqstat, lsr #8 | ||
| 36 | addeq \irqnr, \irqnr, #8 | ||
| 37 | tst \irqstat, #0x0f | ||
| 38 | moveq \irqstat, \irqstat, lsr #4 | ||
| 39 | addeq \irqnr, \irqnr, #4 | ||
| 40 | tst \irqstat, #0x03 | ||
| 41 | moveq \irqstat, \irqstat, lsr #2 | ||
| 42 | addeq \irqnr, \irqnr, #2 | ||
| 43 | tst \irqstat, #0x01 | ||
| 44 | addeqs \irqnr, \irqnr, #1 | ||
| 45 | 1001: | ||
| 46 | .endm | ||
| 47 | |||
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h new file mode 100644 index 000000000000..582a0c92da53 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/gpio.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/gpio.h | ||
| 3 | * | ||
| 4 | * SA1100 GPIO wrappers for arch-neutral GPIO calls | ||
| 5 | * | ||
| 6 | * Written by Philipp Zabel <philipp.zabel@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_ARCH_SA1100_GPIO_H | ||
| 25 | #define __ASM_ARCH_SA1100_GPIO_H | ||
| 26 | |||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <asm/irq.h> | ||
| 29 | #include <asm-generic/gpio.h> | ||
| 30 | |||
| 31 | static inline int gpio_get_value(unsigned gpio) | ||
| 32 | { | ||
| 33 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) | ||
| 34 | return GPLR & GPIO_GPIO(gpio); | ||
| 35 | else | ||
| 36 | return __gpio_get_value(gpio); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 40 | { | ||
| 41 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) | ||
| 42 | if (value) | ||
| 43 | GPSR = GPIO_GPIO(gpio); | ||
| 44 | else | ||
| 45 | GPCR = GPIO_GPIO(gpio); | ||
| 46 | else | ||
| 47 | __gpio_set_value(gpio, value); | ||
| 48 | } | ||
| 49 | |||
| 50 | #define gpio_cansleep __gpio_cansleep | ||
| 51 | |||
| 52 | static inline unsigned gpio_to_irq(unsigned gpio) | ||
| 53 | { | ||
| 54 | if (gpio < 11) | ||
| 55 | return IRQ_GPIO0 + gpio; | ||
| 56 | else | ||
| 57 | return IRQ_GPIO11 - 11 + gpio; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline unsigned irq_to_gpio(unsigned irq) | ||
| 61 | { | ||
| 62 | if (irq < IRQ_GPIO11_27) | ||
| 63 | return irq - IRQ_GPIO0; | ||
| 64 | else | ||
| 65 | return irq - IRQ_GPIO11 + 11; | ||
| 66 | } | ||
| 67 | |||
| 68 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h new file mode 100644 index 000000000000..3ca0ecf095e6 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/h3600.h | |||
| @@ -0,0 +1,169 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Definitions for H3600 Handheld Computer | ||
| 4 | * | ||
| 5 | * Copyright 2000 Compaq Computer Corporation. | ||
| 6 | * | ||
| 7 | * Use consistent with the GNU GPL is permitted, | ||
| 8 | * provided that this copyright notice is | ||
| 9 | * preserved in its entirety in all copies and derived works. | ||
| 10 | * | ||
| 11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
| 12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
| 13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
| 14 | * | ||
| 15 | * Author: Jamey Hicks. | ||
| 16 | * | ||
| 17 | * History: | ||
| 18 | * | ||
| 19 | * 2001-10-?? Andrew Christian Added support for iPAQ H3800 | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _INCLUDE_H3600_H_ | ||
| 24 | #define _INCLUDE_H3600_H_ | ||
| 25 | |||
| 26 | typedef int __bitwise pm_request_t; | ||
| 27 | |||
| 28 | #define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */ | ||
| 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ | ||
| 30 | |||
| 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ | ||
| 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) | ||
| 33 | |||
| 34 | /* Physical memory regions corresponding to chip selects */ | ||
| 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) | ||
| 36 | #define H3600_BANK_2_PHYS SA1100_CS2_PHYS | ||
| 37 | #define H3600_BANK_4_PHYS SA1100_CS4_PHYS | ||
| 38 | |||
| 39 | /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ | ||
| 40 | #define H3600_EGPIO_VIRT 0xf0000000 | ||
| 41 | #define H3600_BANK_2_VIRT 0xf1000000 | ||
| 42 | #define H3600_BANK_4_VIRT 0xf3800000 | ||
| 43 | |||
| 44 | /* | ||
| 45 | Machine-independent GPIO definitions | ||
| 46 | --- these are common across all current iPAQ platforms | ||
| 47 | */ | ||
| 48 | |||
| 49 | #define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) /* Also known as the "off button" */ | ||
| 50 | |||
| 51 | #define GPIO_H3600_PCMCIA_CD1 GPIO_GPIO (10) | ||
| 52 | #define GPIO_H3600_PCMCIA_IRQ1 GPIO_GPIO (11) | ||
| 53 | |||
| 54 | /* UDA1341 L3 Interface */ | ||
| 55 | #define GPIO_H3600_L3_DATA GPIO_GPIO (14) | ||
| 56 | #define GPIO_H3600_L3_MODE GPIO_GPIO (15) | ||
| 57 | #define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) | ||
| 58 | |||
| 59 | #define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) | ||
| 60 | #define GPIO_H3600_SYS_CLK GPIO_GPIO (19) | ||
| 61 | #define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) | ||
| 62 | |||
| 63 | #define GPIO_H3600_COM_DCD GPIO_GPIO (23) | ||
| 64 | #define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) | ||
| 65 | #define GPIO_H3600_COM_CTS GPIO_GPIO (25) | ||
| 66 | #define GPIO_H3600_COM_RTS GPIO_GPIO (26) | ||
| 67 | |||
| 68 | #define IRQ_GPIO_H3600_NPOWER_BUTTON IRQ_GPIO0 | ||
| 69 | #define IRQ_GPIO_H3600_PCMCIA_CD1 IRQ_GPIO10 | ||
| 70 | #define IRQ_GPIO_H3600_PCMCIA_IRQ1 IRQ_GPIO11 | ||
| 71 | #define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 | ||
| 72 | #define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 | ||
| 73 | #define IRQ_GPIO_H3600_COM_DCD IRQ_GPIO23 | ||
| 74 | #define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 | ||
| 75 | #define IRQ_GPIO_H3600_COM_CTS IRQ_GPIO25 | ||
| 76 | |||
| 77 | |||
| 78 | #ifndef __ASSEMBLY__ | ||
| 79 | |||
| 80 | enum ipaq_egpio_type { | ||
| 81 | IPAQ_EGPIO_LCD_POWER, /* Power to the LCD panel */ | ||
| 82 | IPAQ_EGPIO_CODEC_NRESET, /* Clear to reset the audio codec (remember to return high) */ | ||
| 83 | IPAQ_EGPIO_AUDIO_ON, /* Audio power */ | ||
| 84 | IPAQ_EGPIO_QMUTE, /* Audio muting */ | ||
| 85 | IPAQ_EGPIO_OPT_NVRAM_ON, /* Non-volatile RAM on extension sleeves (SPI interface) */ | ||
| 86 | IPAQ_EGPIO_OPT_ON, /* Power to extension sleeves */ | ||
| 87 | IPAQ_EGPIO_CARD_RESET, /* Reset PCMCIA cards on extension sleeve (???) */ | ||
| 88 | IPAQ_EGPIO_OPT_RESET, /* Reset option pack (???) */ | ||
| 89 | IPAQ_EGPIO_IR_ON, /* IR sensor/emitter power */ | ||
| 90 | IPAQ_EGPIO_IR_FSEL, /* IR speed selection 1->fast, 0->slow */ | ||
| 91 | IPAQ_EGPIO_RS232_ON, /* Maxim RS232 chip power */ | ||
| 92 | IPAQ_EGPIO_VPP_ON, /* Turn on power to flash programming */ | ||
| 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ | ||
| 94 | }; | ||
| 95 | |||
| 96 | struct ipaq_model_ops { | ||
| 97 | const char *generic_name; | ||
| 98 | void (*control)(enum ipaq_egpio_type, int); | ||
| 99 | unsigned long (*read)(void); | ||
| 100 | void (*blank_callback)(int blank); | ||
| 101 | int (*pm_callback)(int req); /* Primary model callback */ | ||
| 102 | int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ | ||
| 103 | }; | ||
| 104 | |||
| 105 | extern struct ipaq_model_ops ipaq_model_ops; | ||
| 106 | |||
| 107 | static __inline__ const char * h3600_generic_name(void) | ||
| 108 | { | ||
| 109 | return ipaq_model_ops.generic_name; | ||
| 110 | } | ||
| 111 | |||
| 112 | static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) | ||
| 113 | { | ||
| 114 | if (ipaq_model_ops.control) | ||
| 115 | ipaq_model_ops.control(x,level); | ||
| 116 | } | ||
| 117 | |||
| 118 | static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) | ||
| 119 | { | ||
| 120 | if (ipaq_model_ops.control) | ||
| 121 | ipaq_model_ops.control(x,0); | ||
| 122 | } | ||
| 123 | |||
| 124 | static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) | ||
| 125 | { | ||
| 126 | if (ipaq_model_ops.control) | ||
| 127 | ipaq_model_ops.control(x,1); | ||
| 128 | } | ||
| 129 | |||
| 130 | static __inline__ unsigned long read_h3600_egpio(void) | ||
| 131 | { | ||
| 132 | if (ipaq_model_ops.read) | ||
| 133 | return ipaq_model_ops.read(); | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static __inline__ int h3600_register_blank_callback(void (*f)(int)) | ||
| 138 | { | ||
| 139 | ipaq_model_ops.blank_callback = f; | ||
| 140 | return 0; | ||
| 141 | } | ||
| 142 | |||
| 143 | static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) | ||
| 144 | { | ||
| 145 | ipaq_model_ops.blank_callback = NULL; | ||
| 146 | } | ||
| 147 | |||
| 148 | |||
| 149 | static __inline__ int h3600_register_pm_callback(int (*f)(int)) | ||
| 150 | { | ||
| 151 | ipaq_model_ops.pm_callback_aux = f; | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) | ||
| 156 | { | ||
| 157 | ipaq_model_ops.pm_callback_aux = NULL; | ||
| 158 | } | ||
| 159 | |||
| 160 | static __inline__ int h3600_power_management(int req) | ||
| 161 | { | ||
| 162 | if (ipaq_model_ops.pm_callback) | ||
| 163 | return ipaq_model_ops.pm_callback(req); | ||
| 164 | return 0; | ||
| 165 | } | ||
| 166 | |||
| 167 | #endif /* ASSEMBLY */ | ||
| 168 | |||
| 169 | #endif /* _INCLUDE_H3600_H_ */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h new file mode 100644 index 000000000000..62b0b7879685 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h | |||
| @@ -0,0 +1,540 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Definitions for H3600 Handheld Computer | ||
| 4 | * | ||
| 5 | * Copyright 2000 Compaq Computer Corporation. | ||
| 6 | * | ||
| 7 | * Use consistent with the GNU GPL is permitted, | ||
| 8 | * provided that this copyright notice is | ||
| 9 | * preserved in its entirety in all copies and derived works. | ||
| 10 | * | ||
| 11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
| 12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
| 13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
| 14 | * | ||
| 15 | * Author: Jamey Hicks. | ||
| 16 | * | ||
| 17 | * History: | ||
| 18 | * | ||
| 19 | * 2001-10-?? Andrew Christian Added support for iPAQ H3800 | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _INCLUDE_H3600_GPIO_H_ | ||
| 24 | #define _INCLUDE_H3600_GPIO_H_ | ||
| 25 | |||
| 26 | /* | ||
| 27 | * GPIO lines that are common across ALL iPAQ models are in "h3600.h" | ||
| 28 | * This file contains machine-specific definitions | ||
| 29 | */ | ||
| 30 | |||
| 31 | #define GPIO_H3600_SUSPEND GPIO_GPIO (0) | ||
| 32 | /* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */ | ||
| 33 | #define GPIO_H3100_BT_ON GPIO_GPIO (2) | ||
| 34 | #define GPIO_H3100_GPIO3 GPIO_GPIO (3) | ||
| 35 | #define GPIO_H3100_QMUTE GPIO_GPIO (4) | ||
| 36 | #define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5) | ||
| 37 | #define GPIO_H3100_AUD_ON GPIO_GPIO (6) | ||
| 38 | #define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7) | ||
| 39 | #define GPIO_H3100_IR_ON GPIO_GPIO (8) | ||
| 40 | #define GPIO_H3100_IR_FSEL GPIO_GPIO (9) | ||
| 41 | |||
| 42 | /* for H3600, audio sample rate clock generator */ | ||
| 43 | #define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) | ||
| 44 | #define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) | ||
| 45 | |||
| 46 | #define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) | ||
| 47 | #define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */ | ||
| 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) | ||
| 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) | ||
| 50 | |||
| 51 | /* H3800 specific pins */ | ||
| 52 | #define GPIO_H3800_AC_IN GPIO_GPIO (12) | ||
| 53 | #define GPIO_H3800_COM_DSR GPIO_GPIO (13) | ||
| 54 | #define GPIO_H3800_MMC_INT GPIO_GPIO (18) | ||
| 55 | #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ | ||
| 56 | #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) | ||
| 57 | #define GPIO_H3800_CLK_OUT GPIO_GPIO (27) | ||
| 58 | |||
| 59 | /****************************************************/ | ||
| 60 | |||
| 61 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 | ||
| 62 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 | ||
| 63 | |||
| 64 | #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 | ||
| 65 | #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ | ||
| 66 | |||
| 67 | /* H3100 / 3600 EGPIO pins */ | ||
| 68 | #define EGPIO_H3600_VPP_ON (1 << 0) | ||
| 69 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ | ||
| 70 | #define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ | ||
| 71 | #define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ | ||
| 72 | #define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ | ||
| 73 | #define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ | ||
| 74 | #define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ | ||
| 75 | #define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ | ||
| 76 | |||
| 77 | /* H3600 only EGPIO pins */ | ||
| 78 | #define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ | ||
| 79 | #define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ | ||
| 80 | #define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ | ||
| 81 | #define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */ | ||
| 82 | #define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ | ||
| 83 | #define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ | ||
| 84 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ | ||
| 85 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ | ||
| 86 | |||
| 87 | /********************* H3800, ASIC #2 ********************/ | ||
| 88 | |||
| 89 | #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) | ||
| 90 | #define H3800_ASIC2_OFFSET(s,x,y) \ | ||
| 91 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 92 | #define H3800_ASIC2_NOFFSET(s,x,n,y) \ | ||
| 93 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 94 | |||
| 95 | #define _H3800_ASIC2_GPIO_Base 0x0000 | ||
| 96 | #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ | ||
| 97 | #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 98 | #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 99 | #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 100 | #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ | ||
| 101 | #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ | ||
| 102 | #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 103 | #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 104 | #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ | ||
| 105 | #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ | ||
| 106 | |||
| 107 | #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) | ||
| 108 | #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) | ||
| 109 | #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) | ||
| 110 | #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) | ||
| 111 | #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) | ||
| 112 | #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) | ||
| 113 | #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) | ||
| 114 | #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 115 | #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) | ||
| 116 | #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) | ||
| 117 | |||
| 118 | #define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ | ||
| 119 | #define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ | ||
| 120 | #define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ | ||
| 121 | #define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ | ||
| 122 | #define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ | ||
| 123 | #define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ | ||
| 124 | #define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ | ||
| 125 | #define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ | ||
| 126 | #define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ | ||
| 127 | #define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ | ||
| 128 | #define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ | ||
| 129 | #define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ | ||
| 130 | |||
| 131 | #define _H3800_ASIC2_KPIO_Base 0x0200 | ||
| 132 | #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ | ||
| 133 | #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 134 | #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 135 | #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 136 | #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ | ||
| 137 | #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ | ||
| 138 | #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 139 | #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 140 | #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ | ||
| 141 | #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ | ||
| 142 | |||
| 143 | #define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) | ||
| 144 | #define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) | ||
| 145 | #define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) | ||
| 146 | #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) | ||
| 147 | #define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) | ||
| 148 | #define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) | ||
| 149 | #define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) | ||
| 150 | #define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) | ||
| 151 | #define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) | ||
| 152 | #define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) | ||
| 153 | |||
| 154 | #define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) | ||
| 155 | #define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) | ||
| 156 | #define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) | ||
| 157 | #define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) | ||
| 158 | #define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) | ||
| 159 | #define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) | ||
| 160 | #define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) | ||
| 161 | #define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) | ||
| 162 | |||
| 163 | #define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ | ||
| 164 | #define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ | ||
| 165 | #define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ | ||
| 166 | #define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ | ||
| 167 | #define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ | ||
| 168 | #define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ | ||
| 169 | #define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ | ||
| 170 | #define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ | ||
| 171 | #define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ | ||
| 172 | #define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ | ||
| 173 | #define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ | ||
| 174 | #define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ | ||
| 175 | |||
| 176 | /* Alternate KPIO functions (set by default) */ | ||
| 177 | #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ | ||
| 178 | #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ | ||
| 179 | #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ | ||
| 180 | #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ | ||
| 181 | #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ | ||
| 182 | |||
| 183 | #define _H3800_ASIC2_SPI_Base 0x0400 | ||
| 184 | #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ | ||
| 185 | #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ | ||
| 186 | #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ | ||
| 187 | |||
| 188 | #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) | ||
| 189 | #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) | ||
| 190 | #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) | ||
| 191 | |||
| 192 | #define _H3800_ASIC2_PWM_0_Base 0x0600 | ||
| 193 | #define _H3800_ASIC2_PWM_1_Base 0x0700 | ||
| 194 | #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ | ||
| 195 | #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 196 | #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 197 | |||
| 198 | #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) | ||
| 199 | #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) | ||
| 200 | #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) | ||
| 201 | |||
| 202 | #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) | ||
| 203 | #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) | ||
| 204 | #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) | ||
| 205 | |||
| 206 | #define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ | ||
| 207 | #define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ | ||
| 208 | #define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ | ||
| 209 | |||
| 210 | #define _H3800_ASIC2_LED_0_Base 0x0800 | ||
| 211 | #define _H3800_ASIC2_LED_1_Base 0x0880 | ||
| 212 | #define _H3800_ASIC2_LED_2_Base 0x0900 | ||
| 213 | #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ | ||
| 214 | #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 215 | #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 216 | #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ | ||
| 217 | |||
| 218 | #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) | ||
| 219 | #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) | ||
| 220 | #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) | ||
| 221 | #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) | ||
| 222 | |||
| 223 | #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) | ||
| 224 | #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) | ||
| 225 | #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) | ||
| 226 | #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) | ||
| 227 | |||
| 228 | #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) | ||
| 229 | #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) | ||
| 230 | #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) | ||
| 231 | #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) | ||
| 232 | |||
| 233 | #define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ | ||
| 234 | #define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ | ||
| 235 | #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) | ||
| 236 | #define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ | ||
| 237 | |||
| 238 | #define _H3800_ASIC2_UART_0_Base 0x0A00 | ||
| 239 | #define _H3800_ASIC2_UART_1_Base 0x0C00 | ||
| 240 | #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ | ||
| 241 | #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ | ||
| 242 | #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ | ||
| 243 | #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ | ||
| 244 | #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ | ||
| 245 | #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ | ||
| 246 | #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ | ||
| 247 | #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ | ||
| 248 | #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ | ||
| 249 | #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ | ||
| 250 | #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ | ||
| 251 | |||
| 252 | #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) | ||
| 253 | #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) | ||
| 254 | #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) | ||
| 255 | #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) | ||
| 256 | #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) | ||
| 257 | #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) | ||
| 258 | #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) | ||
| 259 | #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) | ||
| 260 | #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) | ||
| 261 | #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) | ||
| 262 | #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) | ||
| 263 | |||
| 264 | #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) | ||
| 265 | #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) | ||
| 266 | #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) | ||
| 267 | #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) | ||
| 268 | #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) | ||
| 269 | #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) | ||
| 270 | #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) | ||
| 271 | #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) | ||
| 272 | #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) | ||
| 273 | #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) | ||
| 274 | #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) | ||
| 275 | |||
| 276 | #define _H3800_ASIC2_TIMER_Base 0x0E00 | ||
| 277 | #define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ | ||
| 278 | |||
| 279 | #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) | ||
| 280 | |||
| 281 | #define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ | ||
| 282 | #define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ | ||
| 283 | #define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ | ||
| 284 | #define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ | ||
| 285 | #define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ | ||
| 286 | #define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ | ||
| 287 | #define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ | ||
| 288 | #define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ | ||
| 289 | |||
| 290 | #define _H3800_ASIC2_CLOCK_Base 0x1000 | ||
| 291 | #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ | ||
| 292 | |||
| 293 | #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) | ||
| 294 | |||
| 295 | #define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ | ||
| 296 | #define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ | ||
| 297 | #define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ | ||
| 298 | #define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ | ||
| 299 | #define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ | ||
| 300 | #define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ | ||
| 301 | #define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ | ||
| 302 | #define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ | ||
| 303 | #define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ | ||
| 304 | #define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ | ||
| 305 | #define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ | ||
| 306 | #define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ | ||
| 307 | #define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ | ||
| 308 | #define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ | ||
| 309 | #define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ | ||
| 310 | #define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ | ||
| 311 | #define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ | ||
| 312 | #define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ | ||
| 313 | #define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ | ||
| 314 | |||
| 315 | #define _H3800_ASIC2_ADC_Base 0x1200 | ||
| 316 | #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ | ||
| 317 | #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ | ||
| 318 | #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ | ||
| 319 | |||
| 320 | #define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) | ||
| 321 | #define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) | ||
| 322 | #define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) | ||
| 323 | |||
| 324 | #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ | ||
| 325 | #define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ | ||
| 326 | |||
| 327 | #define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ | ||
| 328 | #define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) | ||
| 329 | #define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) | ||
| 330 | #define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ | ||
| 331 | #define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ | ||
| 332 | |||
| 333 | |||
| 334 | #define _H3800_ASIC2_INTR_Base 0x1600 | ||
| 335 | #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ | ||
| 336 | #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ | ||
| 337 | #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ | ||
| 338 | |||
| 339 | #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) | ||
| 340 | #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) | ||
| 341 | #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) | ||
| 342 | |||
| 343 | #define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ | ||
| 344 | #define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ | ||
| 345 | #define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ | ||
| 346 | #define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) | ||
| 347 | #define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) | ||
| 348 | #define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) | ||
| 349 | #define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) | ||
| 350 | |||
| 351 | #define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ | ||
| 352 | #define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ | ||
| 353 | |||
| 354 | |||
| 355 | #define _H3800_ASIC2_OWM_Base 0x1800 | ||
| 356 | #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ | ||
| 357 | #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ | ||
| 358 | #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ | ||
| 359 | #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ | ||
| 360 | #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ | ||
| 361 | |||
| 362 | #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) | ||
| 363 | #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) | ||
| 364 | #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) | ||
| 365 | #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) | ||
| 366 | #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) | ||
| 367 | |||
| 368 | #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ | ||
| 369 | #define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ | ||
| 370 | #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ | ||
| 371 | #define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ | ||
| 372 | |||
| 373 | #define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ | ||
| 374 | #define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ | ||
| 375 | #define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ | ||
| 376 | #define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ | ||
| 377 | #define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ | ||
| 378 | |||
| 379 | #define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ | ||
| 380 | #define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ | ||
| 381 | #define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ | ||
| 382 | #define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ | ||
| 383 | #define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ | ||
| 384 | |||
| 385 | #define _H3800_ASIC2_FlashCtl_Base 0x1A00 | ||
| 386 | |||
| 387 | /****************************************************/ | ||
| 388 | /* H3800, ASIC #1 | ||
| 389 | * This ASIC is accesed through ASIC #2, and | ||
| 390 | * mapped into the 1c00 - 1f00 region | ||
| 391 | */ | ||
| 392 | |||
| 393 | #define H3800_ASIC1_OFFSET(s,x,y) \ | ||
| 394 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) | ||
| 395 | |||
| 396 | #define _H3800_ASIC1_MMC_Base 0x1c00 | ||
| 397 | |||
| 398 | #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ | ||
| 399 | #define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ | ||
| 400 | #define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ | ||
| 401 | #define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ | ||
| 402 | #define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ | ||
| 403 | #define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ | ||
| 404 | #define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ | ||
| 405 | #define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ | ||
| 406 | #define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ | ||
| 407 | #define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ | ||
| 408 | #define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ | ||
| 409 | #define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ | ||
| 410 | #define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ | ||
| 411 | #define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ | ||
| 412 | #define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ | ||
| 413 | |||
| 414 | #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) | ||
| 415 | #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) | ||
| 416 | #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) | ||
| 417 | #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) | ||
| 418 | #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) | ||
| 419 | #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) | ||
| 420 | #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) | ||
| 421 | #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) | ||
| 422 | #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) | ||
| 423 | #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) | ||
| 424 | #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) | ||
| 425 | #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) | ||
| 426 | #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) | ||
| 427 | #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) | ||
| 428 | #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) | ||
| 429 | |||
| 430 | #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ | ||
| 431 | #define H3800_ASIC1_MMC_START_CLOCK (1 << 1) | ||
| 432 | |||
| 433 | #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) | ||
| 434 | #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) | ||
| 435 | #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) | ||
| 436 | #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) | ||
| 437 | #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ | ||
| 438 | #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) | ||
| 439 | #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) | ||
| 440 | #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) | ||
| 441 | #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ | ||
| 442 | #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ | ||
| 443 | #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ | ||
| 444 | #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ | ||
| 445 | |||
| 446 | #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ | ||
| 447 | #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ | ||
| 448 | #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ | ||
| 449 | #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ | ||
| 450 | |||
| 451 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 | ||
| 452 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 | ||
| 453 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 | ||
| 454 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 | ||
| 455 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ | ||
| 456 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ | ||
| 457 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ | ||
| 458 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ | ||
| 459 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ | ||
| 460 | |||
| 461 | #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) | ||
| 462 | #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) | ||
| 463 | #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) | ||
| 464 | #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) | ||
| 465 | |||
| 466 | #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) | ||
| 467 | |||
| 468 | /********* GPIO **********/ | ||
| 469 | |||
| 470 | #define _H3800_ASIC1_GPIO_Base 0x1e00 | ||
| 471 | |||
| 472 | #define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ | ||
| 473 | #define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ | ||
| 474 | #define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ | ||
| 475 | #define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ | ||
| 476 | #define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ | ||
| 477 | #define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ | ||
| 478 | #define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ | ||
| 479 | #define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ | ||
| 480 | #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ | ||
| 481 | #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ | ||
| 482 | #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ | ||
| 483 | #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ | ||
| 484 | #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ | ||
| 485 | #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ | ||
| 486 | #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ | ||
| 487 | #define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ | ||
| 488 | |||
| 489 | #define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) | ||
| 490 | #define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) | ||
| 491 | #define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) | ||
| 492 | #define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) | ||
| 493 | #define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) | ||
| 494 | #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) | ||
| 495 | #define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) | ||
| 496 | #define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) | ||
| 497 | #define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) | ||
| 498 | #define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) | ||
| 499 | #define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) | ||
| 500 | #define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) | ||
| 501 | #define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) | ||
| 502 | #define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) | ||
| 503 | #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) | ||
| 504 | #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 505 | |||
| 506 | #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) | ||
| 507 | #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) | ||
| 508 | #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) | ||
| 509 | #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) | ||
| 510 | #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) | ||
| 511 | #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) | ||
| 512 | |||
| 513 | #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) | ||
| 514 | #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) | ||
| 515 | #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) | ||
| 516 | |||
| 517 | /* These are all outputs */ | ||
| 518 | #define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ | ||
| 519 | #define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ | ||
| 520 | #define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ | ||
| 521 | #define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ | ||
| 522 | #define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ | ||
| 523 | #define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ | ||
| 524 | #define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ | ||
| 525 | #define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ | ||
| 526 | #define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ | ||
| 527 | #define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ | ||
| 528 | #define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ | ||
| 529 | #define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ | ||
| 530 | #define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ | ||
| 531 | #define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ | ||
| 532 | #define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ | ||
| 533 | |||
| 534 | /* Write enable for the flash */ | ||
| 535 | |||
| 536 | #define _H3800_ASIC1_FlashWP_Base 0x1F00 | ||
| 537 | #define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ | ||
| 538 | #define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) | ||
| 539 | |||
| 540 | #endif /* _INCLUDE_H3600_GPIO_H_ */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h new file mode 100644 index 000000000000..5976435f42c2 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/hardware.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware definitions for SA1100 architecture | ||
| 7 | * | ||
| 8 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 9 | * Definitions for SA1111 added. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 13 | #define __ASM_ARCH_HARDWARE_H | ||
| 14 | |||
| 15 | |||
| 16 | #define UNCACHEABLE_ADDR 0xfa050000 | ||
| 17 | |||
| 18 | |||
| 19 | /* | ||
| 20 | * SA1100 internal I/O mappings | ||
| 21 | * | ||
| 22 | * We have the following mapping: | ||
| 23 | * phys virt | ||
| 24 | * 80000000 f8000000 | ||
| 25 | * 90000000 fa000000 | ||
| 26 | * a0000000 fc000000 | ||
| 27 | * b0000000 fe000000 | ||
| 28 | */ | ||
| 29 | |||
| 30 | #define VIO_BASE 0xf8000000 /* virtual start of IO space */ | ||
| 31 | #define VIO_SHIFT 3 /* x = IO space shrink power */ | ||
| 32 | #define PIO_START 0x80000000 /* physical start of IO space */ | ||
| 33 | |||
| 34 | #define io_p2v( x ) \ | ||
| 35 | ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) | ||
| 36 | #define io_v2p( x ) \ | ||
| 37 | ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) | ||
| 38 | |||
| 39 | #ifndef __ASSEMBLY__ | ||
| 40 | |||
| 41 | # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | ||
| 42 | # define __PREG(x) (io_v2p((unsigned long)&(x))) | ||
| 43 | |||
| 44 | #else | ||
| 45 | |||
| 46 | # define __REG(x) io_p2v(x) | ||
| 47 | # define __PREG(x) io_v2p(x) | ||
| 48 | |||
| 49 | #endif | ||
| 50 | |||
| 51 | #include "SA-1100.h" | ||
| 52 | |||
| 53 | #ifdef CONFIG_SA1101 | ||
| 54 | #include "SA-1101.h" | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/ide.h b/arch/arm/mach-sa1100/include/mach/ide.h new file mode 100644 index 000000000000..4c99c8f5e617 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/ide.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/ide.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre | ||
| 5 | * | ||
| 6 | * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl) | ||
| 7 | * Get rid of the special ide_init_hwif_ports() functions | ||
| 8 | * and make a generalised function that can be used by all | ||
| 9 | * architectures. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/irq.h> | ||
| 13 | #include <mach/hardware.h> | ||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #error "This code is broken and needs update to match with current ide support" | ||
| 17 | |||
| 18 | |||
| 19 | /* | ||
| 20 | * Set up a hw structure for a specified data port, control port and IRQ. | ||
| 21 | * This should follow whatever the default interface uses. | ||
| 22 | */ | ||
| 23 | static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, | ||
| 24 | unsigned long ctrl_port, int *irq) | ||
| 25 | { | ||
| 26 | unsigned long reg = data_port; | ||
| 27 | int i; | ||
| 28 | int regincr = 1; | ||
| 29 | |||
| 30 | /* The Empeg board has the first two address lines unused */ | ||
| 31 | if (machine_is_empeg()) | ||
| 32 | regincr = 1 << 2; | ||
| 33 | |||
| 34 | /* The LART doesn't use A0 for IDE */ | ||
| 35 | if (machine_is_lart()) | ||
| 36 | regincr = 1 << 1; | ||
| 37 | |||
| 38 | memset(hw, 0, sizeof(*hw)); | ||
| 39 | |||
| 40 | for (i = 0; i <= 7; i++) { | ||
| 41 | hw->io_ports_array[i] = reg; | ||
| 42 | reg += regincr; | ||
| 43 | } | ||
| 44 | |||
| 45 | hw->io_ports.ctl_addr = ctrl_port; | ||
| 46 | |||
| 47 | if (irq) | ||
| 48 | *irq = 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | /* | ||
| 52 | * This registers the standard ports for this architecture with the IDE | ||
| 53 | * driver. | ||
| 54 | */ | ||
| 55 | static __inline__ void | ||
| 56 | ide_init_default_hwifs(void) | ||
| 57 | { | ||
| 58 | if (machine_is_lart()) { | ||
| 59 | #ifdef CONFIG_SA1100_LART | ||
| 60 | hw_regs_t hw; | ||
| 61 | |||
| 62 | /* Enable GPIO as interrupt line */ | ||
| 63 | GPDR &= ~LART_GPIO_IDE; | ||
| 64 | set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING); | ||
| 65 | |||
| 66 | /* set PCMCIA interface timing */ | ||
| 67 | MECR = 0x00060006; | ||
| 68 | |||
| 69 | /* init the interface */ | ||
| 70 | ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL); | ||
| 71 | hw.irq = LART_IRQ_IDE; | ||
| 72 | ide_register_hw(&hw); | ||
| 73 | #endif | ||
| 74 | } | ||
| 75 | } | ||
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h new file mode 100644 index 000000000000..0c070a6149bc --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/io.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997-1999 Russell King | ||
| 5 | * | ||
| 6 | * Modifications: | ||
| 7 | * 06-12-1997 RMK Created. | ||
| 8 | * 07-04-1999 RMK Major cleanup | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 11 | #define __ASM_ARM_ARCH_IO_H | ||
| 12 | |||
| 13 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 14 | |||
| 15 | /* | ||
| 16 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 17 | * drivers out there that might just work if we fake them... | ||
| 18 | */ | ||
| 19 | static inline void __iomem *__io(unsigned long addr) | ||
| 20 | { | ||
| 21 | return (void __iomem *)addr; | ||
| 22 | } | ||
| 23 | #define __io(a) __io(a) | ||
| 24 | #define __mem_pci(a) (a) | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h new file mode 100644 index 000000000000..0cb36609b3ac --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/irqs.h | |||
| @@ -0,0 +1,197 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). | ||
| 6 | * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) | ||
| 7 | * | ||
| 8 | * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define IRQ_GPIO0 0 | ||
| 12 | #define IRQ_GPIO1 1 | ||
| 13 | #define IRQ_GPIO2 2 | ||
| 14 | #define IRQ_GPIO3 3 | ||
| 15 | #define IRQ_GPIO4 4 | ||
| 16 | #define IRQ_GPIO5 5 | ||
| 17 | #define IRQ_GPIO6 6 | ||
| 18 | #define IRQ_GPIO7 7 | ||
| 19 | #define IRQ_GPIO8 8 | ||
| 20 | #define IRQ_GPIO9 9 | ||
| 21 | #define IRQ_GPIO10 10 | ||
| 22 | #define IRQ_GPIO11_27 11 | ||
| 23 | #define IRQ_LCD 12 /* LCD controller */ | ||
| 24 | #define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */ | ||
| 25 | #define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */ | ||
| 26 | #define IRQ_Ser1UART 15 /* Ser. port 1 UART */ | ||
| 27 | #define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */ | ||
| 28 | #define IRQ_Ser3UART 17 /* Ser. port 3 UART */ | ||
| 29 | #define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */ | ||
| 30 | #define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */ | ||
| 31 | #define IRQ_DMA0 20 /* DMA controller channel 0 */ | ||
| 32 | #define IRQ_DMA1 21 /* DMA controller channel 1 */ | ||
| 33 | #define IRQ_DMA2 22 /* DMA controller channel 2 */ | ||
| 34 | #define IRQ_DMA3 23 /* DMA controller channel 3 */ | ||
| 35 | #define IRQ_DMA4 24 /* DMA controller channel 4 */ | ||
| 36 | #define IRQ_DMA5 25 /* DMA controller channel 5 */ | ||
| 37 | #define IRQ_OST0 26 /* OS Timer match 0 */ | ||
| 38 | #define IRQ_OST1 27 /* OS Timer match 1 */ | ||
| 39 | #define IRQ_OST2 28 /* OS Timer match 2 */ | ||
| 40 | #define IRQ_OST3 29 /* OS Timer match 3 */ | ||
| 41 | #define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */ | ||
| 42 | #define IRQ_RTCAlrm 31 /* RTC Alarm */ | ||
| 43 | |||
| 44 | #define IRQ_GPIO11 32 | ||
| 45 | #define IRQ_GPIO12 33 | ||
| 46 | #define IRQ_GPIO13 34 | ||
| 47 | #define IRQ_GPIO14 35 | ||
| 48 | #define IRQ_GPIO15 36 | ||
| 49 | #define IRQ_GPIO16 37 | ||
| 50 | #define IRQ_GPIO17 38 | ||
| 51 | #define IRQ_GPIO18 39 | ||
| 52 | #define IRQ_GPIO19 40 | ||
| 53 | #define IRQ_GPIO20 41 | ||
| 54 | #define IRQ_GPIO21 42 | ||
| 55 | #define IRQ_GPIO22 43 | ||
| 56 | #define IRQ_GPIO23 44 | ||
| 57 | #define IRQ_GPIO24 45 | ||
| 58 | #define IRQ_GPIO25 46 | ||
| 59 | #define IRQ_GPIO26 47 | ||
| 60 | #define IRQ_GPIO27 48 | ||
| 61 | |||
| 62 | /* | ||
| 63 | * The next 16 interrupts are for board specific purposes. Since | ||
| 64 | * the kernel can only run on one machine at a time, we can re-use | ||
| 65 | * these. If you need more, increase IRQ_BOARD_END, but keep it | ||
| 66 | * within sensible limits. IRQs 49 to 64 are available. | ||
| 67 | */ | ||
| 68 | #define IRQ_BOARD_START 49 | ||
| 69 | #define IRQ_BOARD_END 65 | ||
| 70 | |||
| 71 | #define IRQ_SA1111_START (IRQ_BOARD_END) | ||
| 72 | #define IRQ_GPAIN0 (IRQ_BOARD_END + 0) | ||
| 73 | #define IRQ_GPAIN1 (IRQ_BOARD_END + 1) | ||
| 74 | #define IRQ_GPAIN2 (IRQ_BOARD_END + 2) | ||
| 75 | #define IRQ_GPAIN3 (IRQ_BOARD_END + 3) | ||
| 76 | #define IRQ_GPBIN0 (IRQ_BOARD_END + 4) | ||
| 77 | #define IRQ_GPBIN1 (IRQ_BOARD_END + 5) | ||
| 78 | #define IRQ_GPBIN2 (IRQ_BOARD_END + 6) | ||
| 79 | #define IRQ_GPBIN3 (IRQ_BOARD_END + 7) | ||
| 80 | #define IRQ_GPBIN4 (IRQ_BOARD_END + 8) | ||
| 81 | #define IRQ_GPBIN5 (IRQ_BOARD_END + 9) | ||
| 82 | #define IRQ_GPCIN0 (IRQ_BOARD_END + 10) | ||
| 83 | #define IRQ_GPCIN1 (IRQ_BOARD_END + 11) | ||
| 84 | #define IRQ_GPCIN2 (IRQ_BOARD_END + 12) | ||
| 85 | #define IRQ_GPCIN3 (IRQ_BOARD_END + 13) | ||
| 86 | #define IRQ_GPCIN4 (IRQ_BOARD_END + 14) | ||
| 87 | #define IRQ_GPCIN5 (IRQ_BOARD_END + 15) | ||
| 88 | #define IRQ_GPCIN6 (IRQ_BOARD_END + 16) | ||
| 89 | #define IRQ_GPCIN7 (IRQ_BOARD_END + 17) | ||
| 90 | #define IRQ_MSTXINT (IRQ_BOARD_END + 18) | ||
| 91 | #define IRQ_MSRXINT (IRQ_BOARD_END + 19) | ||
| 92 | #define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) | ||
| 93 | #define IRQ_TPTXINT (IRQ_BOARD_END + 21) | ||
| 94 | #define IRQ_TPRXINT (IRQ_BOARD_END + 22) | ||
| 95 | #define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) | ||
| 96 | #define SSPXMTINT (IRQ_BOARD_END + 24) | ||
| 97 | #define SSPRCVINT (IRQ_BOARD_END + 25) | ||
| 98 | #define SSPROR (IRQ_BOARD_END + 26) | ||
| 99 | #define AUDXMTDMADONEA (IRQ_BOARD_END + 32) | ||
| 100 | #define AUDRCVDMADONEA (IRQ_BOARD_END + 33) | ||
| 101 | #define AUDXMTDMADONEB (IRQ_BOARD_END + 34) | ||
| 102 | #define AUDRCVDMADONEB (IRQ_BOARD_END + 35) | ||
| 103 | #define AUDTFSR (IRQ_BOARD_END + 36) | ||
| 104 | #define AUDRFSR (IRQ_BOARD_END + 37) | ||
| 105 | #define AUDTUR (IRQ_BOARD_END + 38) | ||
| 106 | #define AUDROR (IRQ_BOARD_END + 39) | ||
| 107 | #define AUDDTS (IRQ_BOARD_END + 40) | ||
| 108 | #define AUDRDD (IRQ_BOARD_END + 41) | ||
| 109 | #define AUDSTO (IRQ_BOARD_END + 42) | ||
| 110 | #define IRQ_USBPWR (IRQ_BOARD_END + 43) | ||
| 111 | #define IRQ_HCIM (IRQ_BOARD_END + 44) | ||
| 112 | #define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) | ||
| 113 | #define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) | ||
| 114 | #define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) | ||
| 115 | #define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) | ||
| 116 | #define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) | ||
| 117 | #define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) | ||
| 118 | #define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) | ||
| 119 | #define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) | ||
| 120 | #define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) | ||
| 121 | #define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) | ||
| 122 | |||
| 123 | #define IRQ_LOCOMO_START (IRQ_BOARD_END) | ||
| 124 | #define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) | ||
| 125 | #define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) | ||
| 126 | #define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) | ||
| 127 | #define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) | ||
| 128 | #define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) | ||
| 129 | #define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) | ||
| 130 | #define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) | ||
| 131 | #define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) | ||
| 132 | #define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) | ||
| 133 | #define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) | ||
| 134 | #define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) | ||
| 135 | #define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) | ||
| 136 | #define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) | ||
| 137 | #define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) | ||
| 138 | #define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) | ||
| 139 | #define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) | ||
| 140 | #define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) | ||
| 141 | #define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) | ||
| 142 | #define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) | ||
| 143 | #define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) | ||
| 144 | #define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) | ||
| 145 | #define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Figure out the MAX IRQ number. | ||
| 149 | * | ||
| 150 | * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. | ||
| 151 | * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 | ||
| 152 | * Otherwise, we have the standard IRQs only. | ||
| 153 | */ | ||
| 154 | #ifdef CONFIG_SA1111 | ||
| 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) | ||
| 156 | #elif defined(CONFIG_SA1100_H3800) | ||
| 157 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 158 | #elif defined(CONFIG_SHARP_LOCOMO) | ||
| 159 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) | ||
| 160 | #else | ||
| 161 | #define NR_IRQS (IRQ_BOARD_START) | ||
| 162 | #endif | ||
| 163 | |||
| 164 | /* | ||
| 165 | * Board specific IRQs. Define them here. | ||
| 166 | * Do not surround them with ifdefs. | ||
| 167 | */ | ||
| 168 | #define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) | ||
| 169 | #define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) | ||
| 170 | #define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) | ||
| 171 | |||
| 172 | /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ | ||
| 173 | #define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) | ||
| 174 | #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) | ||
| 175 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) | ||
| 176 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) | ||
| 177 | |||
| 178 | /* H3800-specific IRQs (CONFIG_SA1100_H3800) */ | ||
| 179 | #define H3800_KPIO_IRQ_START (IRQ_BOARD_START) | ||
| 180 | #define IRQ_H3800_KEY (IRQ_BOARD_START + 0) | ||
| 181 | #define IRQ_H3800_SPI (IRQ_BOARD_START + 1) | ||
| 182 | #define IRQ_H3800_OWM (IRQ_BOARD_START + 2) | ||
| 183 | #define IRQ_H3800_ADC (IRQ_BOARD_START + 3) | ||
| 184 | #define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) | ||
| 185 | #define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) | ||
| 186 | #define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) | ||
| 187 | #define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) | ||
| 188 | #define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) | ||
| 189 | #define H3800_KPIO_IRQ_COUNT 9 | ||
| 190 | |||
| 191 | #define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) | ||
| 192 | #define IRQ_H3800_PEN (IRQ_BOARD_START + 9) | ||
| 193 | #define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) | ||
| 194 | #define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) | ||
| 195 | #define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) | ||
| 196 | #define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) | ||
| 197 | #define H3800_GPIO_IRQ_COUNT 5 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/jornada720.h b/arch/arm/mach-sa1100/include/mach/jornada720.h new file mode 100644 index 000000000000..bc120850d313 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/jornada720.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/jornada720.h | ||
| 3 | * | ||
| 4 | * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728 | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> | ||
| 7 | * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* HP Jornada 7xx microprocessor commands */ | ||
| 16 | #define GETBATTERYDATA 0xc0 | ||
| 17 | #define GETSCANKEYCODE 0x90 | ||
| 18 | #define GETTOUCHSAMPLES 0xa0 | ||
| 19 | #define GETCONTRAST 0xD0 | ||
| 20 | #define SETCONTRAST 0xD1 | ||
| 21 | #define GETBRIGHTNESS 0xD2 | ||
| 22 | #define SETBRIGHTNESS 0xD3 | ||
| 23 | #define CONTRASTOFF 0xD8 | ||
| 24 | #define BRIGHTNESSOFF 0xD9 | ||
| 25 | #define PWMOFF 0xDF | ||
| 26 | #define TXDUMMY 0x11 | ||
| 27 | #define ERRORCODE 0x00 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/lart.h b/arch/arm/mach-sa1100/include/mach/lart.h new file mode 100644 index 000000000000..8a5482d908db --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/lart.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef _INCLUDE_LART_H | ||
| 2 | #define _INCLUDE_LART_H | ||
| 3 | |||
| 4 | #define LART_GPIO_ETH0 GPIO_GPIO0 | ||
| 5 | #define LART_IRQ_ETH0 IRQ_GPIO0 | ||
| 6 | |||
| 7 | #define LART_GPIO_IDE GPIO_GPIO1 | ||
| 8 | #define LART_IRQ_IDE IRQ_GPIO1 | ||
| 9 | |||
| 10 | #define LART_GPIO_UCB1200 GPIO_GPIO18 | ||
| 11 | #define LART_IRQ_UCB1200 IRQ_GPIO18 | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h new file mode 100644 index 000000000000..fb8b09a57ad7 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/mcp.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/mcp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_MCP_H | ||
| 11 | #define __ASM_ARM_ARCH_MCP_H | ||
| 12 | |||
| 13 | #include <linux/types.h> | ||
| 14 | |||
| 15 | struct mcp_plat_data { | ||
| 16 | u32 mccr0; | ||
| 17 | u32 mccr1; | ||
| 18 | unsigned int sclk_rate; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h new file mode 100644 index 000000000000..29f639e2afc6 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/memory.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org> | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 8 | #define __ASM_ARCH_MEMORY_H | ||
| 9 | |||
| 10 | #include <asm/sizes.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Physical DRAM offset is 0xc0000000 on the SA1100 | ||
| 14 | */ | ||
| 15 | #define PHYS_OFFSET UL(0xc0000000) | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | |||
| 19 | #ifdef CONFIG_SA1111 | ||
| 20 | void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); | ||
| 21 | |||
| 22 | #define arch_adjust_zones(node, size, holes) \ | ||
| 23 | sa1111_adjust_zones(node, size, holes) | ||
| 24 | |||
| 25 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) | ||
| 26 | |||
| 27 | #endif | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Virtual view <-> DMA view memory address translations | ||
| 32 | * virt_to_bus: Used to translate the virtual address to an | ||
| 33 | * address suitable to be passed to set_dma_addr | ||
| 34 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 35 | * to an address that the kernel can use. | ||
| 36 | * | ||
| 37 | * On the SA1100, bus addresses are equivalent to physical addresses. | ||
| 38 | */ | ||
| 39 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 40 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Because of the wide memory address space between physical RAM banks on the | ||
| 44 | * SA1100, it's much convenient to use Linux's NUMA support to implement our | ||
| 45 | * memory map representation. Assuming all memory nodes have equal access | ||
| 46 | * characteristics, we then have generic discontiguous memory support. | ||
| 47 | * | ||
| 48 | * Of course, all this isn't mandatory for SA1100 implementations with only | ||
| 49 | * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. | ||
| 50 | * | ||
| 51 | * The nodes are matched with the physical memory bank addresses which are | ||
| 52 | * incidentally the same as virtual addresses. | ||
| 53 | * | ||
| 54 | * node 0: 0xc0000000 - 0xc7ffffff | ||
| 55 | * node 1: 0xc8000000 - 0xcfffffff | ||
| 56 | * node 2: 0xd0000000 - 0xd7ffffff | ||
| 57 | * node 3: 0xd8000000 - 0xdfffffff | ||
| 58 | */ | ||
| 59 | #define NODE_MEM_SIZE_BITS 27 | ||
| 60 | |||
| 61 | /* | ||
| 62 | * Cache flushing area - SA1100 zero bank | ||
| 63 | */ | ||
| 64 | #define FLUSH_BASE_PHYS 0xe0000000 | ||
| 65 | #define FLUSH_BASE 0xf5000000 | ||
| 66 | #define FLUSH_BASE_MINICACHE 0xf5100000 | ||
| 67 | |||
| 68 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/mtd-xip.h b/arch/arm/mach-sa1100/include/mach/mtd-xip.h new file mode 100644 index 000000000000..80cfdac2b944 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/mtd-xip.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * MTD primitives for XIP support. Architecture specific functions | ||
| 3 | * | ||
| 4 | * Do not include this file directly. It's included from linux/mtd/xip.h | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Nov 2, 2004 | ||
| 8 | * Copyright: (C) 2004 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_SA1100_MTD_XIP_H__ | ||
| 18 | #define __ARCH_SA1100_MTD_XIP_H__ | ||
| 19 | |||
| 20 | #define xip_irqpending() (ICIP & ICMR) | ||
| 21 | |||
| 22 | /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ | ||
| 23 | #define xip_currtime() (OSCR) | ||
| 24 | #define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) | ||
| 25 | |||
| 26 | #endif /* __ARCH_SA1100_MTD_XIP_H__ */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h new file mode 100644 index 000000000000..d3f044f92c00 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/neponset.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/neponset.h | ||
| 3 | * | ||
| 4 | * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for Assabet | ||
| 7 | * Only include this file from SA1100-specific files. | ||
| 8 | * | ||
| 9 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 10 | * Definitions for Neponset added. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_NEPONSET_H | ||
| 13 | #define __ASM_ARCH_NEPONSET_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Neponset definitions: | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define NEPONSET_CPLD_BASE (0x10000000) | ||
| 20 | #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) | ||
| 21 | #define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) | ||
| 22 | |||
| 23 | #define _IRR 0x10000024 /* Interrupt Reason Register */ | ||
| 24 | #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ | ||
| 25 | #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ | ||
| 26 | #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ | ||
| 27 | #define _NCR_0 0x100000a0 /* Control Register (RW) */ | ||
| 28 | #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ | ||
| 29 | #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ | ||
| 30 | #define _SWPK 0x10000020 /* Switch pack (RO) */ | ||
| 31 | #define _WHOAMI 0x10000000 /* System ID Register (RO) */ | ||
| 32 | |||
| 33 | #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ | ||
| 34 | |||
| 35 | #define IRR (*((volatile u_char *) Nep_p2v(_IRR))) | ||
| 36 | #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) | ||
| 37 | #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) | ||
| 38 | #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) | ||
| 39 | #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) | ||
| 40 | #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) | ||
| 41 | #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) | ||
| 42 | #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) | ||
| 43 | #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) | ||
| 44 | |||
| 45 | #define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) | ||
| 46 | |||
| 47 | #define IRR_ETHERNET (1<<0) | ||
| 48 | #define IRR_USAR (1<<1) | ||
| 49 | #define IRR_SA1111 (1<<2) | ||
| 50 | |||
| 51 | #define AUD_SEL_1341 (1<<0) | ||
| 52 | #define AUD_MUTE_1341 (1<<1) | ||
| 53 | |||
| 54 | #define MDM_CTL0_RTS1 (1 << 0) | ||
| 55 | #define MDM_CTL0_DTR1 (1 << 1) | ||
| 56 | #define MDM_CTL0_RTS2 (1 << 2) | ||
| 57 | #define MDM_CTL0_DTR2 (1 << 3) | ||
| 58 | |||
| 59 | #define MDM_CTL1_CTS1 (1 << 0) | ||
| 60 | #define MDM_CTL1_DSR1 (1 << 1) | ||
| 61 | #define MDM_CTL1_DCD1 (1 << 2) | ||
| 62 | #define MDM_CTL1_CTS2 (1 << 3) | ||
| 63 | #define MDM_CTL1_DSR2 (1 << 4) | ||
| 64 | #define MDM_CTL1_DCD2 (1 << 5) | ||
| 65 | |||
| 66 | #define NCR_GP01_OFF (1<<0) | ||
| 67 | #define NCR_TP_PWR_EN (1<<1) | ||
| 68 | #define NCR_MS_PWR_EN (1<<2) | ||
| 69 | #define NCR_ENET_OSC_EN (1<<3) | ||
| 70 | #define NCR_SPI_KB_WK_UP (1<<4) | ||
| 71 | #define NCR_A0VPP (1<<5) | ||
| 72 | #define NCR_A1VPP (1<<6) | ||
| 73 | |||
| 74 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h new file mode 100644 index 000000000000..ec27d6e12140 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/shannon.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | #ifndef _INCLUDE_SHANNON_H | ||
| 2 | #define _INCLUDE_SHANNON_H | ||
| 3 | |||
| 4 | /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, | ||
| 5 | * written by <forsyth@vitanuova.com> */ | ||
| 6 | |||
| 7 | #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ | ||
| 8 | #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ | ||
| 9 | /* lcd lower = GPIO 2-9 */ | ||
| 10 | #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ | ||
| 11 | #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ | ||
| 12 | #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ | ||
| 13 | #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ | ||
| 14 | #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ | ||
| 15 | #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 | ||
| 16 | #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ | ||
| 17 | #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ | ||
| 18 | #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 | ||
| 19 | #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ | ||
| 20 | #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ | ||
| 21 | #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ | ||
| 22 | #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ | ||
| 23 | #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ | ||
| 24 | #define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ | ||
| 25 | /* XXX GPIO 23 unaccounted for */ | ||
| 26 | #define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ | ||
| 27 | #define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 | ||
| 28 | #define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ | ||
| 29 | #define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 | ||
| 30 | #define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ | ||
| 31 | #define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 | ||
| 32 | #define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ | ||
| 33 | #define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 | ||
| 34 | |||
| 35 | /* MCP UCB codec GPIO pins... */ | ||
| 36 | |||
| 37 | #define SHANNON_UCB_GPIO_BACKLIGHT 9 | ||
| 38 | #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 | ||
| 39 | #define SHANNON_UCB_GPIO_BRIGHT 6 | ||
| 40 | #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f | ||
| 41 | #define SHANNON_UCB_GPIO_CONTRAST 0 | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h new file mode 100644 index 000000000000..9296c4513ce1 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/simpad.h | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/simpad.h | ||
| 3 | * | ||
| 4 | * based of assabet.h same as HUW_Webpanel | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for SIMpad | ||
| 7 | * | ||
| 8 | * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_SIMPAD_H | ||
| 12 | #define __ASM_ARCH_SIMPAD_H | ||
| 13 | |||
| 14 | |||
| 15 | #define GPIO_UART1_RTS GPIO_GPIO14 | ||
| 16 | #define GPIO_UART1_DTR GPIO_GPIO7 | ||
| 17 | #define GPIO_UART1_CTS GPIO_GPIO8 | ||
| 18 | #define GPIO_UART1_DCD GPIO_GPIO23 | ||
| 19 | #define GPIO_UART1_DSR GPIO_GPIO6 | ||
| 20 | |||
| 21 | #define GPIO_UART3_RTS GPIO_GPIO12 | ||
| 22 | #define GPIO_UART3_DTR GPIO_GPIO16 | ||
| 23 | #define GPIO_UART3_CTS GPIO_GPIO13 | ||
| 24 | #define GPIO_UART3_DCD GPIO_GPIO18 | ||
| 25 | #define GPIO_UART3_DSR GPIO_GPIO17 | ||
| 26 | |||
| 27 | #define GPIO_POWER_BUTTON GPIO_GPIO0 | ||
| 28 | #define GPIO_UCB1300_IRQ GPIO_GPIO22 /* UCB GPIO and touchscreen */ | ||
| 29 | |||
| 30 | #define IRQ_UART1_CTS IRQ_GPIO15 | ||
| 31 | #define IRQ_UART1_DCD GPIO_GPIO23 | ||
| 32 | #define IRQ_UART1_DSR GPIO_GPIO6 | ||
| 33 | #define IRQ_UART3_CTS GPIO_GPIO13 | ||
| 34 | #define IRQ_UART3_DCD GPIO_GPIO18 | ||
| 35 | #define IRQ_UART3_DSR GPIO_GPIO17 | ||
| 36 | |||
| 37 | #define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22 | ||
| 38 | #define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0 | ||
| 39 | |||
| 40 | |||
| 41 | /*--- PCMCIA ---*/ | ||
| 42 | #define GPIO_CF_CD GPIO_GPIO24 | ||
| 43 | #define GPIO_CF_IRQ GPIO_GPIO1 | ||
| 44 | #define IRQ_GPIO_CF_IRQ IRQ_GPIO1 | ||
| 45 | #define IRQ_GPIO_CF_CD IRQ_GPIO24 | ||
| 46 | |||
| 47 | /*--- SmartCard ---*/ | ||
| 48 | #define GPIO_SMART_CARD GPIO_GPIO10 | ||
| 49 | #define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 | ||
| 50 | |||
| 51 | // CS3 Latch is write only, a shadow is necessary | ||
| 52 | |||
| 53 | #define CS3BUSTYPE unsigned volatile long | ||
| 54 | #define CS3_BASE 0xf1000000 | ||
| 55 | |||
| 56 | #define VCC_5V_EN 0x0001 // For 5V PCMCIA | ||
| 57 | #define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA | ||
| 58 | #define EN1 0x0004 // This is only for EPROM's | ||
| 59 | #define EN0 0x0008 // Both should be enable for 3.3V or 5V | ||
| 60 | #define DISPLAY_ON 0x0010 | ||
| 61 | #define PCMCIA_BUFF_DIS 0x0020 | ||
| 62 | #define MQ_RESET 0x0040 | ||
| 63 | #define PCMCIA_RESET 0x0080 | ||
| 64 | #define DECT_POWER_ON 0x0100 | ||
| 65 | #define IRDA_SD 0x0200 // Shutdown for powersave | ||
| 66 | #define RS232_ON 0x0400 | ||
| 67 | #define SD_MEDIAQ 0x0800 // Shutdown for powersave | ||
| 68 | #define LED2_ON 0x1000 | ||
| 69 | #define IRDA_MODE 0x2000 // Fast/Slow IrDA mode | ||
| 70 | #define ENABLE_5V 0x4000 // Enable 5V circuit | ||
| 71 | #define RESET_SIMCARD 0x8000 | ||
| 72 | |||
| 73 | #define RS232_ENABLE 0x0440 | ||
| 74 | #define PCMCIAMASK 0x402f | ||
| 75 | |||
| 76 | |||
| 77 | struct simpad_battery { | ||
| 78 | unsigned char ac_status; /* line connected yes/no */ | ||
| 79 | unsigned char status; /* battery loading yes/no */ | ||
| 80 | unsigned char percentage; /* percentage loaded */ | ||
| 81 | unsigned short life; /* life till empty */ | ||
| 82 | }; | ||
| 83 | |||
| 84 | /* These should match the apm_bios.h definitions */ | ||
| 85 | #define SIMPAD_AC_STATUS_AC_OFFLINE 0x00 | ||
| 86 | #define SIMPAD_AC_STATUS_AC_ONLINE 0x01 | ||
| 87 | #define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */ | ||
| 88 | #define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff | ||
| 89 | |||
| 90 | /* These bitfields are rarely "or'd" together */ | ||
| 91 | #define SIMPAD_BATT_STATUS_HIGH 0x01 | ||
| 92 | #define SIMPAD_BATT_STATUS_LOW 0x02 | ||
| 93 | #define SIMPAD_BATT_STATUS_CRITICAL 0x04 | ||
| 94 | #define SIMPAD_BATT_STATUS_CHARGING 0x08 | ||
| 95 | #define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10 | ||
| 96 | #define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */ | ||
| 97 | #define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */ | ||
| 98 | #define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */ | ||
| 99 | #define SIMPAD_BATT_STATUS_NOBATT 0x80 | ||
| 100 | #define SIMPAD_BATT_STATUS_UNKNOWN 0xff | ||
| 101 | |||
| 102 | extern int simpad_get_battery(struct simpad_battery* ); | ||
| 103 | |||
| 104 | #endif // __ASM_ARCH_SIMPAD_H | ||
| 105 | |||
| 106 | |||
| 107 | |||
| 108 | |||
| 109 | |||
| 110 | |||
| 111 | |||
| 112 | |||
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h new file mode 100644 index 000000000000..63755ca5b1b4 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/system.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/system.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> | ||
| 5 | */ | ||
| 6 | #include <mach/hardware.h> | ||
| 7 | |||
| 8 | static inline void arch_idle(void) | ||
| 9 | { | ||
| 10 | cpu_do_idle(); | ||
| 11 | } | ||
| 12 | |||
| 13 | static inline void arch_reset(char mode) | ||
| 14 | { | ||
| 15 | if (mode == 's') { | ||
| 16 | /* Jump into ROM at address 0 */ | ||
| 17 | cpu_reset(0); | ||
| 18 | } else { | ||
| 19 | /* Use on-chip reset capability */ | ||
| 20 | RSRR = RSRR_SWR; | ||
| 21 | } | ||
| 22 | } | ||
diff --git a/arch/arm/mach-sa1100/include/mach/timex.h b/arch/arm/mach-sa1100/include/mach/timex.h new file mode 100644 index 000000000000..7a5d017b58b3 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/timex.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * SA1100 architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1998 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * SA1100 timer | ||
| 11 | */ | ||
| 12 | #define CLOCK_TICK_RATE 3686400 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h new file mode 100644 index 000000000000..714160b03d7a --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/uncompress.h | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * (C) 1999 Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * Reorganised to be machine independent. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include "hardware.h" | ||
| 10 | |||
| 11 | /* | ||
| 12 | * The following code assumes the serial port has already been | ||
| 13 | * initialized by the bootloader. We search for the first enabled | ||
| 14 | * port in the most probable order. If you didn't setup a port in | ||
| 15 | * your bootloader then nothing will appear (which might be desired). | ||
| 16 | */ | ||
| 17 | |||
| 18 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
| 19 | |||
| 20 | static void putc(int c) | ||
| 21 | { | ||
| 22 | unsigned long serial_port; | ||
| 23 | |||
| 24 | do { | ||
| 25 | serial_port = _Ser3UTCR0; | ||
| 26 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 27 | serial_port = _Ser1UTCR0; | ||
| 28 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 29 | serial_port = _Ser2UTCR0; | ||
| 30 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 31 | return; | ||
| 32 | } while (0); | ||
| 33 | |||
| 34 | /* wait for space in the UART's transmitter */ | ||
| 35 | while (!(UART(UTSR1) & UTSR1_TNF)) | ||
| 36 | barrier(); | ||
| 37 | |||
| 38 | /* send the character out. */ | ||
| 39 | UART(UTDR) = c; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline void flush(void) | ||
| 43 | { | ||
| 44 | } | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Nothing to do for these | ||
| 48 | */ | ||
| 49 | #define arch_decomp_setup() | ||
| 50 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h new file mode 100644 index 000000000000..ec8fdc5a3606 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/vmalloc.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (0xe8000000) | ||