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Diffstat (limited to 'arch/arm/mach-sa1100/clock.c')
-rw-r--r--arch/arm/mach-sa1100/clock.c82
1 files changed, 47 insertions, 35 deletions
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dab3c6347a8f..172ebd0ee0a2 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,17 +11,29 @@
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
14 16
15#include <mach/hardware.h> 17#include <mach/hardware.h>
16 18
17/* 19struct clkops {
18 * Very simple clock implementation - we only have one clock to deal with. 20 void (*enable)(struct clk *);
19 */ 21 void (*disable)(struct clk *);
22};
23
20struct clk { 24struct clk {
25 const struct clkops *ops;
21 unsigned int enabled; 26 unsigned int enabled;
22}; 27};
23 28
24static void clk_gpio27_enable(void) 29#define DEFINE_CLK(_name, _ops) \
30struct clk clk_##_name = { \
31 .ops = _ops, \
32 }
33
34static DEFINE_SPINLOCK(clocks_lock);
35
36static void clk_gpio27_enable(struct clk *clk)
25{ 37{
26 /* 38 /*
27 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 39 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +44,24 @@ static void clk_gpio27_enable(void)
32 TUCR = TUCR_3_6864MHz; 44 TUCR = TUCR_3_6864MHz;
33} 45}
34 46
35static void clk_gpio27_disable(void) 47static void clk_gpio27_disable(struct clk *clk)
36{ 48{
37 TUCR = 0; 49 TUCR = 0;
38 GPDR &= ~GPIO_32_768kHz; 50 GPDR &= ~GPIO_32_768kHz;
39 GAFR &= ~GPIO_32_768kHz; 51 GAFR &= ~GPIO_32_768kHz;
40} 52}
41 53
42static struct clk clk_gpio27;
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46struct clk *clk_get(struct device *dev, const char *id)
47{
48 const char *devname = dev_name(dev);
49
50 return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
51}
52EXPORT_SYMBOL(clk_get);
53
54void clk_put(struct clk *clk)
55{
56}
57EXPORT_SYMBOL(clk_put);
58
59int clk_enable(struct clk *clk) 54int clk_enable(struct clk *clk)
60{ 55{
61 unsigned long flags; 56 unsigned long flags;
62 57
63 spin_lock_irqsave(&clocks_lock, flags); 58 if (clk) {
64 if (clk->enabled++ == 0) 59 spin_lock_irqsave(&clocks_lock, flags);
65 clk_gpio27_enable(); 60 if (clk->enabled++ == 0)
66 spin_unlock_irqrestore(&clocks_lock, flags); 61 clk->ops->enable(clk);
62 spin_unlock_irqrestore(&clocks_lock, flags);
63 }
64
67 return 0; 65 return 0;
68} 66}
69EXPORT_SYMBOL(clk_enable); 67EXPORT_SYMBOL(clk_enable);
@@ -72,17 +70,31 @@ void clk_disable(struct clk *clk)
72{ 70{
73 unsigned long flags; 71 unsigned long flags;
74 72
75 WARN_ON(clk->enabled == 0); 73 if (clk) {
76 74 WARN_ON(clk->enabled == 0);
77 spin_lock_irqsave(&clocks_lock, flags); 75 spin_lock_irqsave(&clocks_lock, flags);
78 if (--clk->enabled == 0) 76 if (--clk->enabled == 0)
79 clk_gpio27_disable(); 77 clk->ops->disable(clk);
80 spin_unlock_irqrestore(&clocks_lock, flags); 78 spin_unlock_irqrestore(&clocks_lock, flags);
79 }
81} 80}
82EXPORT_SYMBOL(clk_disable); 81EXPORT_SYMBOL(clk_disable);
83 82
84unsigned long clk_get_rate(struct clk *clk) 83const struct clkops clk_gpio27_ops = {
84 .enable = clk_gpio27_enable,
85 .disable = clk_gpio27_disable,
86};
87
88static DEFINE_CLK(gpio27, &clk_gpio27_ops);
89
90static struct clk_lookup sa11xx_clkregs[] = {
91 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
92 CLKDEV_INIT("sa1100-rtc", NULL, NULL),
93};
94
95static int __init sa11xx_clk_init(void)
85{ 96{
86 return 3686400; 97 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
98 return 0;
87} 99}
88EXPORT_SYMBOL(clk_get_rate); 100core_initcall(sa11xx_clk_init);