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-rw-r--r--arch/arm/mach-s5pv310/clock.c82
-rw-r--r--arch/arm/mach-s5pv310/cpu.c10
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h11
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h16
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h59
-rw-r--r--arch/arm/mach-s5pv310/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pv310/platsmp.c2
7 files changed, 126 insertions, 56 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 77f2b4d85e6b..26a0f03df8ea 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
30 .rate = 27000000, 30 .rate = 27000000,
31}; 31};
32 32
33static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34{
35 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36}
37
38static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39{
40 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41}
42
33/* Core list of CMU_CPU side */ 43/* Core list of CMU_CPU side */
34 44
35static struct clksrc_clk clk_mout_apll = { 45static struct clksrc_clk clk_mout_apll = {
@@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
39 }, 49 },
40 .sources = &clk_src_apll, 50 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 51 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
52};
53
54static struct clksrc_clk clk_sclk_apll = {
55 .clk = {
56 .name = "sclk_apll",
57 .id = -1,
58 .parent = &clk_mout_apll.clk,
59 },
42 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 60 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
43}; 61};
44 62
@@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
61}; 79};
62 80
63static struct clk *clkset_moutcore_list[] = { 81static struct clk *clkset_moutcore_list[] = {
64 [0] = &clk_mout_apll.clk, 82 [0] = &clk_sclk_apll.clk,
65 [1] = &clk_mout_mpll.clk, 83 [1] = &clk_mout_mpll.clk,
66}; 84};
67 85
@@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
154 172
155static struct clk *clkset_corebus_list[] = { 173static struct clk *clkset_corebus_list[] = {
156 [0] = &clk_mout_mpll.clk, 174 [0] = &clk_mout_mpll.clk,
157 [1] = &clk_mout_apll.clk, 175 [1] = &clk_sclk_apll.clk,
158}; 176};
159 177
160static struct clksrc_sources clkset_mout_corebus = { 178static struct clksrc_sources clkset_mout_corebus = {
@@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
220 238
221static struct clk *clkset_aclk_top_list[] = { 239static struct clk *clkset_aclk_top_list[] = {
222 [0] = &clk_mout_mpll.clk, 240 [0] = &clk_mout_mpll.clk,
223 [1] = &clk_mout_apll.clk, 241 [1] = &clk_sclk_apll.clk,
224}; 242};
225 243
226static struct clksrc_sources clkset_aclk_200 = { 244static struct clksrc_sources clkset_aclk_200 = {
@@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
321 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 339 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
322}; 340};
323 341
324static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
325{
326 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
327}
328
329static struct clk init_clocks_disable[] = { 342static struct clk init_clocks_disable[] = {
330 { 343 {
331 .name = "timers", 344 .name = "timers",
@@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
337}; 350};
338 351
339static struct clk init_clocks[] = { 352static struct clk init_clocks[] = {
340 /* Nothing here yet */ 353 {
354 .name = "uart",
355 .id = 0,
356 .enable = s5pv310_clk_ip_peril_ctrl,
357 .ctrlbit = (1 << 0),
358 }, {
359 .name = "uart",
360 .id = 1,
361 .enable = s5pv310_clk_ip_peril_ctrl,
362 .ctrlbit = (1 << 1),
363 }, {
364 .name = "uart",
365 .id = 2,
366 .enable = s5pv310_clk_ip_peril_ctrl,
367 .ctrlbit = (1 << 2),
368 }, {
369 .name = "uart",
370 .id = 3,
371 .enable = s5pv310_clk_ip_peril_ctrl,
372 .ctrlbit = (1 << 3),
373 }, {
374 .name = "uart",
375 .id = 4,
376 .enable = s5pv310_clk_ip_peril_ctrl,
377 .ctrlbit = (1 << 4),
378 }, {
379 .name = "uart",
380 .id = 5,
381 .enable = s5pv310_clk_ip_peril_ctrl,
382 .ctrlbit = (1 << 5),
383 }
341}; 384};
342 385
343static struct clk *clkset_group_list[] = { 386static struct clk *clkset_group_list[] = {
@@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
359 .clk = { 402 .clk = {
360 .name = "uclk1", 403 .name = "uclk1",
361 .id = 0, 404 .id = 0,
405 .enable = s5pv310_clksrc_mask_peril0_ctrl,
362 .ctrlbit = (1 << 0), 406 .ctrlbit = (1 << 0),
363 .enable = s5pv310_clk_ip_peril_ctrl,
364 }, 407 },
365 .sources = &clkset_group, 408 .sources = &clkset_group,
366 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, 409 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
369 .clk = { 412 .clk = {
370 .name = "uclk1", 413 .name = "uclk1",
371 .id = 1, 414 .id = 1,
372 .enable = s5pv310_clk_ip_peril_ctrl, 415 .enable = s5pv310_clksrc_mask_peril0_ctrl,
373 .ctrlbit = (1 << 1), 416 .ctrlbit = (1 << 4),
374 }, 417 },
375 .sources = &clkset_group, 418 .sources = &clkset_group,
376 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, 419 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
379 .clk = { 422 .clk = {
380 .name = "uclk1", 423 .name = "uclk1",
381 .id = 2, 424 .id = 2,
382 .enable = s5pv310_clk_ip_peril_ctrl, 425 .enable = s5pv310_clksrc_mask_peril0_ctrl,
383 .ctrlbit = (1 << 2), 426 .ctrlbit = (1 << 8),
384 }, 427 },
385 .sources = &clkset_group, 428 .sources = &clkset_group,
386 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, 429 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
389 .clk = { 432 .clk = {
390 .name = "uclk1", 433 .name = "uclk1",
391 .id = 3, 434 .id = 3,
392 .enable = s5pv310_clk_ip_peril_ctrl, 435 .enable = s5pv310_clksrc_mask_peril0_ctrl,
393 .ctrlbit = (1 << 3), 436 .ctrlbit = (1 << 12),
394 }, 437 },
395 .sources = &clkset_group, 438 .sources = &clkset_group,
396 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, 439 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
399 .clk = { 442 .clk = {
400 .name = "sclk_pwm", 443 .name = "sclk_pwm",
401 .id = -1, 444 .id = -1,
402 .enable = s5pv310_clk_ip_peril_ctrl, 445 .enable = s5pv310_clksrc_mask_peril0_ctrl,
403 .ctrlbit = (1 << 24), 446 .ctrlbit = (1 << 24),
404 }, 447 },
405 .sources = &clkset_group, 448 .sources = &clkset_group,
@@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
411/* Clock initialization code */ 454/* Clock initialization code */
412static struct clksrc_clk *sysclks[] = { 455static struct clksrc_clk *sysclks[] = {
413 &clk_mout_apll, 456 &clk_mout_apll,
457 &clk_sclk_apll,
414 &clk_mout_epll, 458 &clk_mout_epll,
415 &clk_mout_mpll, 459 &clk_mout_mpll,
416 &clk_moutcore, 460 &clk_moutcore,
@@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
470 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); 514 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
471 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); 515 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
472 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), 516 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
473 __raw_readl(S5P_EPLL_CON1), pll_4500); 517 __raw_readl(S5P_EPLL_CON1), pll_4600);
474 518
475 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 519 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
476 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 520 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
477 __raw_readl(S5P_VPLL_CON1), pll_4502); 521 __raw_readl(S5P_VPLL_CON1), pll_4650);
478 522
479 clk_fout_apll.rate = apll; 523 clk_fout_apll.rate = apll;
480 clk_fout_mpll.rate = mpll; 524 clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 196c9f12ed85..e5b261a99ab2 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
46 .length = SZ_4K, 46 .length = SZ_4K,
47 .type = MT_DEVICE, 47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long)S5P_VA_SYSRAM,
50 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)S5P_VA_CMU,
55 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
56 .length = SZ_128K,
57 .type = MT_DEVICE,
48 }, 58 },
49}; 59};
50 60
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 56885ca3773c..4cdedda6e652 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -15,12 +15,14 @@
15 15
16#include <plat/irqs.h> 16#include <plat/irqs.h>
17 17
18/* Private Peripheral Interrupt */ 18/* PPI: Private Peripheral Interrupt */
19
19#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
20 21
21#define IRQ_LOCALTIMER IRQ_PPI(13) 22#define IRQ_LOCALTIMER IRQ_PPI(13)
22 23
23/* Shared Peripheral Interrupt */ 24/* SPI: Shared Peripheral Interrupt */
25
24#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) S5P_IRQ(x+32)
25 27
26#define IRQ_EINT0 IRQ_SPI(40) 28#define IRQ_EINT0 IRQ_SPI(40)
@@ -36,7 +38,7 @@
36#define IRQ_PCIE IRQ_SPI(50) 38#define IRQ_PCIE IRQ_SPI(50)
37#define IRQ_SYSTEM_TIMER IRQ_SPI(51) 39#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
38#define IRQ_MFC IRQ_SPI(52) 40#define IRQ_MFC IRQ_SPI(52)
39#define IRQ_WTD IRQ_SPI(53) 41#define IRQ_WDT IRQ_SPI(53)
40#define IRQ_AUDIO_SS IRQ_SPI(54) 42#define IRQ_AUDIO_SS IRQ_SPI(54)
41#define IRQ_AC97 IRQ_SPI(55) 43#define IRQ_AC97 IRQ_SPI(55)
42#define IRQ_SPDIF IRQ_SPI(56) 44#define IRQ_SPDIF IRQ_SPI(56)
@@ -67,8 +69,9 @@
67#define IRQ_IIC COMBINER_IRQ(27, 0) 69#define IRQ_IIC COMBINER_IRQ(27, 0)
68 70
69/* Set the default NR_IRQS */ 71/* Set the default NR_IRQS */
72
70#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) 73#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
71 74
72#define MAX_COMBINER_NR 39 75#define MAX_COMBINER_NR 39
73 76
74#endif /* ASM_ARCH_IRQS_H */ 77#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 87697c9fca5b..213e1101a3b3 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -23,12 +23,16 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define S5PV310_PA_SYSRAM (0x02025000)
27
26#define S5PV310_PA_CHIPID (0x10000000) 28#define S5PV310_PA_CHIPID (0x10000000)
27#define S5P_PA_CHIPID S5PV310_PA_CHIPID 29#define S5P_PA_CHIPID S5PV310_PA_CHIPID
28 30
29#define S5PV310_PA_SYSCON (0x10020000) 31#define S5PV310_PA_SYSCON (0x10020000)
30#define S5P_PA_SYSCON S5PV310_PA_SYSCON 32#define S5P_PA_SYSCON S5PV310_PA_SYSCON
31 33
34#define S5PV310_PA_CMU (0x10030000)
35
32#define S5PV310_PA_WATCHDOG (0x10060000) 36#define S5PV310_PA_WATCHDOG (0x10060000)
33 37
34#define S5PV310_PA_COMBINER (0x10448000) 38#define S5PV310_PA_COMBINER (0x10448000)
@@ -39,8 +43,12 @@
39#define S5PV310_PA_GIC_DIST (0x10501000) 43#define S5PV310_PA_GIC_DIST (0x10501000)
40#define S5PV310_PA_L2CC (0x10502000) 44#define S5PV310_PA_L2CC (0x10502000)
41 45
42#define S5PV310_PA_GPIO (0x11000000) 46#define S5PV310_PA_GPIO1 (0x11400000)
43#define S5P_PA_GPIO S5PV310_PA_GPIO 47#define S5PV310_PA_GPIO2 (0x11000000)
48#define S5PV310_PA_GPIO3 (0x03860000)
49#define S5P_PA_GPIO S5PV310_PA_GPIO1
50
51#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
44 52
45#define S5PV310_PA_UART (0x13800000) 53#define S5PV310_PA_UART (0x13800000)
46 54
@@ -63,6 +71,10 @@
63 71
64/* compatibiltiy defines. */ 72/* compatibiltiy defines. */
65#define S3C_PA_UART S5PV310_PA_UART 73#define S3C_PA_UART S5PV310_PA_UART
74#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
75#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
76#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
77#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
66#define S3C_PA_IIC S5PV310_PA_IIC0 78#define S3C_PA_IIC S5PV310_PA_IIC0
67#define S3C_PA_WDT S5PV310_PA_WATCHDOG 79#define S3C_PA_WDT S5PV310_PA_WATCHDOG
68 80
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 59e3a7e94d80..4013553cd9be 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -15,48 +15,49 @@
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800) 20#define S5P_INFORM0 S5P_CLKREG(0x800)
21 21
22#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110) 22#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114) 23#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120) 24#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
25#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124) 25#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
26 26
27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210) 27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214) 28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
29 29
30#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250) 30#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
31 31
32#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510) 32#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
33 33
34#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550) 34#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
35#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554) 35#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
36#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558) 36#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
37#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C) 37#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560) 38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564) 39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
40 40
41#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950) 41#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
42 42
43#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200) 43#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
44 44
45#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500) 45#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
46#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
46 47
47#define S5P_APLL_LOCK S5P_CLKREG(0x24000) 48#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
48#define S5P_MPLL_LOCK S5P_CLKREG(0x24004) 49#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
49#define S5P_APLL_CON0 S5P_CLKREG(0x24100) 50#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
50#define S5P_APLL_CON1 S5P_CLKREG(0x24104) 51#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
51#define S5P_MPLL_CON0 S5P_CLKREG(0x24108) 52#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
52#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C) 53#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
53 54
54#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200) 55#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
55#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400) 56#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
56 57
57#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500) 58#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
58#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600) 59#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
59 60
60#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800) 61#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
61 62
62#endif /* __ASM_ARCH_REGS_CLOCK_H */ 63#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
index 3f565ebb7daa..256f221edf3a 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__ 18#define __ASM_ARCH_VMALLOC_H __FILE__
19 19
20#define VMALLOC_END (0xF0000000) 20#define VMALLOC_END (0xF0000000UL)
21 21
22#endif /* __ASM_ARCH_VMALLOC_H */ 22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
index fe9469abd006..d357c198edee 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
187 * until it receives a soft interrupt, and then the 187 * until it receives a soft interrupt, and then the
188 * secondary CPU branches to this address. 188 * secondary CPU branches to this address.
189 */ 189 */
190 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0); 190 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
191 } 191 }
192} 192}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 12:29:03 -0500