aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv310
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pv310')
-rw-r--r--arch/arm/mach-s5pv310/Kconfig151
-rw-r--r--arch/arm/mach-s5pv310/Makefile43
-rw-r--r--arch/arm/mach-s5pv310/Makefile.boot2
-rw-r--r--arch/arm/mach-s5pv310/clock.c1122
-rw-r--r--arch/arm/mach-s5pv310/cpu.c202
-rw-r--r--arch/arm/mach-s5pv310/cpufreq.c580
-rw-r--r--arch/arm/mach-s5pv310/dev-audio.c364
-rw-r--r--arch/arm/mach-s5pv310/dev-pd.c139
-rw-r--r--arch/arm/mach-s5pv310/dev-sysmmu.c187
-rw-r--r--arch/arm/mach-s5pv310/dma.c168
-rw-r--r--arch/arm/mach-s5pv310/gpiolib.c304
-rw-r--r--arch/arm/mach-s5pv310/headsmp.S41
-rw-r--r--arch/arm/mach-s5pv310/hotplug.c130
-rw-r--r--arch/arm/mach-s5pv310/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-s5pv310/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/entry-macro.S84
-rw-r--r--arch/arm/mach-s5pv310/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-s5pv310/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5pv310/include/mach/io.h26
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h146
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/memory.h22
-rw-r--r--arch/arm/mach-s5pv310/include/mach/pwm-clock.h70
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h167
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-irq.h19
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-mem.h23
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-pmu.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h24
-rw-r--r--arch/arm/mach-s5pv310/include/mach/smp.h19
-rw-r--r--arch/arm/mach-s5pv310/include/mach/sysmmu.h122
-rw-r--r--arch/arm/mach-s5pv310/include/mach/system.h22
-rw-r--r--arch/arm/mach-s5pv310/include/mach/timex.h29
-rw-r--r--arch/arm/mach-s5pv310/include/mach/uncompress.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/vmalloc.h22
-rw-r--r--arch/arm/mach-s5pv310/init.c41
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c127
-rw-r--r--arch/arm/mach-s5pv310/irq-eint.c229
-rw-r--r--arch/arm/mach-s5pv310/localtimer.c25
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkc210.c223
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkv310.c224
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c237
-rw-r--r--arch/arm/mach-s5pv310/platsmp.c172
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c0.c26
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c1.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c2.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c3.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c4.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c5.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c6.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c7.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci-gpio.c152
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci.c69
-rw-r--r--arch/arm/mach-s5pv310/time.c283
54 files changed, 0 insertions, 6657 deletions
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
deleted file mode 100644
index b2a9acc5185f..000000000000
--- a/arch/arm/mach-s5pv310/Kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
1# arch/arm/mach-s5pv310/Kconfig
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the S5PV310
9
10if ARCH_S5PV310
11
12config CPU_S5PV310
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable S5PV310 CPU support
17
18config S5PV310_DEV_PD
19 bool
20 help
21 Compile in platform device definitions for Power Domain
22
23config S5PV310_SETUP_I2C1
24 bool
25 help
26 Common setup code for i2c bus 1.
27
28config S5PV310_SETUP_I2C2
29 bool
30 help
31 Common setup code for i2c bus 2.
32
33config S5PV310_SETUP_I2C3
34 bool
35 help
36 Common setup code for i2c bus 3.
37
38config S5PV310_SETUP_I2C4
39 bool
40 help
41 Common setup code for i2c bus 4.
42
43config S5PV310_SETUP_I2C5
44 bool
45 help
46 Common setup code for i2c bus 5.
47
48config S5PV310_SETUP_I2C6
49 bool
50 help
51 Common setup code for i2c bus 6.
52
53config S5PV310_SETUP_I2C7
54 bool
55 help
56 Common setup code for i2c bus 7.
57
58config S5PV310_SETUP_SDHCI
59 bool
60 select S5PV310_SETUP_SDHCI_GPIO
61 help
62 Internal helper functions for S5PV310 based SDHCI systems.
63
64config S5PV310_SETUP_SDHCI_GPIO
65 bool
66 help
67 Common setup code for SDHCI gpio.
68
69config S5PV310_DEV_SYSMMU
70 bool
71 help
72 Common setup code for SYSTEM MMU in S5PV310
73
74# machine support
75
76menu "S5PC210 Machines"
77
78config MACH_SMDKC210
79 bool "SMDKC210"
80 select CPU_S5PV310
81 select S3C_DEV_RTC
82 select S3C_DEV_WDT
83 select S3C_DEV_I2C1
84 select S3C_DEV_HSMMC
85 select S3C_DEV_HSMMC1
86 select S3C_DEV_HSMMC2
87 select S3C_DEV_HSMMC3
88 select S5PV310_DEV_PD
89 select S5PV310_SETUP_I2C1
90 select S5PV310_SETUP_SDHCI
91 select S5PV310_DEV_SYSMMU
92 help
93 Machine support for Samsung SMDKC210
94 S5PC210(MCP) is one of package option of S5PV310
95
96config MACH_UNIVERSAL_C210
97 bool "Mobile UNIVERSAL_C210 Board"
98 select CPU_S5PV310
99 select S5P_DEV_ONENAND
100 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC2
102 select S3C_DEV_HSMMC3
103 select S5PV310_SETUP_SDHCI
104 select S3C_DEV_I2C1
105 select S5PV310_SETUP_I2C1
106 help
107 Machine support for Samsung Mobile Universal S5PC210 Reference
108 Board. S5PC210(MCP) is one of package option of S5PV310
109
110endmenu
111
112menu "S5PV310 Machines"
113
114config MACH_SMDKV310
115 bool "SMDKV310"
116 select CPU_S5PV310
117 select S3C_DEV_RTC
118 select S3C_DEV_WDT
119 select S3C_DEV_I2C1
120 select S3C_DEV_HSMMC
121 select S3C_DEV_HSMMC1
122 select S3C_DEV_HSMMC2
123 select S3C_DEV_HSMMC3
124 select S5PV310_DEV_PD
125 select S5PV310_DEV_SYSMMU
126 select S5PV310_SETUP_I2C1
127 select S5PV310_SETUP_SDHCI
128 help
129 Machine support for Samsung SMDKV310
130
131endmenu
132
133comment "Configuration for HSMMC bus width"
134
135menu "Use 8-bit bus width"
136
137config S5PV310_SDHCI_CH0_8BIT
138 bool "Channel 0 with 8-bit bus"
139 help
140 Support HSMMC Channel 0 8-bit bus.
141 If selected, Channel 1 is disabled.
142
143config S5PV310_SDHCI_CH2_8BIT
144 bool "Channel 2 with 8-bit bus"
145 help
146 Support HSMMC Channel 2 8-bit bus.
147 If selected, Channel 3 is disabled.
148
149endmenu
150
151endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
deleted file mode 100644
index 036fb383b830..000000000000
--- a/arch/arm/mach-s5pv310/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
1# arch/arm/mach-s5pv310/Makefile
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5PV310 system
14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
18
19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
20obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
22
23# machine support
24
25obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
26obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
27obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
28
29# device support
30
31obj-y += dev-audio.o
32obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
33obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
34
35obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
36obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
37obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
38obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
39obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
40obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
41obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
42obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
43obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-s5pv310/Makefile.boot
deleted file mode 100644
index d65956ffb43d..000000000000
--- a/arch/arm/mach-s5pv310/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
deleted file mode 100644
index fc7c2f8d165e..000000000000
--- a/arch/arm/mach-s5pv310/clock.c
+++ /dev/null
@@ -1,1122 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/io.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
29 .id = -1,
30 .rate = 27000000,
31};
32
33static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
35 .id = -1,
36};
37
38static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
40 .id = -1,
41 .rate = 27000000,
42};
43
44static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
46 .id = -1,
47};
48
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52}
53
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57}
58
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62}
63
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67}
68
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72}
73
74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
75{
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
77}
78
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82}
83
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87}
88
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
90{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92}
93
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97}
98
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102}
103
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107}
108
109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
110{
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
112}
113
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117}
118
119/* Core list of CMU_CPU side */
120
121static struct clksrc_clk clk_mout_apll = {
122 .clk = {
123 .name = "mout_apll",
124 .id = -1,
125 },
126 .sources = &clk_src_apll,
127 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
128};
129
130static struct clksrc_clk clk_sclk_apll = {
131 .clk = {
132 .name = "sclk_apll",
133 .id = -1,
134 .parent = &clk_mout_apll.clk,
135 },
136 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
137};
138
139static struct clksrc_clk clk_mout_epll = {
140 .clk = {
141 .name = "mout_epll",
142 .id = -1,
143 },
144 .sources = &clk_src_epll,
145 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
146};
147
148static struct clksrc_clk clk_mout_mpll = {
149 .clk = {
150 .name = "mout_mpll",
151 .id = -1,
152 },
153 .sources = &clk_src_mpll,
154 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
155};
156
157static struct clk *clkset_moutcore_list[] = {
158 [0] = &clk_mout_apll.clk,
159 [1] = &clk_mout_mpll.clk,
160};
161
162static struct clksrc_sources clkset_moutcore = {
163 .sources = clkset_moutcore_list,
164 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
165};
166
167static struct clksrc_clk clk_moutcore = {
168 .clk = {
169 .name = "moutcore",
170 .id = -1,
171 },
172 .sources = &clkset_moutcore,
173 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
174};
175
176static struct clksrc_clk clk_coreclk = {
177 .clk = {
178 .name = "core_clk",
179 .id = -1,
180 .parent = &clk_moutcore.clk,
181 },
182 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
183};
184
185static struct clksrc_clk clk_armclk = {
186 .clk = {
187 .name = "armclk",
188 .id = -1,
189 .parent = &clk_coreclk.clk,
190 },
191};
192
193static struct clksrc_clk clk_aclk_corem0 = {
194 .clk = {
195 .name = "aclk_corem0",
196 .id = -1,
197 .parent = &clk_coreclk.clk,
198 },
199 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
200};
201
202static struct clksrc_clk clk_aclk_cores = {
203 .clk = {
204 .name = "aclk_cores",
205 .id = -1,
206 .parent = &clk_coreclk.clk,
207 },
208 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
209};
210
211static struct clksrc_clk clk_aclk_corem1 = {
212 .clk = {
213 .name = "aclk_corem1",
214 .id = -1,
215 .parent = &clk_coreclk.clk,
216 },
217 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
218};
219
220static struct clksrc_clk clk_periphclk = {
221 .clk = {
222 .name = "periphclk",
223 .id = -1,
224 .parent = &clk_coreclk.clk,
225 },
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
227};
228
229/* Core list of CMU_CORE side */
230
231static struct clk *clkset_corebus_list[] = {
232 [0] = &clk_mout_mpll.clk,
233 [1] = &clk_sclk_apll.clk,
234};
235
236static struct clksrc_sources clkset_mout_corebus = {
237 .sources = clkset_corebus_list,
238 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
239};
240
241static struct clksrc_clk clk_mout_corebus = {
242 .clk = {
243 .name = "mout_corebus",
244 .id = -1,
245 },
246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
248};
249
250static struct clksrc_clk clk_sclk_dmc = {
251 .clk = {
252 .name = "sclk_dmc",
253 .id = -1,
254 .parent = &clk_mout_corebus.clk,
255 },
256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
257};
258
259static struct clksrc_clk clk_aclk_cored = {
260 .clk = {
261 .name = "aclk_cored",
262 .id = -1,
263 .parent = &clk_sclk_dmc.clk,
264 },
265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
266};
267
268static struct clksrc_clk clk_aclk_corep = {
269 .clk = {
270 .name = "aclk_corep",
271 .id = -1,
272 .parent = &clk_aclk_cored.clk,
273 },
274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
275};
276
277static struct clksrc_clk clk_aclk_acp = {
278 .clk = {
279 .name = "aclk_acp",
280 .id = -1,
281 .parent = &clk_mout_corebus.clk,
282 },
283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
284};
285
286static struct clksrc_clk clk_pclk_acp = {
287 .clk = {
288 .name = "pclk_acp",
289 .id = -1,
290 .parent = &clk_aclk_acp.clk,
291 },
292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
293};
294
295/* Core list of CMU_TOP side */
296
297static struct clk *clkset_aclk_top_list[] = {
298 [0] = &clk_mout_mpll.clk,
299 [1] = &clk_sclk_apll.clk,
300};
301
302static struct clksrc_sources clkset_aclk = {
303 .sources = clkset_aclk_top_list,
304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
305};
306
307static struct clksrc_clk clk_aclk_200 = {
308 .clk = {
309 .name = "aclk_200",
310 .id = -1,
311 },
312 .sources = &clkset_aclk,
313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
315};
316
317static struct clksrc_clk clk_aclk_100 = {
318 .clk = {
319 .name = "aclk_100",
320 .id = -1,
321 },
322 .sources = &clkset_aclk,
323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
325};
326
327static struct clksrc_clk clk_aclk_160 = {
328 .clk = {
329 .name = "aclk_160",
330 .id = -1,
331 },
332 .sources = &clkset_aclk,
333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
335};
336
337static struct clksrc_clk clk_aclk_133 = {
338 .clk = {
339 .name = "aclk_133",
340 .id = -1,
341 },
342 .sources = &clkset_aclk,
343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
345};
346
347static struct clk *clkset_vpllsrc_list[] = {
348 [0] = &clk_fin_vpll,
349 [1] = &clk_sclk_hdmi27m,
350};
351
352static struct clksrc_sources clkset_vpllsrc = {
353 .sources = clkset_vpllsrc_list,
354 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
355};
356
357static struct clksrc_clk clk_vpllsrc = {
358 .clk = {
359 .name = "vpll_src",
360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0),
363 },
364 .sources = &clkset_vpllsrc,
365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
366};
367
368static struct clk *clkset_sclk_vpll_list[] = {
369 [0] = &clk_vpllsrc.clk,
370 [1] = &clk_fout_vpll,
371};
372
373static struct clksrc_sources clkset_sclk_vpll = {
374 .sources = clkset_sclk_vpll_list,
375 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
376};
377
378static struct clksrc_clk clk_sclk_vpll = {
379 .clk = {
380 .name = "sclk_vpll",
381 .id = -1,
382 },
383 .sources = &clkset_sclk_vpll,
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
385};
386
387static struct clk init_clocks_off[] = {
388 {
389 .name = "timers",
390 .id = -1,
391 .parent = &clk_aclk_100.clk,
392 .enable = s5pv310_clk_ip_peril_ctrl,
393 .ctrlbit = (1<<24),
394 }, {
395 .name = "csis",
396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "csis",
401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5),
404 }, {
405 .name = "fimc",
406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0),
409 }, {
410 .name = "fimc",
411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1),
414 }, {
415 .name = "fimc",
416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "fimc",
421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3),
424 }, {
425 .name = "fimd",
426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0),
429 }, {
430 .name = "fimd",
431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0),
434 }, {
435 .name = "hsmmc",
436 .id = 0,
437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5),
440 }, {
441 .name = "hsmmc",
442 .id = 1,
443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6),
446 }, {
447 .name = "hsmmc",
448 .id = 2,
449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7),
452 }, {
453 .name = "hsmmc",
454 .id = 3,
455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8),
458 }, {
459 .name = "hsmmc",
460 .id = 4,
461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9),
464 }, {
465 .name = "sata",
466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
469 }, {
470 .name = "pdma",
471 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0),
474 }, {
475 .name = "pdma",
476 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1),
479 }, {
480 .name = "adc",
481 .id = -1,
482 .enable = s5pv310_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15),
484 }, {
485 .name = "rtc",
486 .id = -1,
487 .enable = s5pv310_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15),
489 }, {
490 .name = "watchdog",
491 .id = -1,
492 .enable = s5pv310_clk_ip_perir_ctrl,
493 .ctrlbit = (1 << 14),
494 }, {
495 .name = "usbhost",
496 .id = -1,
497 .enable = s5pv310_clk_ip_fsys_ctrl ,
498 .ctrlbit = (1 << 12),
499 }, {
500 .name = "otg",
501 .id = -1,
502 .enable = s5pv310_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 13),
504 }, {
505 .name = "spi",
506 .id = 0,
507 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 16),
509 }, {
510 .name = "spi",
511 .id = 1,
512 .enable = s5pv310_clk_ip_peril_ctrl,
513 .ctrlbit = (1 << 17),
514 }, {
515 .name = "spi",
516 .id = 2,
517 .enable = s5pv310_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 18),
519 }, {
520 .name = "iis",
521 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19),
524 }, {
525 .name = "iis",
526 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20),
529 }, {
530 .name = "iis",
531 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21),
534 }, {
535 .name = "ac97",
536 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27),
539 }, {
540 .name = "fimg2d",
541 .id = -1,
542 .enable = s5pv310_clk_ip_image_ctrl,
543 .ctrlbit = (1 << 0),
544 }, {
545 .name = "i2c",
546 .id = 0,
547 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 6),
550 }, {
551 .name = "i2c",
552 .id = 1,
553 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 7),
556 }, {
557 .name = "i2c",
558 .id = 2,
559 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 8),
562 }, {
563 .name = "i2c",
564 .id = 3,
565 .parent = &clk_aclk_100.clk,
566 .enable = s5pv310_clk_ip_peril_ctrl,
567 .ctrlbit = (1 << 9),
568 }, {
569 .name = "i2c",
570 .id = 4,
571 .parent = &clk_aclk_100.clk,
572 .enable = s5pv310_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 10),
574 }, {
575 .name = "i2c",
576 .id = 5,
577 .parent = &clk_aclk_100.clk,
578 .enable = s5pv310_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 11),
580 }, {
581 .name = "i2c",
582 .id = 6,
583 .parent = &clk_aclk_100.clk,
584 .enable = s5pv310_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 12),
586 }, {
587 .name = "i2c",
588 .id = 7,
589 .parent = &clk_aclk_100.clk,
590 .enable = s5pv310_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 13),
592 },
593};
594
595static struct clk init_clocks[] = {
596 {
597 .name = "uart",
598 .id = 0,
599 .enable = s5pv310_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 0),
601 }, {
602 .name = "uart",
603 .id = 1,
604 .enable = s5pv310_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 1),
606 }, {
607 .name = "uart",
608 .id = 2,
609 .enable = s5pv310_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 2),
611 }, {
612 .name = "uart",
613 .id = 3,
614 .enable = s5pv310_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 3),
616 }, {
617 .name = "uart",
618 .id = 4,
619 .enable = s5pv310_clk_ip_peril_ctrl,
620 .ctrlbit = (1 << 4),
621 }, {
622 .name = "uart",
623 .id = 5,
624 .enable = s5pv310_clk_ip_peril_ctrl,
625 .ctrlbit = (1 << 5),
626 }
627};
628
629static struct clk *clkset_group_list[] = {
630 [0] = &clk_ext_xtal_mux,
631 [1] = &clk_xusbxti,
632 [2] = &clk_sclk_hdmi27m,
633 [3] = &clk_sclk_usbphy0,
634 [4] = &clk_sclk_usbphy1,
635 [5] = &clk_sclk_hdmiphy,
636 [6] = &clk_mout_mpll.clk,
637 [7] = &clk_mout_epll.clk,
638 [8] = &clk_sclk_vpll.clk,
639};
640
641static struct clksrc_sources clkset_group = {
642 .sources = clkset_group_list,
643 .nr_sources = ARRAY_SIZE(clkset_group_list),
644};
645
646static struct clk *clkset_mout_g2d0_list[] = {
647 [0] = &clk_mout_mpll.clk,
648 [1] = &clk_sclk_apll.clk,
649};
650
651static struct clksrc_sources clkset_mout_g2d0 = {
652 .sources = clkset_mout_g2d0_list,
653 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
654};
655
656static struct clksrc_clk clk_mout_g2d0 = {
657 .clk = {
658 .name = "mout_g2d0",
659 .id = -1,
660 },
661 .sources = &clkset_mout_g2d0,
662 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
663};
664
665static struct clk *clkset_mout_g2d1_list[] = {
666 [0] = &clk_mout_epll.clk,
667 [1] = &clk_sclk_vpll.clk,
668};
669
670static struct clksrc_sources clkset_mout_g2d1 = {
671 .sources = clkset_mout_g2d1_list,
672 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
673};
674
675static struct clksrc_clk clk_mout_g2d1 = {
676 .clk = {
677 .name = "mout_g2d1",
678 .id = -1,
679 },
680 .sources = &clkset_mout_g2d1,
681 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
682};
683
684static struct clk *clkset_mout_g2d_list[] = {
685 [0] = &clk_mout_g2d0.clk,
686 [1] = &clk_mout_g2d1.clk,
687};
688
689static struct clksrc_sources clkset_mout_g2d = {
690 .sources = clkset_mout_g2d_list,
691 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
692};
693
694static struct clksrc_clk clk_dout_mmc0 = {
695 .clk = {
696 .name = "dout_mmc0",
697 .id = -1,
698 },
699 .sources = &clkset_group,
700 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
701 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
702};
703
704static struct clksrc_clk clk_dout_mmc1 = {
705 .clk = {
706 .name = "dout_mmc1",
707 .id = -1,
708 },
709 .sources = &clkset_group,
710 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
711 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
712};
713
714static struct clksrc_clk clk_dout_mmc2 = {
715 .clk = {
716 .name = "dout_mmc2",
717 .id = -1,
718 },
719 .sources = &clkset_group,
720 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
721 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
722};
723
724static struct clksrc_clk clk_dout_mmc3 = {
725 .clk = {
726 .name = "dout_mmc3",
727 .id = -1,
728 },
729 .sources = &clkset_group,
730 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
731 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
732};
733
734static struct clksrc_clk clk_dout_mmc4 = {
735 .clk = {
736 .name = "dout_mmc4",
737 .id = -1,
738 },
739 .sources = &clkset_group,
740 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
741 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
742};
743
744static struct clksrc_clk clksrcs[] = {
745 {
746 .clk = {
747 .name = "uclk1",
748 .id = 0,
749 .enable = s5pv310_clksrc_mask_peril0_ctrl,
750 .ctrlbit = (1 << 0),
751 },
752 .sources = &clkset_group,
753 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
754 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
755 }, {
756 .clk = {
757 .name = "uclk1",
758 .id = 1,
759 .enable = s5pv310_clksrc_mask_peril0_ctrl,
760 .ctrlbit = (1 << 4),
761 },
762 .sources = &clkset_group,
763 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
764 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
765 }, {
766 .clk = {
767 .name = "uclk1",
768 .id = 2,
769 .enable = s5pv310_clksrc_mask_peril0_ctrl,
770 .ctrlbit = (1 << 8),
771 },
772 .sources = &clkset_group,
773 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
774 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
775 }, {
776 .clk = {
777 .name = "uclk1",
778 .id = 3,
779 .enable = s5pv310_clksrc_mask_peril0_ctrl,
780 .ctrlbit = (1 << 12),
781 },
782 .sources = &clkset_group,
783 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
784 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
785 }, {
786 .clk = {
787 .name = "sclk_pwm",
788 .id = -1,
789 .enable = s5pv310_clksrc_mask_peril0_ctrl,
790 .ctrlbit = (1 << 24),
791 },
792 .sources = &clkset_group,
793 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
794 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
795 }, {
796 .clk = {
797 .name = "sclk_csis",
798 .id = 0,
799 .enable = s5pv310_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 24),
801 },
802 .sources = &clkset_group,
803 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
804 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
805 }, {
806 .clk = {
807 .name = "sclk_csis",
808 .id = 1,
809 .enable = s5pv310_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 28),
811 },
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
815 }, {
816 .clk = {
817 .name = "sclk_cam",
818 .id = 0,
819 .enable = s5pv310_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 16),
821 },
822 .sources = &clkset_group,
823 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
824 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
825 }, {
826 .clk = {
827 .name = "sclk_cam",
828 .id = 1,
829 .enable = s5pv310_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 20),
831 },
832 .sources = &clkset_group,
833 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
834 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
835 }, {
836 .clk = {
837 .name = "sclk_fimc",
838 .id = 0,
839 .enable = s5pv310_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 0),
841 },
842 .sources = &clkset_group,
843 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
844 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
845 }, {
846 .clk = {
847 .name = "sclk_fimc",
848 .id = 1,
849 .enable = s5pv310_clksrc_mask_cam_ctrl,
850 .ctrlbit = (1 << 4),
851 },
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
855 }, {
856 .clk = {
857 .name = "sclk_fimc",
858 .id = 2,
859 .enable = s5pv310_clksrc_mask_cam_ctrl,
860 .ctrlbit = (1 << 8),
861 },
862 .sources = &clkset_group,
863 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
864 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
865 }, {
866 .clk = {
867 .name = "sclk_fimc",
868 .id = 3,
869 .enable = s5pv310_clksrc_mask_cam_ctrl,
870 .ctrlbit = (1 << 12),
871 },
872 .sources = &clkset_group,
873 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
874 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
875 }, {
876 .clk = {
877 .name = "sclk_fimd",
878 .id = 0,
879 .enable = s5pv310_clksrc_mask_lcd0_ctrl,
880 .ctrlbit = (1 << 0),
881 },
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
885 }, {
886 .clk = {
887 .name = "sclk_fimd",
888 .id = 1,
889 .enable = s5pv310_clksrc_mask_lcd1_ctrl,
890 .ctrlbit = (1 << 0),
891 },
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
895 }, {
896 .clk = {
897 .name = "sclk_sata",
898 .id = -1,
899 .enable = s5pv310_clksrc_mask_fsys_ctrl,
900 .ctrlbit = (1 << 24),
901 },
902 .sources = &clkset_mout_corebus,
903 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
904 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
905 }, {
906 .clk = {
907 .name = "sclk_spi",
908 .id = 0,
909 .enable = s5pv310_clksrc_mask_peril1_ctrl,
910 .ctrlbit = (1 << 16),
911 },
912 .sources = &clkset_group,
913 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
914 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
915 }, {
916 .clk = {
917 .name = "sclk_spi",
918 .id = 1,
919 .enable = s5pv310_clksrc_mask_peril1_ctrl,
920 .ctrlbit = (1 << 20),
921 },
922 .sources = &clkset_group,
923 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
924 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
925 }, {
926 .clk = {
927 .name = "sclk_spi",
928 .id = 2,
929 .enable = s5pv310_clksrc_mask_peril1_ctrl,
930 .ctrlbit = (1 << 24),
931 },
932 .sources = &clkset_group,
933 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
934 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
935 }, {
936 .clk = {
937 .name = "sclk_fimg2d",
938 .id = -1,
939 },
940 .sources = &clkset_mout_g2d,
941 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
942 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
943 }, {
944 .clk = {
945 .name = "sclk_mmc",
946 .id = 0,
947 .parent = &clk_dout_mmc0.clk,
948 .enable = s5pv310_clksrc_mask_fsys_ctrl,
949 .ctrlbit = (1 << 0),
950 },
951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
952 }, {
953 .clk = {
954 .name = "sclk_mmc",
955 .id = 1,
956 .parent = &clk_dout_mmc1.clk,
957 .enable = s5pv310_clksrc_mask_fsys_ctrl,
958 .ctrlbit = (1 << 4),
959 },
960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
961 }, {
962 .clk = {
963 .name = "sclk_mmc",
964 .id = 2,
965 .parent = &clk_dout_mmc2.clk,
966 .enable = s5pv310_clksrc_mask_fsys_ctrl,
967 .ctrlbit = (1 << 8),
968 },
969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
970 }, {
971 .clk = {
972 .name = "sclk_mmc",
973 .id = 3,
974 .parent = &clk_dout_mmc3.clk,
975 .enable = s5pv310_clksrc_mask_fsys_ctrl,
976 .ctrlbit = (1 << 12),
977 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
979 }, {
980 .clk = {
981 .name = "sclk_mmc",
982 .id = 4,
983 .parent = &clk_dout_mmc4.clk,
984 .enable = s5pv310_clksrc_mask_fsys_ctrl,
985 .ctrlbit = (1 << 16),
986 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
988 }
989};
990
991/* Clock initialization code */
992static struct clksrc_clk *sysclks[] = {
993 &clk_mout_apll,
994 &clk_sclk_apll,
995 &clk_mout_epll,
996 &clk_mout_mpll,
997 &clk_moutcore,
998 &clk_coreclk,
999 &clk_armclk,
1000 &clk_aclk_corem0,
1001 &clk_aclk_cores,
1002 &clk_aclk_corem1,
1003 &clk_periphclk,
1004 &clk_mout_corebus,
1005 &clk_sclk_dmc,
1006 &clk_aclk_cored,
1007 &clk_aclk_corep,
1008 &clk_aclk_acp,
1009 &clk_pclk_acp,
1010 &clk_vpllsrc,
1011 &clk_sclk_vpll,
1012 &clk_aclk_200,
1013 &clk_aclk_100,
1014 &clk_aclk_160,
1015 &clk_aclk_133,
1016 &clk_dout_mmc0,
1017 &clk_dout_mmc1,
1018 &clk_dout_mmc2,
1019 &clk_dout_mmc3,
1020 &clk_dout_mmc4,
1021};
1022
1023static int xtal_rate;
1024
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
1026{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028}
1029
1030static struct clk_ops s5pv310_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate,
1032};
1033
1034void __init_or_cpufreq s5pv310_setup_clocks(void)
1035{
1036 struct clk *xtal_clk;
1037 unsigned long apll;
1038 unsigned long mpll;
1039 unsigned long epll;
1040 unsigned long vpll;
1041 unsigned long vpllsrc;
1042 unsigned long xtal;
1043 unsigned long armclk;
1044 unsigned long sclk_dmc;
1045 unsigned long aclk_200;
1046 unsigned long aclk_100;
1047 unsigned long aclk_160;
1048 unsigned long aclk_133;
1049 unsigned int ptr;
1050
1051 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1052
1053 xtal_clk = clk_get(NULL, "xtal");
1054 BUG_ON(IS_ERR(xtal_clk));
1055
1056 xtal = clk_get_rate(xtal_clk);
1057
1058 xtal_rate = xtal;
1059
1060 clk_put(xtal_clk);
1061
1062 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1063
1064 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1065 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1066 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1067 __raw_readl(S5P_EPLL_CON1), pll_4600);
1068
1069 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1072
1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops;
1074 clk_fout_mpll.rate = mpll;
1075 clk_fout_epll.rate = epll;
1076 clk_fout_vpll.rate = vpll;
1077
1078 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1079 apll, mpll, epll, vpll);
1080
1081 armclk = clk_get_rate(&clk_armclk.clk);
1082 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1083
1084 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1085 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1088
1089 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1091 armclk, sclk_dmc, aclk_200,
1092 aclk_100, aclk_160, aclk_133);
1093
1094 clk_f.rate = armclk;
1095 clk_h.rate = sclk_dmc;
1096 clk_p.rate = aclk_100;
1097
1098 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1099 s3c_set_clksrc(&clksrcs[ptr], true);
1100}
1101
1102static struct clk *clks[] __initdata = {
1103 /* Nothing here yet */
1104};
1105
1106void __init s5pv310_register_clocks(void)
1107{
1108 int ptr;
1109
1110 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1111
1112 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1113 s3c_register_clksrc(sysclks[ptr], 1);
1114
1115 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1116 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1117
1118 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1119 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1120
1121 s3c_pwmclk_init();
1122}
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
deleted file mode 100644
index 0db0fb65bd70..000000000000
--- a/arch/arm/mach-s5pv310/cpu.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/cpu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
19
20#include <plat/cpu.h>
21#include <plat/clock.h>
22#include <plat/s5pv310.h>
23#include <plat/sdhci.h>
24
25#include <mach/regs-irq.h>
26
27extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
28 unsigned int irq_start);
29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
30
31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = {
33 {
34 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
41 .length = SZ_128K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU),
46 .length = SZ_64K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
55 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
56 .length = SZ_8K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)S5P_VA_L2CC,
60 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (unsigned long)S5P_VA_GPIO1,
65 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (unsigned long)S5P_VA_GPIO2,
70 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = (unsigned long)S5P_VA_GPIO3,
75 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
76 .length = SZ_256,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 }, {
84 .virtual = (unsigned long)S3C_VA_UART,
85 .pfn = __phys_to_pfn(S3C_PA_UART),
86 .length = SZ_512K,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = (unsigned long)S5P_VA_SROMC,
90 .pfn = __phys_to_pfn(S5PV310_PA_SROMC),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 },
94};
95
96static void s5pv310_idle(void)
97{
98 if (!need_resched())
99 cpu_do_idle();
100
101 local_irq_enable();
102}
103
104/* s5pv310_map_io
105 *
106 * register the standard cpu IO areas
107*/
108void __init s5pv310_map_io(void)
109{
110 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
111
112 /* initialize device information early */
113 s5pv310_default_sdhci0();
114 s5pv310_default_sdhci1();
115 s5pv310_default_sdhci2();
116 s5pv310_default_sdhci3();
117}
118
119void __init s5pv310_init_clocks(int xtal)
120{
121 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
122
123 s3c24xx_register_baseclocks(xtal);
124 s5p_register_clocks(xtal);
125 s5pv310_register_clocks();
126 s5pv310_setup_clocks();
127}
128
129void __init s5pv310_init_irq(void)
130{
131 int irq;
132
133 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
134
135 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
136
137 /*
138 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
139 * connected to the interrupt combiner. These irqs
140 * should be initialized to support cascade interrupt.
141 */
142 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
143 continue;
144
145 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
146 COMBINER_IRQ(irq, 0));
147 combiner_cascade_irq(irq, IRQ_SPI(irq));
148 }
149
150 /* The parameters of s5p_init_irq() are for VIC init.
151 * Theses parameters should be NULL and 0 because S5PV310
152 * uses GIC instead of VIC.
153 */
154 s5p_init_irq(NULL, 0);
155}
156
157struct sysdev_class s5pv310_sysclass = {
158 .name = "s5pv310-core",
159};
160
161static struct sys_device s5pv310_sysdev = {
162 .cls = &s5pv310_sysclass,
163};
164
165static int __init s5pv310_core_init(void)
166{
167 return sysdev_class_register(&s5pv310_sysclass);
168}
169
170core_initcall(s5pv310_core_init);
171
172#ifdef CONFIG_CACHE_L2X0
173static int __init s5pv310_l2x0_cache_init(void)
174{
175 /* TAG, Data Latency Control: 2cycle */
176 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
177 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
178
179 /* L2X0 Prefetch Control */
180 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
181
182 /* L2X0 Power Control */
183 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
184 S5P_VA_L2CC + L2X0_POWER_CTRL);
185
186 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
187
188 return 0;
189}
190
191early_initcall(s5pv310_l2x0_cache_init);
192#endif
193
194int __init s5pv310_init(void)
195{
196 printk(KERN_INFO "S5PV310: Initializing architecture\n");
197
198 /* set idle function */
199 pm_idle = s5pv310_idle;
200
201 return sysdev_register(&s5pv310_sysdev);
202}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c
deleted file mode 100644
index b04cbc731128..000000000000
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ /dev/null
@@ -1,580 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator;
36static struct regulator *int_regulator;
37#endif
38
39static struct cpufreq_freqs freqs;
40static unsigned int memtype;
41
42enum s5pv310_memory_type {
43 DDR2 = 4,
44 LPDDR2,
45 DDR3,
46};
47
48enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50};
51
52static struct cpufreq_frequency_table s5pv310_freq_table[] = {
53 {L0, 1000*1000},
54 {L1, 800*1000},
55 {L2, 400*1000},
56 {L3, 100*1000},
57 {0, CPUFREQ_TABLE_END},
58};
59
60static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
61 /*
62 * Clock divider value for following
63 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
64 * DIVATB, DIVPCLK_DBG, DIVAPLL }
65 */
66
67 /* ARM L0: 1000MHz */
68 { 0, 3, 7, 3, 3, 0, 1 },
69
70 /* ARM L1: 800MHz */
71 { 0, 3, 7, 3, 3, 0, 1 },
72
73 /* ARM L2: 400MHz */
74 { 0, 1, 3, 1, 3, 0, 1 },
75
76 /* ARM L3: 100MHz */
77 { 0, 0, 1, 0, 3, 1, 1 },
78};
79
80static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
81 /*
82 * Clock divider value for following
83 * { DIVCOPY, DIVHPM }
84 */
85
86 /* ARM L0: 1000MHz */
87 { 3, 0 },
88
89 /* ARM L1: 800MHz */
90 { 3, 0 },
91
92 /* ARM L2: 400MHz */
93 { 3, 0 },
94
95 /* ARM L3: 100MHz */
96 { 3, 0 },
97};
98
99static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
100 /*
101 * Clock divider value for following
102 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
103 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
104 */
105
106 /* DMC L0: 400MHz */
107 { 3, 1, 1, 1, 1, 1, 3, 1 },
108
109 /* DMC L1: 400MHz */
110 { 3, 1, 1, 1, 1, 1, 3, 1 },
111
112 /* DMC L2: 266.7MHz */
113 { 7, 1, 1, 2, 1, 1, 3, 1 },
114
115 /* DMC L3: 200MHz */
116 { 7, 1, 1, 3, 1, 1, 3, 1 },
117};
118
119static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
120 /*
121 * Clock divider value for following
122 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
123 */
124
125 /* ACLK200 L0: 200MHz */
126 { 3, 7, 4, 5, 1 },
127
128 /* ACLK200 L1: 200MHz */
129 { 3, 7, 4, 5, 1 },
130
131 /* ACLK200 L2: 160MHz */
132 { 4, 7, 5, 7, 1 },
133
134 /* ACLK200 L3: 133.3MHz */
135 { 5, 7, 7, 7, 1 },
136};
137
138static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
139 /*
140 * Clock divider value for following
141 * { DIVGDL/R, DIVGPL/R }
142 */
143
144 /* ACLK_GDL/R L0: 200MHz */
145 { 3, 1 },
146
147 /* ACLK_GDL/R L1: 200MHz */
148 { 3, 1 },
149
150 /* ACLK_GDL/R L2: 160MHz */
151 { 4, 1 },
152
153 /* ACLK_GDL/R L3: 133.3MHz */
154 { 5, 1 },
155};
156
157struct cpufreq_voltage_table {
158 unsigned int index; /* any */
159 unsigned int arm_volt; /* uV */
160 unsigned int int_volt;
161};
162
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
164 {
165 .index = L0,
166 .arm_volt = 1200000,
167 .int_volt = 1100000,
168 }, {
169 .index = L1,
170 .arm_volt = 1100000,
171 .int_volt = 1100000,
172 }, {
173 .index = L2,
174 .arm_volt = 1000000,
175 .int_volt = 1000000,
176 }, {
177 .index = L3,
178 .arm_volt = 900000,
179 .int_volt = 1000000,
180 },
181};
182
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1),
186
187 /* APLL FOUT L1: 800MHz */
188 ((200 << 16) | (6 << 8) | 1),
189
190 /* APLL FOUT L2 : 400MHz */
191 ((200 << 16) | (6 << 8) | 2),
192
193 /* APLL FOUT L3: 100MHz */
194 ((200 << 16) | (6 << 8) | 4),
195};
196
197int s5pv310_verify_speed(struct cpufreq_policy *policy)
198{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
200}
201
202unsigned int s5pv310_getspeed(unsigned int cpu)
203{
204 return clk_get_rate(cpu_clk) / 1000;
205}
206
207void s5pv310_set_clkdiv(unsigned int div_index)
208{
209 unsigned int tmp;
210
211 /* Change Divider - CPU0 */
212
213 tmp = __raw_readl(S5P_CLKDIV_CPU);
214
215 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
216 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
217 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
218 S5P_CLKDIV_CPU0_APLL_MASK);
219
220 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
221 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
222 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
223 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
224 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
225 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
226 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
227
228 __raw_writel(tmp, S5P_CLKDIV_CPU);
229
230 do {
231 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
232 } while (tmp & 0x1111111);
233
234 /* Change Divider - CPU1 */
235
236 tmp = __raw_readl(S5P_CLKDIV_CPU1);
237
238 tmp &= ~((0x7 << 4) | 0x7);
239
240 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
241 (clkdiv_cpu1[div_index][1] << 0));
242
243 __raw_writel(tmp, S5P_CLKDIV_CPU1);
244
245 do {
246 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
247 } while (tmp & 0x11);
248
249 /* Change Divider - DMC0 */
250
251 tmp = __raw_readl(S5P_CLKDIV_DMC0);
252
253 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
254 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
255 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
256 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
257
258 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
259 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
260 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
261 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
262 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
263 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
264 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
265 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
266
267 __raw_writel(tmp, S5P_CLKDIV_DMC0);
268
269 do {
270 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
271 } while (tmp & 0x11111111);
272
273 /* Change Divider - TOP */
274
275 tmp = __raw_readl(S5P_CLKDIV_TOP);
276
277 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
278 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
279 S5P_CLKDIV_TOP_ONENAND_MASK);
280
281 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
282 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
283 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
284 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
285 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
286
287 __raw_writel(tmp, S5P_CLKDIV_TOP);
288
289 do {
290 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
291 } while (tmp & 0x11111);
292
293 /* Change Divider - LEFTBUS */
294
295 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
296
297 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
298
299 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
300 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
301
302 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
303
304 do {
305 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
306 } while (tmp & 0x11);
307
308 /* Change Divider - RIGHTBUS */
309
310 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
311
312 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
313
314 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
315 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
316
317 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
318
319 do {
320 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
321 } while (tmp & 0x11);
322}
323
324static void s5pv310_set_apll(unsigned int index)
325{
326 unsigned int tmp;
327
328 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
329 clk_set_parent(moutcore, mout_mpll);
330
331 do {
332 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
333 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
334 tmp &= 0x7;
335 } while (tmp != 0x2);
336
337 /* 2. Set APLL Lock time */
338 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
339
340 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0);
345
346 /* 4. wait_lock_time */
347 do {
348 tmp = __raw_readl(S5P_APLL_CON0);
349 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
350
351 /* 5. MUX_CORE_SEL = APLL */
352 clk_set_parent(moutcore, mout_apll);
353
354 do {
355 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
356 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358}
359
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
361{
362 unsigned int tmp;
363
364 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index);
369
370 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index);
372 } else {
373 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index);
375
376 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0);
381 }
382 }
383
384 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index);
389
390 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index);
392 } else {
393 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0);
398
399 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index);
401 }
402 }
403}
404
405static int s5pv310_target(struct cpufreq_policy *policy,
406 unsigned int target_freq,
407 unsigned int relation)
408{
409 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt;
411
412 freqs.old = s5pv310_getspeed(policy->cpu);
413
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
415 freqs.old, relation, &old_index))
416 return -EINVAL;
417
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
419 target_freq, relation, &index))
420 return -EINVAL;
421
422 freqs.new = s5pv310_freq_table[index].frequency;
423 freqs.cpu = policy->cpu;
424
425 if (freqs.new == freqs.old)
426 return 0;
427
428 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt;
431
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433
434 /* control regulator */
435 if (freqs.new > freqs.old) {
436 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 }
442
443 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index);
445
446 /* control regulator */
447 if (freqs.new < freqs.old) {
448 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 }
454
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
456
457 return 0;
458}
459
460#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg)
463{
464 return 0;
465}
466
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
468{
469 return 0;
470}
471#endif
472
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
476
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
478
479 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000;
481
482 /*
483 * S5PV310 multi-core processors has 2 cores
484 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus.
487 */
488 cpumask_setall(policy->cpus);
489
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
491}
492
493static struct cpufreq_driver s5pv310_driver = {
494 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed,
496 .target = s5pv310_target,
497 .get = s5pv310_getspeed,
498 .init = s5pv310_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq",
500#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume,
503#endif
504};
505
506static int __init s5pv310_cpufreq_init(void)
507{
508 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk))
510 return PTR_ERR(cpu_clk);
511
512 moutcore = clk_get(NULL, "moutcore");
513 if (IS_ERR(moutcore))
514 goto out;
515
516 mout_mpll = clk_get(NULL, "mout_mpll");
517 if (IS_ERR(mout_mpll))
518 goto out;
519
520 mout_apll = clk_get(NULL, "mout_apll");
521 if (IS_ERR(mout_apll))
522 goto out;
523
524#ifdef CONFIG_REGULATOR
525 arm_regulator = regulator_get(NULL, "vdd_arm");
526 if (IS_ERR(arm_regulator)) {
527 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
528 goto out;
529 }
530
531 int_regulator = regulator_get(NULL, "vdd_int");
532 if (IS_ERR(int_regulator)) {
533 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
534 goto out;
535 }
536#endif
537
538 /*
539 * Check DRAM type.
540 * Because DVFS level is different according to DRAM type.
541 */
542 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
543 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
544 memtype &= S5P_DMC0_MEMTYPE_MASK;
545
546 if ((memtype < DDR2) && (memtype > DDR3)) {
547 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
548 goto out;
549 } else {
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 }
552
553 return cpufreq_register_driver(&s5pv310_driver);
554
555out:
556 if (!IS_ERR(cpu_clk))
557 clk_put(cpu_clk);
558
559 if (!IS_ERR(moutcore))
560 clk_put(moutcore);
561
562 if (!IS_ERR(mout_mpll))
563 clk_put(mout_mpll);
564
565 if (!IS_ERR(mout_apll))
566 clk_put(mout_apll);
567
568#ifdef CONFIG_REGULATOR
569 if (!IS_ERR(arm_regulator))
570 regulator_put(arm_regulator);
571
572 if (!IS_ERR(int_regulator))
573 regulator_put(int_regulator);
574#endif
575
576 printk(KERN_ERR "%s: failed initialization\n", __func__);
577
578 return -EINVAL;
579}
580late_initcall(s5pv310_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-s5pv310/dev-audio.c
deleted file mode 100644
index a1964242f0fa..000000000000
--- a/arch/arm/mach-s5pv310/dev-audio.c
+++ /dev/null
@@ -1,364 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static const char *rclksrc[] = {
23 [0] = "busclk",
24 [1] = "i2sclk",
25};
26
27static int s5pv310_cfg_i2s(struct platform_device *pdev)
28{
29 /* configure GPIO for i2s port */
30 switch (pdev->id) {
31 case 0:
32 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
33 break;
34 case 1:
35 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
36 break;
37 case 2:
38 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
39 break;
40 default:
41 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
42 return -EINVAL;
43 }
44
45 return 0;
46}
47
48static struct s3c_audio_pdata i2sv5_pdata = {
49 .cfg_gpio = s5pv310_cfg_i2s,
50 .type = {
51 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
53 | QUIRK_NEED_RSTCLR,
54 .src_clk = rclksrc,
55 },
56 },
57};
58
59static struct resource s5pv310_i2s0_resource[] = {
60 [0] = {
61 .start = S5PV310_PA_I2S0,
62 .end = S5PV310_PA_I2S0 + 0x100 - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .start = DMACH_I2S0_TX,
67 .end = DMACH_I2S0_TX,
68 .flags = IORESOURCE_DMA,
69 },
70 [2] = {
71 .start = DMACH_I2S0_RX,
72 .end = DMACH_I2S0_RX,
73 .flags = IORESOURCE_DMA,
74 },
75 [3] = {
76 .start = DMACH_I2S0S_TX,
77 .end = DMACH_I2S0S_TX,
78 .flags = IORESOURCE_DMA,
79 },
80};
81
82struct platform_device s5pv310_device_i2s0 = {
83 .name = "samsung-i2s",
84 .id = 0,
85 .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
86 .resource = s5pv310_i2s0_resource,
87 .dev = {
88 .platform_data = &i2sv5_pdata,
89 },
90};
91
92static const char *rclksrc_v3[] = {
93 [0] = "sclk_i2s",
94 [1] = "no_such_clock",
95};
96
97static struct s3c_audio_pdata i2sv3_pdata = {
98 .cfg_gpio = s5pv310_cfg_i2s,
99 .type = {
100 .i2s = {
101 .quirks = QUIRK_NO_MUXPSR,
102 .src_clk = rclksrc_v3,
103 },
104 },
105};
106
107static struct resource s5pv310_i2s1_resource[] = {
108 [0] = {
109 .start = S5PV310_PA_I2S1,
110 .end = S5PV310_PA_I2S1 + 0x100 - 1,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = DMACH_I2S1_TX,
115 .end = DMACH_I2S1_TX,
116 .flags = IORESOURCE_DMA,
117 },
118 [2] = {
119 .start = DMACH_I2S1_RX,
120 .end = DMACH_I2S1_RX,
121 .flags = IORESOURCE_DMA,
122 },
123};
124
125struct platform_device s5pv310_device_i2s1 = {
126 .name = "samsung-i2s",
127 .id = 1,
128 .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
129 .resource = s5pv310_i2s1_resource,
130 .dev = {
131 .platform_data = &i2sv3_pdata,
132 },
133};
134
135static struct resource s5pv310_i2s2_resource[] = {
136 [0] = {
137 .start = S5PV310_PA_I2S2,
138 .end = S5PV310_PA_I2S2 + 0x100 - 1,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = DMACH_I2S2_TX,
143 .end = DMACH_I2S2_TX,
144 .flags = IORESOURCE_DMA,
145 },
146 [2] = {
147 .start = DMACH_I2S2_RX,
148 .end = DMACH_I2S2_RX,
149 .flags = IORESOURCE_DMA,
150 },
151};
152
153struct platform_device s5pv310_device_i2s2 = {
154 .name = "samsung-i2s",
155 .id = 2,
156 .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
157 .resource = s5pv310_i2s2_resource,
158 .dev = {
159 .platform_data = &i2sv3_pdata,
160 },
161};
162
163/* PCM Controller platform_devices */
164
165static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
166{
167 switch (pdev->id) {
168 case 0:
169 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
170 break;
171 case 1:
172 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
173 break;
174 case 2:
175 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
176 break;
177 default:
178 printk(KERN_DEBUG "Invalid PCM Controller number!");
179 return -EINVAL;
180 }
181
182 return 0;
183}
184
185static struct s3c_audio_pdata s3c_pcm_pdata = {
186 .cfg_gpio = s5pv310_pcm_cfg_gpio,
187};
188
189static struct resource s5pv310_pcm0_resource[] = {
190 [0] = {
191 .start = S5PV310_PA_PCM0,
192 .end = S5PV310_PA_PCM0 + 0x100 - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 .start = DMACH_PCM0_TX,
197 .end = DMACH_PCM0_TX,
198 .flags = IORESOURCE_DMA,
199 },
200 [2] = {
201 .start = DMACH_PCM0_RX,
202 .end = DMACH_PCM0_RX,
203 .flags = IORESOURCE_DMA,
204 },
205};
206
207struct platform_device s5pv310_device_pcm0 = {
208 .name = "samsung-pcm",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
211 .resource = s5pv310_pcm0_resource,
212 .dev = {
213 .platform_data = &s3c_pcm_pdata,
214 },
215};
216
217static struct resource s5pv310_pcm1_resource[] = {
218 [0] = {
219 .start = S5PV310_PA_PCM1,
220 .end = S5PV310_PA_PCM1 + 0x100 - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = DMACH_PCM1_TX,
225 .end = DMACH_PCM1_TX,
226 .flags = IORESOURCE_DMA,
227 },
228 [2] = {
229 .start = DMACH_PCM1_RX,
230 .end = DMACH_PCM1_RX,
231 .flags = IORESOURCE_DMA,
232 },
233};
234
235struct platform_device s5pv310_device_pcm1 = {
236 .name = "samsung-pcm",
237 .id = 1,
238 .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
239 .resource = s5pv310_pcm1_resource,
240 .dev = {
241 .platform_data = &s3c_pcm_pdata,
242 },
243};
244
245static struct resource s5pv310_pcm2_resource[] = {
246 [0] = {
247 .start = S5PV310_PA_PCM2,
248 .end = S5PV310_PA_PCM2 + 0x100 - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 [1] = {
252 .start = DMACH_PCM2_TX,
253 .end = DMACH_PCM2_TX,
254 .flags = IORESOURCE_DMA,
255 },
256 [2] = {
257 .start = DMACH_PCM2_RX,
258 .end = DMACH_PCM2_RX,
259 .flags = IORESOURCE_DMA,
260 },
261};
262
263struct platform_device s5pv310_device_pcm2 = {
264 .name = "samsung-pcm",
265 .id = 2,
266 .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
267 .resource = s5pv310_pcm2_resource,
268 .dev = {
269 .platform_data = &s3c_pcm_pdata,
270 },
271};
272
273/* AC97 Controller platform devices */
274
275static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
276{
277 return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
278}
279
280static struct resource s5pv310_ac97_resource[] = {
281 [0] = {
282 .start = S5PV310_PA_AC97,
283 .end = S5PV310_PA_AC97 + 0x100 - 1,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = DMACH_AC97_PCMOUT,
288 .end = DMACH_AC97_PCMOUT,
289 .flags = IORESOURCE_DMA,
290 },
291 [2] = {
292 .start = DMACH_AC97_PCMIN,
293 .end = DMACH_AC97_PCMIN,
294 .flags = IORESOURCE_DMA,
295 },
296 [3] = {
297 .start = DMACH_AC97_MICIN,
298 .end = DMACH_AC97_MICIN,
299 .flags = IORESOURCE_DMA,
300 },
301 [4] = {
302 .start = IRQ_AC97,
303 .end = IRQ_AC97,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308static struct s3c_audio_pdata s3c_ac97_pdata = {
309 .cfg_gpio = s5pv310_ac97_cfg_gpio,
310};
311
312static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
313
314struct platform_device s5pv310_device_ac97 = {
315 .name = "samsung-ac97",
316 .id = -1,
317 .num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
318 .resource = s5pv310_ac97_resource,
319 .dev = {
320 .platform_data = &s3c_ac97_pdata,
321 .dma_mask = &s5pv310_ac97_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 },
324};
325
326/* S/PDIF Controller platform_device */
327
328static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
329{
330 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
331
332 return 0;
333}
334
335static struct resource s5pv310_spdif_resource[] = {
336 [0] = {
337 .start = S5PV310_PA_SPDIF,
338 .end = S5PV310_PA_SPDIF + 0x100 - 1,
339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
342 .start = DMACH_SPDIF,
343 .end = DMACH_SPDIF,
344 .flags = IORESOURCE_DMA,
345 },
346};
347
348static struct s3c_audio_pdata samsung_spdif_pdata = {
349 .cfg_gpio = s5pv310_spdif_cfg_gpio,
350};
351
352static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
353
354struct platform_device s5pv310_device_spdif = {
355 .name = "samsung-spdif",
356 .id = -1,
357 .num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
358 .resource = s5pv310_spdif_resource,
359 .dev = {
360 .platform_data = &samsung_spdif_pdata,
361 .dma_mask = &s5pv310_spdif_dmamask,
362 .coherent_dma_mask = DMA_BIT_MASK(32),
363 },
364};
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c
deleted file mode 100644
index 58a50c2d0b67..000000000000
--- a/arch/arm/mach-s5pv310/dev-pd.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/dev-pd.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int s5pv310_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int s5pv310_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device s5pv310_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = s5pv310_pd_enable,
74 .disable = s5pv310_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = s5pv310_pd_enable,
84 .disable = s5pv310_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = s5pv310_pd_enable,
94 .disable = s5pv310_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = s5pv310_pd_enable,
104 .disable = s5pv310_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = s5pv310_pd_enable,
114 .disable = s5pv310_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = s5pv310_pd_enable,
124 .disable = s5pv310_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = s5pv310_pd_enable,
134 .disable = s5pv310_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-s5pv310/dev-sysmmu.c
deleted file mode 100644
index e1bb200ac0f0..000000000000
--- a/arch/arm/mach-s5pv310/dev-sysmmu.c
+++ /dev/null
@@ -1,187 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13
14#include <mach/map.h>
15#include <mach/irqs.h>
16
17static struct resource s5pv310_sysmmu_resource[] = {
18 [0] = {
19 .start = S5PV310_PA_SYSMMU_MDMA,
20 .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
21 .flags = IORESOURCE_MEM,
22 },
23 [1] = {
24 .start = IRQ_SYSMMU_MDMA0_0,
25 .end = IRQ_SYSMMU_MDMA0_0,
26 .flags = IORESOURCE_IRQ,
27 },
28 [2] = {
29 .start = S5PV310_PA_SYSMMU_SSS,
30 .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [3] = {
34 .start = IRQ_SYSMMU_SSS_0,
35 .end = IRQ_SYSMMU_SSS_0,
36 .flags = IORESOURCE_IRQ,
37 },
38 [4] = {
39 .start = S5PV310_PA_SYSMMU_FIMC0,
40 .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [5] = {
44 .start = IRQ_SYSMMU_FIMC0_0,
45 .end = IRQ_SYSMMU_FIMC0_0,
46 .flags = IORESOURCE_IRQ,
47 },
48 [6] = {
49 .start = S5PV310_PA_SYSMMU_FIMC1,
50 .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
51 .flags = IORESOURCE_MEM,
52 },
53 [7] = {
54 .start = IRQ_SYSMMU_FIMC1_0,
55 .end = IRQ_SYSMMU_FIMC1_0,
56 .flags = IORESOURCE_IRQ,
57 },
58 [8] = {
59 .start = S5PV310_PA_SYSMMU_FIMC2,
60 .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
61 .flags = IORESOURCE_MEM,
62 },
63 [9] = {
64 .start = IRQ_SYSMMU_FIMC2_0,
65 .end = IRQ_SYSMMU_FIMC2_0,
66 .flags = IORESOURCE_IRQ,
67 },
68 [10] = {
69 .start = S5PV310_PA_SYSMMU_FIMC3,
70 .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
71 .flags = IORESOURCE_MEM,
72 },
73 [11] = {
74 .start = IRQ_SYSMMU_FIMC3_0,
75 .end = IRQ_SYSMMU_FIMC3_0,
76 .flags = IORESOURCE_IRQ,
77 },
78 [12] = {
79 .start = S5PV310_PA_SYSMMU_JPEG,
80 .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
81 .flags = IORESOURCE_MEM,
82 },
83 [13] = {
84 .start = IRQ_SYSMMU_JPEG_0,
85 .end = IRQ_SYSMMU_JPEG_0,
86 .flags = IORESOURCE_IRQ,
87 },
88 [14] = {
89 .start = S5PV310_PA_SYSMMU_FIMD0,
90 .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [15] = {
94 .start = IRQ_SYSMMU_LCD0_M0_0,
95 .end = IRQ_SYSMMU_LCD0_M0_0,
96 .flags = IORESOURCE_IRQ,
97 },
98 [16] = {
99 .start = S5PV310_PA_SYSMMU_FIMD1,
100 .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [17] = {
104 .start = IRQ_SYSMMU_LCD1_M1_0,
105 .end = IRQ_SYSMMU_LCD1_M1_0,
106 .flags = IORESOURCE_IRQ,
107 },
108 [18] = {
109 .start = S5PV310_PA_SYSMMU_PCIe,
110 .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
111 .flags = IORESOURCE_MEM,
112 },
113 [19] = {
114 .start = IRQ_SYSMMU_PCIE_0,
115 .end = IRQ_SYSMMU_PCIE_0,
116 .flags = IORESOURCE_IRQ,
117 },
118 [20] = {
119 .start = S5PV310_PA_SYSMMU_G2D,
120 .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
121 .flags = IORESOURCE_MEM,
122 },
123 [21] = {
124 .start = IRQ_SYSMMU_2D_0,
125 .end = IRQ_SYSMMU_2D_0,
126 .flags = IORESOURCE_IRQ,
127 },
128 [22] = {
129 .start = S5PV310_PA_SYSMMU_ROTATOR,
130 .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 [23] = {
134 .start = IRQ_SYSMMU_ROTATOR_0,
135 .end = IRQ_SYSMMU_ROTATOR_0,
136 .flags = IORESOURCE_IRQ,
137 },
138 [24] = {
139 .start = S5PV310_PA_SYSMMU_MDMA2,
140 .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
141 .flags = IORESOURCE_MEM,
142 },
143 [25] = {
144 .start = IRQ_SYSMMU_MDMA1_0,
145 .end = IRQ_SYSMMU_MDMA1_0,
146 .flags = IORESOURCE_IRQ,
147 },
148 [26] = {
149 .start = S5PV310_PA_SYSMMU_TV,
150 .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 [27] = {
154 .start = IRQ_SYSMMU_TV_M0_0,
155 .end = IRQ_SYSMMU_TV_M0_0,
156 .flags = IORESOURCE_IRQ,
157 },
158 [28] = {
159 .start = S5PV310_PA_SYSMMU_MFC_L,
160 .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 [29] = {
164 .start = IRQ_SYSMMU_MFC_M0_0,
165 .end = IRQ_SYSMMU_MFC_M0_0,
166 .flags = IORESOURCE_IRQ,
167 },
168 [30] = {
169 .start = S5PV310_PA_SYSMMU_MFC_R,
170 .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 [31] = {
174 .start = IRQ_SYSMMU_MFC_M1_0,
175 .end = IRQ_SYSMMU_MFC_M1_0,
176 .flags = IORESOURCE_IRQ,
177 },
178};
179
180struct platform_device s5pv310_device_sysmmu = {
181 .name = "s5p-sysmmu",
182 .id = 32,
183 .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource),
184 .resource = s5pv310_sysmmu_resource,
185};
186
187EXPORT_SYMBOL(s5pv310_device_sysmmu);
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-s5pv310/dma.c
deleted file mode 100644
index 20066c7c9e56..000000000000
--- a/arch/arm/mach-s5pv310/dma.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5pv310_pdma0_resource[] = {
34 [0] = {
35 .start = S5PV310_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_PDMA0,
41 .end = IRQ_PDMA0,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
47 .peri = {
48 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX,
50 [2] = DMACH_PCM2_RX,
51 [3] = DMACH_PCM2_TX,
52 [4] = DMACH_MSM_REQ0,
53 [5] = DMACH_MSM_REQ2,
54 [6] = DMACH_SPI0_RX,
55 [7] = DMACH_SPI0_TX,
56 [8] = DMACH_SPI2_RX,
57 [9] = DMACH_SPI2_TX,
58 [10] = DMACH_I2S0S_TX,
59 [11] = DMACH_I2S0_RX,
60 [12] = DMACH_I2S0_TX,
61 [13] = DMACH_I2S2_RX,
62 [14] = DMACH_I2S2_TX,
63 [15] = DMACH_UART0_RX,
64 [16] = DMACH_UART0_TX,
65 [17] = DMACH_UART2_RX,
66 [18] = DMACH_UART2_TX,
67 [19] = DMACH_UART4_RX,
68 [20] = DMACH_UART4_TX,
69 [21] = DMACH_SLIMBUS0_RX,
70 [22] = DMACH_SLIMBUS0_TX,
71 [23] = DMACH_SLIMBUS2_RX,
72 [24] = DMACH_SLIMBUS2_TX,
73 [25] = DMACH_SLIMBUS4_RX,
74 [26] = DMACH_SLIMBUS4_TX,
75 [27] = DMACH_AC97_MICIN,
76 [28] = DMACH_AC97_PCMIN,
77 [29] = DMACH_AC97_PCMOUT,
78 [30] = DMACH_MAX,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5pv310_device_pdma0 = {
84 .name = "s3c-pl330",
85 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
87 .resource = s5pv310_pdma0_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata,
92 },
93};
94
95static struct resource s5pv310_pdma1_resource[] = {
96 [0] = {
97 .start = S5PV310_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
102 .start = IRQ_PDMA1,
103 .end = IRQ_PDMA1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
109 .peri = {
110 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX,
112 [2] = DMACH_PCM1_RX,
113 [3] = DMACH_PCM1_TX,
114 [4] = DMACH_MSM_REQ1,
115 [5] = DMACH_MSM_REQ3,
116 [6] = DMACH_SPI1_RX,
117 [7] = DMACH_SPI1_TX,
118 [8] = DMACH_I2S0S_TX,
119 [9] = DMACH_I2S0_RX,
120 [10] = DMACH_I2S0_TX,
121 [11] = DMACH_I2S1_RX,
122 [12] = DMACH_I2S1_TX,
123 [13] = DMACH_UART0_RX,
124 [14] = DMACH_UART0_TX,
125 [15] = DMACH_UART1_RX,
126 [16] = DMACH_UART1_TX,
127 [17] = DMACH_UART3_RX,
128 [18] = DMACH_UART3_TX,
129 [19] = DMACH_SLIMBUS1_RX,
130 [20] = DMACH_SLIMBUS1_TX,
131 [21] = DMACH_SLIMBUS3_RX,
132 [22] = DMACH_SLIMBUS3_TX,
133 [23] = DMACH_SLIMBUS5_RX,
134 [24] = DMACH_SLIMBUS5_TX,
135 [25] = DMACH_SLIMBUS0AUX_RX,
136 [26] = DMACH_SLIMBUS0AUX_TX,
137 [27] = DMACH_SPDIF,
138 [28] = DMACH_MAX,
139 [29] = DMACH_MAX,
140 [30] = DMACH_MAX,
141 [31] = DMACH_MAX,
142 },
143};
144
145static struct platform_device s5pv310_device_pdma1 = {
146 .name = "s3c-pl330",
147 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
149 .resource = s5pv310_pdma1_resource,
150 .dev = {
151 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata,
154 },
155};
156
157static struct platform_device *s5pv310_dmacs[] __initdata = {
158 &s5pv310_device_pdma0,
159 &s5pv310_device_pdma1,
160};
161
162static int __init s5pv310_dma_init(void)
163{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
165
166 return 0;
167}
168arch_initcall(s5pv310_dma_init);
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
deleted file mode 100644
index 55217b8923ec..000000000000
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ /dev/null
@@ -1,304 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = S5PV310_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = S5PV310_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = S5PV310_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = S5PV310_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = S5PV310_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = S5PV310_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = S5PV310_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = S5PV310_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = S5PV310_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = S5PV310_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = S5PV310_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = S5PV310_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = S5PV310_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = S5PV310_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = S5PV310_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = S5PV310_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = S5PV310_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = S5PV310_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = S5PV310_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV310_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV310_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV310_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV310_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = S5PV310_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = S5PV310_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .base = (S5P_VA_GPIO2 + 0xC00),
203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0),
205 .chip = {
206 .base = S5PV310_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR,
208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq,
210 },
211 }, {
212 .base = (S5P_VA_GPIO2 + 0xC20),
213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8),
215 .chip = {
216 .base = S5PV310_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR,
218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq,
220 },
221 }, {
222 .base = (S5P_VA_GPIO2 + 0xC40),
223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16),
225 .chip = {
226 .base = S5PV310_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR,
228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq,
230 },
231 }, {
232 .base = (S5P_VA_GPIO2 + 0xC60),
233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24),
235 .chip = {
236 .base = S5PV310_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR,
238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq,
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
245 {
246 .chip = {
247 .base = S5PV310_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR,
249 .label = "GPZ",
250 },
251 },
252};
253
254static __init int s5pv310_gpiolib_init(void)
255{
256 struct s3c_gpio_chip *chip;
257 int i;
258 int nr_chips;
259
260 /* GPIO part 1 */
261
262 chip = s5pv310_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
264
265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL)
267 chip->config = &gpio_cfg;
268 if (chip->base == NULL)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 }
271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
273
274 /* GPIO part 2 */
275
276 chip = s5pv310_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
278
279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL)
281 chip->config = &gpio_cfg;
282 if (chip->base == NULL)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 }
285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
287
288 /* GPIO part 3 */
289
290 chip = s5pv310_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
292
293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL)
295 chip->config = &gpio_cfg;
296 if (chip->base == NULL)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 }
299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
301
302 return 0;
303}
304core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-s5pv310/headsmp.S
deleted file mode 100644
index 164b7b045713..000000000000
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/headsmp.S
3 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 *
6 * Copyright (c) 2003 ARM Limited
7 * All Rights Reserved
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15
16 __INIT
17
18/*
19 * s5pv310 specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise.
22 */
23ENTRY(s5pv310_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15
26 adr r4, 1f
27 ldmia r4, {r5, r6}
28 sub r4, r4, r5
29 add r6, r6, r4
30pen: ldr r7, [r6]
31 cmp r7, r0
32 bne pen
33
34 /*
35 * we've been released from the holding pen: secondary_stack
36 * should now contain the SVC stack for this core
37 */
38 b secondary_startup
39
401: .long .
41 .long pen_release
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c
deleted file mode 100644
index c24235c89eed..000000000000
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16
17#include <asm/cacheflush.h>
18
19extern volatile int pen_release;
20
21static inline void cpu_enter_lowpower(void)
22{
23 unsigned int v;
24
25 flush_cache_all();
26 asm volatile(
27 " mcr p15, 0, %1, c7, c5, 0\n"
28 " mcr p15, 0, %1, c7, c10, 4\n"
29 /*
30 * Turn off coherency
31 */
32 " mrc p15, 0, %0, c1, c0, 1\n"
33 " bic %0, %0, #0x20\n"
34 " mcr p15, 0, %0, c1, c0, 1\n"
35 " mrc p15, 0, %0, c1, c0, 0\n"
36 " bic %0, %0, %2\n"
37 " mcr p15, 0, %0, c1, c0, 0\n"
38 : "=&r" (v)
39 : "r" (0), "Ir" (CR_C)
40 : "cc");
41}
42
43static inline void cpu_leave_lowpower(void)
44{
45 unsigned int v;
46
47 asm volatile(
48 "mrc p15, 0, %0, c1, c0, 0\n"
49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n"
53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v)
55 : "Ir" (CR_C)
56 : "cc");
57}
58
59static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
60{
61 /*
62 * there is no power-control hardware on this platform, so all
63 * we can do is put the core into WFI; this is safe as the calling
64 * code will have already disabled interrupts
65 */
66 for (;;) {
67 /*
68 * here's the WFI
69 */
70 asm(".word 0xe320f003\n"
71 :
72 :
73 : "memory", "cc");
74
75 if (pen_release == cpu) {
76 /*
77 * OK, proper wakeup, we're done
78 */
79 break;
80 }
81
82 /*
83 * Getting here, means that we have come out of WFI without
84 * having been woken up - this shouldn't happen
85 *
86 * Just note it happening - when we're woken, we can report
87 * its occurrence.
88 */
89 (*spurious)++;
90 }
91}
92
93int platform_cpu_kill(unsigned int cpu)
94{
95 return 1;
96}
97
98/*
99 * platform-specific code to shutdown a CPU
100 *
101 * Called with IRQs disabled
102 */
103void platform_cpu_die(unsigned int cpu)
104{
105 int spurious = 0;
106
107 /*
108 * we're ready for shutdown now, so do it
109 */
110 cpu_enter_lowpower();
111 platform_do_lowpower(cpu, &spurious);
112
113 /*
114 * bring this CPU back into the world of cache
115 * coherency, and then restore interrupts
116 */
117 cpu_leave_lowpower();
118
119 if (spurious)
120 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
121}
122
123int platform_cpu_disable(unsigned int cpu)
124{
125 /*
126 * we don't allow CPU 0 to be shutdown (it is still too special
127 * e.g. clock tick interrupts)
128 */
129 return cpu == 0 ? -EPERM : 0;
130}
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
deleted file mode 100644
index b0d920c474d3..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16
17 /* note, for the boot process to work we have to keep the UART
18 * virtual address aligned to an 1MiB boundary for the L1
19 * mapping the head code makes. We keep the UART virtual address
20 * aligned and add in the offset when we load the value here.
21 */
22
23 .macro addruart, rp, rv
24 ldreq \rp, = S3C_PA_UART
25 ldrne \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#define fifo_full fifo_full_s5pv210
33#define fifo_level fifo_level_s5pv210
34
35#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-s5pv310/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-s5pv310/include/mach/entry-macro.S
deleted file mode 100644
index e600e1d522df..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ /dev/null
@@ -1,84 +0,0 @@
1/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 *
5 * Low-level IRQ helper macros for S5PV310 platforms
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10*/
11
12#include <mach/hardware.h>
13#include <asm/hardware/gic.h>
14
15 .macro disable_fiq
16 .endm
17
18 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =gic_cpu_base_addr
20 ldr \base, [\base]
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 /*
27 * The interrupt numbering scheme is defined in the
28 * interrupt controller spec. To wit:
29 *
30 * Interrupts 0-15 are IPI
31 * 16-28 are reserved
32 * 29-31 are local. We allow 30 to be used for the watchdog.
33 * 32-1020 are global
34 * 1021-1022 are reserved
35 * 1023 is "spurious" (no interrupt)
36 *
37 * For now, we ignore all local interrupts so only return an interrupt if it's
38 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
39 *
40 * A simple read from the controller will tell us the number of the highest
41 * priority enabled interrupt. We then just need to check whether it is in the
42 * valid range for an IRQ (30-1020 inclusive).
43 */
44
45 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
46
47 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
48
49 ldr \tmp, =1021
50
51 bic \irqnr, \irqstat, #0x1c00
52
53 cmp \irqnr, #29
54 cmpcc \irqnr, \irqnr
55 cmpne \irqnr, \tmp
56 cmpcs \irqnr, \irqnr
57 addne \irqnr, \irqnr, #32
58
59 .endm
60
61 /* We assume that irqstat (the raw value of the IRQ acknowledge
62 * register) is preserved from the macro above.
63 * If there is an IPI, we immediately signal end of interrupt on the
64 * controller, since this requires the original irqstat value which
65 * we won't easily be able to recreate later.
66 */
67
68 .macro test_for_ipi, irqnr, irqstat, base, tmp
69 bic \irqnr, \irqstat, #0x1c00
70 cmp \irqnr, #16
71 strcc \irqstat, [\base, #GIC_CPU_EOI]
72 cmpcs \irqnr, \irqnr
73 .endm
74
75 /* As above, this assumes that irqstat and base are preserved.. */
76
77 .macro test_for_ltirq, irqnr, irqstat, base, tmp
78 bic \irqnr, \irqstat, #0x1c00
79 mov \tmp, #0
80 cmp \irqnr, #29
81 moveq \tmp, #1
82 streq \irqstat, [\base, #GIC_CPU_EOI]
83 cmp \tmp, #0
84 .endm
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define S5PV310_GPIO_A0_NR (8)
25#define S5PV310_GPIO_A1_NR (6)
26#define S5PV310_GPIO_B_NR (8)
27#define S5PV310_GPIO_C0_NR (5)
28#define S5PV310_GPIO_C1_NR (5)
29#define S5PV310_GPIO_D0_NR (4)
30#define S5PV310_GPIO_D1_NR (4)
31#define S5PV310_GPIO_E0_NR (5)
32#define S5PV310_GPIO_E1_NR (8)
33#define S5PV310_GPIO_E2_NR (6)
34#define S5PV310_GPIO_E3_NR (8)
35#define S5PV310_GPIO_E4_NR (8)
36#define S5PV310_GPIO_F0_NR (8)
37#define S5PV310_GPIO_F1_NR (8)
38#define S5PV310_GPIO_F2_NR (8)
39#define S5PV310_GPIO_F3_NR (6)
40#define S5PV310_GPIO_J0_NR (8)
41#define S5PV310_GPIO_J1_NR (5)
42#define S5PV310_GPIO_K0_NR (7)
43#define S5PV310_GPIO_K1_NR (7)
44#define S5PV310_GPIO_K2_NR (7)
45#define S5PV310_GPIO_K3_NR (7)
46#define S5PV310_GPIO_L0_NR (8)
47#define S5PV310_GPIO_L1_NR (3)
48#define S5PV310_GPIO_L2_NR (8)
49#define S5PV310_GPIO_X0_NR (8)
50#define S5PV310_GPIO_X1_NR (8)
51#define S5PV310_GPIO_X2_NR (8)
52#define S5PV310_GPIO_X3_NR (8)
53#define S5PV310_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define S5PV310_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 S5PV310_GPIO_A0_START = 0,
62 S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
63 S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
64 S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
65 S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
66 S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
67 S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
68 S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
69 S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
70 S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
71 S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
72 S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
73 S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
74 S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
75 S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
76 S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
77 S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
78 S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
79 S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
80 S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
81 S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
82 S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
83 S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
84 S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
85 S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
86 S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
87 S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
88 S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
89 S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
90 S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
91};
92
93/* S5PV310 GPIO number definitions */
94#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
95#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
96#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
97#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
98#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
99#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
100#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
101#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
102#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
103#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
104#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
105#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
106#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
107#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
108#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
109#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
110#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
111#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
112#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
113#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
114#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
115#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
116#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
117#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
118#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
119#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
120#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
121#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
122#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
123#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
124
125/* the end of the S5PV310 specific gpios */
126#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END S5PV310_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-s5pv310/include/mach/hardware.h
deleted file mode 100644
index 28ff9881f1a6..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-s5pv310/include/mach/io.h
deleted file mode 100644
index 8a7f9128391f..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/io.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 *
10 * Default IO routines for S5PV310
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17#ifndef __ASM_ARM_ARCH_IO_H
18#define __ASM_ARM_ARCH_IO_H __FILE__
19
20/* No current ISA/PCI bus support. */
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23
24#define IO_SPACE_LIMIT (0xFFFFFFFF)
25
26#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
deleted file mode 100644
index 536b0b59fc83..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* PPI: Private Peripheral Interrupt */
19
20#define IRQ_PPI(x) S5P_IRQ(x+16)
21
22#define IRQ_LOCALTIMER IRQ_PPI(13)
23
24/* SPI: Shared Peripheral Interrupt */
25
26#define IRQ_SPI(x) S5P_IRQ(x+32)
27
28#define IRQ_MCT1 IRQ_SPI(35)
29
30#define IRQ_EINT0 IRQ_SPI(40)
31#define IRQ_EINT1 IRQ_SPI(41)
32#define IRQ_EINT2 IRQ_SPI(42)
33#define IRQ_EINT3 IRQ_SPI(43)
34#define IRQ_USB_HSOTG IRQ_SPI(44)
35#define IRQ_USB_HOST IRQ_SPI(45)
36#define IRQ_MODEM_IF IRQ_SPI(46)
37#define IRQ_ROTATOR IRQ_SPI(47)
38#define IRQ_JPEG IRQ_SPI(48)
39#define IRQ_2D IRQ_SPI(49)
40#define IRQ_PCIE IRQ_SPI(50)
41#define IRQ_MCT0 IRQ_SPI(51)
42#define IRQ_MFC IRQ_SPI(52)
43#define IRQ_AUDIO_SS IRQ_SPI(54)
44#define IRQ_AC97 IRQ_SPI(55)
45#define IRQ_SPDIF IRQ_SPI(56)
46#define IRQ_KEYPAD IRQ_SPI(57)
47#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
48#define IRQ_SLIMBUS IRQ_SPI(59)
49#define IRQ_PMU IRQ_SPI(60)
50#define IRQ_TSI IRQ_SPI(61)
51#define IRQ_SATA IRQ_SPI(62)
52#define IRQ_GPS IRQ_SPI(63)
53
54#define MAX_IRQ_IN_COMBINER 8
55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
57
58#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
59#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
60#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
61#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
62#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
63#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
64#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
65#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
66
67#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
68#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
69#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
70#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
71#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
72#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
73#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
74#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
75
76#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
77#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
78
79#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
80#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
81#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
82#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
83#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
84
85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
87
88#define IRQ_UART0 COMBINER_IRQ(26, 0)
89#define IRQ_UART1 COMBINER_IRQ(26, 1)
90#define IRQ_UART2 COMBINER_IRQ(26, 2)
91#define IRQ_UART3 COMBINER_IRQ(26, 3)
92#define IRQ_UART4 COMBINER_IRQ(26, 4)
93
94#define IRQ_IIC COMBINER_IRQ(27, 0)
95#define IRQ_IIC1 COMBINER_IRQ(27, 1)
96#define IRQ_IIC2 COMBINER_IRQ(27, 2)
97#define IRQ_IIC3 COMBINER_IRQ(27, 3)
98#define IRQ_IIC4 COMBINER_IRQ(27, 4)
99#define IRQ_IIC5 COMBINER_IRQ(27, 5)
100#define IRQ_IIC6 COMBINER_IRQ(27, 6)
101#define IRQ_IIC7 COMBINER_IRQ(27, 7)
102
103#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
104#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
105#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
106#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
107
108#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
109#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
110
111#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
112
113#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
114
115#define IRQ_EINT4 COMBINER_IRQ(37, 0)
116#define IRQ_EINT5 COMBINER_IRQ(37, 1)
117#define IRQ_EINT6 COMBINER_IRQ(37, 2)
118#define IRQ_EINT7 COMBINER_IRQ(37, 3)
119#define IRQ_EINT8 COMBINER_IRQ(38, 0)
120
121#define IRQ_EINT9 COMBINER_IRQ(38, 1)
122#define IRQ_EINT10 COMBINER_IRQ(38, 2)
123#define IRQ_EINT11 COMBINER_IRQ(38, 3)
124#define IRQ_EINT12 COMBINER_IRQ(38, 4)
125#define IRQ_EINT13 COMBINER_IRQ(38, 5)
126#define IRQ_EINT14 COMBINER_IRQ(38, 6)
127#define IRQ_EINT15 COMBINER_IRQ(38, 7)
128
129#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
130
131#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
132
133#define IRQ_WDT COMBINER_IRQ(53, 0)
134
135#define MAX_COMBINER_NR 54
136
137#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
138
139#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
140#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
141
142/* Set the default NR_IRQS */
143
144#define NR_IRQS (S5P_IRQ_EINT_BASE + 32)
145
146#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define S5PV310_PA_SYSRAM 0x02025000
27
28#define S5PV310_PA_I2S0 0x03830000
29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PV310_PA_I2S2 0xE2A00000
31
32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
35
36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41#define S5PV310_PA_CHIPID 0x10000000
42
43#define S5PV310_PA_SYSCON 0x10010000
44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
46
47#define S5PV310_PA_WATCHDOG 0x10060000
48#define S5PV310_PA_RTC 0x10070000
49
50#define S5PV310_PA_DMC0 0x10400000
51
52#define S5PV310_PA_COMBINER 0x10448000
53
54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
59
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
66#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
67#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
68#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
69#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
70#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
71#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
72#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
73#define S5PV310_PA_SYSMMU_PCIe 0x12620000
74#define S5PV310_PA_SYSMMU_G2D 0x12A20000
75#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
76#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
77#define S5PV310_PA_SYSMMU_TV 0x12E20000
78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81#define S5PV310_PA_GPIO1 0x11400000
82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
110#define S3C_PA_IIC S5PV310_PA_IIC(0)
111#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
112#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
113#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
114#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
115#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
116#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118#define S3C_PA_RTC S5PV310_PA_RTC
119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h
deleted file mode 100644
index 1dffb4823245..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H __FILE__
15
16#define PHYS_OFFSET UL(0x40000000)
17
18/* Maximum of 256MiB in one bank */
19#define MAX_PHYSMEM_BITS 32
20#define SECTION_SIZE_BITS 28
21
22#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
deleted file mode 100644
index 7e6da2701088..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 *
13 * S5PV310 - pwm clock and timer support
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#ifndef __ASM_ARCH_PWMCLK_H
21#define __ASM_ARCH_PWMCLK_H __FILE__
22
23/**
24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
26 *
27 * Return true if the given configuration from TCFG1 is a TCLK instead
28 * any of the TDIV clocks.
29 */
30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
31{
32 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
33}
34
35/**
36 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
37 * @tcfg1: The tcfg1 setting, shifted down.
38 *
39 * Get the divisor value for the given tcfg1 setting. We assume the
40 * caller has already checked to see if this is not a TCLK source.
41 */
42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
43{
44 return 1 << tcfg1;
45}
46
47/**
48 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
49 *
50 * Return true if we have a /1 in the tdiv setting.
51 */
52static inline unsigned int pwm_tdiv_has_div1(void)
53{
54 return 1;
55}
56
57/**
58 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
59 * @div: The divisor to calculate the bit information for.
60 *
61 * Turn a divisor into the necessary bit field for TCFG1.
62 */
63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
64{
65 return ilog2(div);
66}
67
68#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
69
70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
deleted file mode 100644
index b5c4ada1cff5..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
19
20#define S5P_INFORM0 S5P_CLKREG(0x800)
21
22#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
27
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
31#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
32
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
36#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
37#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
38#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
39#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
40#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
41#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
42
43#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
44#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
45#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
46#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
47#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
48#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
49#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
50#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
51#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
52#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
53#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
54#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
55#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
56#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
57#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
58
59#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
60#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
61#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
62#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
63#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
64#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
65#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
66
67#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68
69#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
72#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
73#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
74#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
75#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
76
77#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
80
81#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
83#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
84#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
85#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
86#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
87
88#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
89#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
90
91#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
92#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
93#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
94#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
95
96#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
97
98/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
100
101/* APLL_CON0 */
102#define S5P_APLLCON0_ENABLE_SHIFT (31)
103#define S5P_APLLCON0_LOCKED_SHIFT (29)
104#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
105#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
106
107/* CLK_SRC_CPU */
108#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
109#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
110
111/* CLKDIV_CPU0 */
112#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
113#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
114#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
115#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
116#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
117#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
118#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
119#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
120#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
121#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
122#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
123#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
124#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
125#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
126
127/* CLKDIV_DMC0 */
128#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
129#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
130#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
131#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
132#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
133#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
134#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
135#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
136#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
137#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
138#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
139#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
140#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
141#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
142#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
143#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
144
145/* CLKDIV_TOP */
146#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
147#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
148#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
149#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
150#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
151#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
152#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
153#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
154#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
155#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
156
157/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
158#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
159#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162
163/* Compatibility defines */
164
165#define S5P_EPLL_CON S5P_EPLL_CON0
166
167#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-s5pv310/include/mach/regs-irq.h
deleted file mode 100644
index c6e09c7f9161..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/gic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
deleted file mode 100644
index 834227140eaa..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC and DMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MEM_H
14#define __ASM_ARCH_REGS_MEM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_DMC0_MEMCON_OFFSET 0x04
19
20#define S5P_DMC0_MEMTYPE_SHIFT 8
21#define S5P_DMC0_MEMTYPE_MASK 0xF
22
23#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
deleted file mode 100644
index fb333d0f6073..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
25#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
26#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
27
28#define S5P_INT_LOCAL_PWR_EN 0x7
29
30#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
deleted file mode 100644
index 0b28e81a16f7..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - System MMU register
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SYSMMU_H
14#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
15
16#define S5P_MMU_CTRL 0x000
17#define S5P_MMU_CFG 0x004
18#define S5P_MMU_STATUS 0x008
19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018
22#define S5P_PAGE_FAULT_ADDR 0x024
23
24#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
deleted file mode 100644
index 393ccbd52c4a..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/
5
6#ifndef ASM_ARCH_SMP_H
7#define ASM_ARCH_SMP_H __FILE__
8
9#include <asm/hardware/gic.h>
10
11/*
12 * We use IRQ1 as the IPI
13 */
14static inline void smp_cross_call(const struct cpumask *mask, int ipi)
15{
16 gic_raise_softirq(mask, ipi);
17}
18
19#endif
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
deleted file mode 100644
index 598fc5c9211b..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Samsung sysmmu driver for S5PV310
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
18
19enum s5pv310_sysmmu_ips {
20 SYSMMU_MDMA,
21 SYSMMU_SSS,
22 SYSMMU_FIMC0,
23 SYSMMU_FIMC1,
24 SYSMMU_FIMC2,
25 SYSMMU_FIMC3,
26 SYSMMU_JPEG,
27 SYSMMU_FIMD0,
28 SYSMMU_FIMD1,
29 SYSMMU_PCIe,
30 SYSMMU_G2D,
31 SYSMMU_ROTATOR,
32 SYSMMU_MDMA2,
33 SYSMMU_TV,
34 SYSMMU_MFC_L,
35 SYSMMU_MFC_R,
36};
37
38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
39 "SYSMMU_MDMA" ,
40 "SYSMMU_SSS" ,
41 "SYSMMU_FIMC0" ,
42 "SYSMMU_FIMC1" ,
43 "SYSMMU_FIMC2" ,
44 "SYSMMU_FIMC3" ,
45 "SYSMMU_JPEG" ,
46 "SYSMMU_FIMD0" ,
47 "SYSMMU_FIMD1" ,
48 "SYSMMU_PCIe" ,
49 "SYSMMU_G2D" ,
50 "SYSMMU_ROTATOR",
51 "SYSMMU_MDMA2" ,
52 "SYSMMU_TV" ,
53 "SYSMMU_MFC_L" ,
54 "SYSMMU_MFC_R" ,
55};
56
57typedef enum s5pv310_sysmmu_ips sysmmu_ips;
58
59struct sysmmu_tt_info {
60 unsigned long *pgd;
61 unsigned long pgd_paddr;
62 unsigned long *pte;
63};
64
65struct sysmmu_controller {
66 const char *name;
67
68 /* channels registers */
69 void __iomem *regs;
70
71 /* channel irq */
72 unsigned int irq;
73
74 sysmmu_ips ips;
75
76 /* Translation Table Info. */
77 struct sysmmu_tt_info *tt_info;
78
79 struct resource *mem;
80 struct device *dev;
81
82 /* SysMMU controller enable - true : enable */
83 bool enable;
84};
85
86/**
87 * s5p_sysmmu_enable() - enable system mmu of ip
88 * @ips: The ip connected system mmu.
89 *
90 * This function enable system mmu to transfer address
91 * from virtual address to physical address
92 */
93int s5p_sysmmu_enable(sysmmu_ips ips);
94
95/**
96 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
97 * @ips: The ip connected system mmu.
98 *
99 * This function disable system mmu to transfer address
100 * from virtual address to physical address
101 */
102int s5p_sysmmu_disable(sysmmu_ips ips);
103
104/**
105 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
106 * @ips: The ip connected system mmu.
107 * @pgd: The page table base address.
108 *
109 * This function set page table base address
110 * When system mmu transfer address from virtaul address to physical address,
111 * system mmu refer address information from page table
112 */
113int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
114
115/**
116 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
117 * @ips: The ip connected system mmu.
118 *
119 * This function flush all TLB entry in system mmu
120 */
121int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
122#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-s5pv310/include/mach/system.h
deleted file mode 100644
index d10c009cf0f1..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/system.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-s5pv310/include/mach/timex.h
deleted file mode 100644
index bd2359b952b4..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 *
11 * S5PV310 - time parameters
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_ARCH_TIMEX_H
19#define __ASM_ARCH_TIMEX_H __FILE__
20
21/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
22 * a variable is useless. It seems as long as we make our timers an
23 * exact multiple of HZ, any value that makes a 1->1 correspondence
24 * for the time conversion functions to/from jiffies is acceptable.
25*/
26
27#define CLOCK_TICK_RATE 12000000
28
29#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-s5pv310/include/mach/uncompress.h
deleted file mode 100644
index 59593c1e2416..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22
23 /*
24 * For preventing FIFO overrun or infinite loop of UART console,
25 * fifo_max should be the minimum fifo size of all of the UART channels
26 */
27 fifo_mask = S5PV210_UFSTAT_TXMASK;
28 fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
29}
30#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
deleted file mode 100644
index 65759fb97581..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 *
8 * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S5PV310 vmalloc definition
15*/
16
17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__
19
20#define VMALLOC_END 0xF6000000UL
21
22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-s5pv310/init.c
deleted file mode 100644
index 182dcf42cfb4..000000000000
--- a/arch/arm/mach-s5pv310/init.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12
13#include <plat/cpu.h>
14#include <plat/devs.h>
15#include <plat/regs-serial.h>
16
17static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
18 [0] = {
19 .name = "uclk1",
20 .divisor = 1,
21 .min_baud = 0,
22 .max_baud = 0,
23 },
24};
25
26/* uart registration process */
27void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{
29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt;
31
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1;
35 tcfg->clocks = s5pv310_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
37 }
38 }
39
40 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
41}
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
deleted file mode 100644
index 1ea4a9e83bbe..000000000000
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/irq-combiner.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/common/gic.c
7 *
8 * IRQ COMBINER support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/io.h>
16
17#include <asm/mach/irq.h>
18
19#define COMBINER_ENABLE_SET 0x0
20#define COMBINER_ENABLE_CLEAR 0x4
21#define COMBINER_INT_STATUS 0xC
22
23static DEFINE_SPINLOCK(irq_controller_lock);
24
25struct combiner_chip_data {
26 unsigned int irq_offset;
27 unsigned int irq_mask;
28 void __iomem *base;
29};
30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32
33static inline void __iomem *combiner_base(struct irq_data *data)
34{
35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
38 return combiner_data->base;
39}
40
41static void combiner_mask_irq(struct irq_data *data)
42{
43 u32 mask = 1 << (data->irq % 32);
44
45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
46}
47
48static void combiner_unmask_irq(struct irq_data *data)
49{
50 u32 mask = 1 << (data->irq % 32);
51
52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
53}
54
55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
56{
57 struct combiner_chip_data *chip_data = get_irq_data(irq);
58 struct irq_chip *chip = get_irq_chip(irq);
59 unsigned int cascade_irq, combiner_irq;
60 unsigned long status;
61
62 /* primary controller ack'ing */
63 chip->irq_ack(&desc->irq_data);
64
65 spin_lock(&irq_controller_lock);
66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
67 spin_unlock(&irq_controller_lock);
68 status &= chip_data->irq_mask;
69
70 if (status == 0)
71 goto out;
72
73 combiner_irq = __ffs(status);
74
75 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
76 if (unlikely(cascade_irq >= NR_IRQS))
77 do_bad_IRQ(cascade_irq, desc);
78 else
79 generic_handle_irq(cascade_irq);
80
81 out:
82 /* primary controller unmasking */
83 chip->irq_unmask(&desc->irq_data);
84}
85
86static struct irq_chip combiner_chip = {
87 .name = "COMBINER",
88 .irq_mask = combiner_mask_irq,
89 .irq_unmask = combiner_unmask_irq,
90};
91
92void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
93{
94 if (combiner_nr >= MAX_COMBINER_NR)
95 BUG();
96 if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
97 BUG();
98 set_irq_chained_handler(irq, combiner_handle_cascade_irq);
99}
100
101void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
102 unsigned int irq_start)
103{
104 unsigned int i;
105
106 if (combiner_nr >= MAX_COMBINER_NR)
107 BUG();
108
109 combiner_data[combiner_nr].base = base;
110 combiner_data[combiner_nr].irq_offset = irq_start;
111 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
112
113 /* Disable all interrupts */
114
115 __raw_writel(combiner_data[combiner_nr].irq_mask,
116 base + COMBINER_ENABLE_CLEAR);
117
118 /* Setup the Linux IRQ subsystem */
119
120 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
121 + MAX_IRQ_IN_COMBINER; i++) {
122 set_irq_chip(i, &combiner_chip);
123 set_irq_chip_data(i, &combiner_data[combiner_nr]);
124 set_irq_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 }
127}
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
deleted file mode 100644
index 477bd9e97f0f..000000000000
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ /dev/null
@@ -1,229 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/irq-eint.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26static DEFINE_SPINLOCK(eint_lock);
27
28static unsigned int eint0_15_data[16];
29
30static unsigned int s5pv310_get_irq_nr(unsigned int number)
31{
32 u32 ret = 0;
33
34 switch (number) {
35 case 0 ... 3:
36 ret = (number + IRQ_EINT0);
37 break;
38 case 4 ... 7:
39 ret = (number + (IRQ_EINT4 - 4));
40 break;
41 case 8 ... 15:
42 ret = (number + (IRQ_EINT8 - 8));
43 break;
44 default:
45 printk(KERN_ERR "number available : %d\n", number);
46 }
47
48 return ret;
49}
50
51static inline void s5pv310_irq_eint_mask(struct irq_data *data)
52{
53 u32 mask;
54
55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
57 mask |= eint_irq_to_bit(data->irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 spin_unlock(&eint_lock);
60}
61
62static void s5pv310_irq_eint_unmask(struct irq_data *data)
63{
64 u32 mask;
65
66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
68 mask &= ~(eint_irq_to_bit(data->irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 spin_unlock(&eint_lock);
71}
72
73static inline void s5pv310_irq_eint_ack(struct irq_data *data)
74{
75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
77}
78
79static void s5pv310_irq_eint_maskack(struct irq_data *data)
80{
81 s5pv310_irq_eint_mask(data);
82 s5pv310_irq_eint_ack(data);
83}
84
85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
86{
87 int offs = EINT_OFFSET(data->irq);
88 int shift;
89 u32 ctrl, mask;
90 u32 newvalue = 0;
91
92 switch (type) {
93 case IRQ_TYPE_EDGE_RISING:
94 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
95 break;
96
97 case IRQ_TYPE_EDGE_FALLING:
98 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
99 break;
100
101 case IRQ_TYPE_EDGE_BOTH:
102 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
103 break;
104
105 case IRQ_TYPE_LEVEL_LOW:
106 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
107 break;
108
109 case IRQ_TYPE_LEVEL_HIGH:
110 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
111 break;
112
113 default:
114 printk(KERN_ERR "No such irq type %d", type);
115 return -EINVAL;
116 }
117
118 shift = (offs & 0x7) * 4;
119 mask = 0x7 << shift;
120
121 spin_lock(&eint_lock);
122 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
123 ctrl &= ~mask;
124 ctrl |= newvalue << shift;
125 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
126 spin_unlock(&eint_lock);
127
128 switch (offs) {
129 case 0 ... 7:
130 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
131 break;
132 case 8 ... 15:
133 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
134 break;
135 case 16 ... 23:
136 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
137 break;
138 case 24 ... 31:
139 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
140 break;
141 default:
142 printk(KERN_ERR "No such irq number %d", offs);
143 }
144
145 return 0;
146}
147
148static struct irq_chip s5pv310_irq_eint = {
149 .name = "s5pv310-eint",
150 .irq_mask = s5pv310_irq_eint_mask,
151 .irq_unmask = s5pv310_irq_eint_unmask,
152 .irq_mask_ack = s5pv310_irq_eint_maskack,
153 .irq_ack = s5pv310_irq_eint_ack,
154 .irq_set_type = s5pv310_irq_eint_set_type,
155#ifdef CONFIG_PM
156 .irq_set_wake = s3c_irqext_wake,
157#endif
158};
159
160/* s5pv310_irq_demux_eint
161 *
162 * This function demuxes the IRQ from from EINTs 16 to 31.
163 * It is designed to be inlined into the specific handler
164 * s5p_irq_demux_eintX_Y.
165 *
166 * Each EINT pend/mask registers handle eight of them.
167 */
168static inline void s5pv310_irq_demux_eint(unsigned int start)
169{
170 unsigned int irq;
171
172 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
173 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
174
175 status &= ~mask;
176 status &= 0xff;
177
178 while (status) {
179 irq = fls(status) - 1;
180 generic_handle_irq(irq + start);
181 status &= ~(1 << irq);
182 }
183}
184
185static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
186{
187 s5pv310_irq_demux_eint(IRQ_EINT(16));
188 s5pv310_irq_demux_eint(IRQ_EINT(24));
189}
190
191static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192{
193 u32 *irq_data = get_irq_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq);
195
196 chip->irq_mask(&desc->irq_data);
197
198 if (chip->irq_ack)
199 chip->irq_ack(&desc->irq_data);
200
201 generic_handle_irq(*irq_data);
202
203 chip->irq_unmask(&desc->irq_data);
204}
205
206int __init s5pv310_init_irq_eint(void)
207{
208 int irq;
209
210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 }
215
216 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
217
218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq);
220
221 set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
222 set_irq_chained_handler(s5pv310_get_irq_nr(irq),
223 s5pv310_irq_eint0_15);
224 }
225
226 return 0;
227}
228
229arch_initcall(s5pv310_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-s5pv310/localtimer.c
deleted file mode 100644
index 2784036cd8b1..000000000000
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/localtimer.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/clockchips.h>
14
15#include <asm/irq.h>
16#include <asm/localtimer.h>
17
18/*
19 * Setup the local clock events for a CPU.
20 */
21void __cpuinit local_timer_setup(struct clock_event_device *evt)
22{
23 evt->irq = IRQ_LOCALTIMER;
24 twd_timer_setup(evt);
25}
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
deleted file mode 100644
index d9cab02e23ca..000000000000
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach-types.h>
21
22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
24#include <plat/s5pv310.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
30
31#include <mach/map.h>
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = SMDKC210_UCON_DEFAULT,
52 .ulcon = SMDKC210_ULCON_DEFAULT,
53 .ufcon = SMDKC210_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = SMDKC210_UCON_DEFAULT,
59 .ulcon = SMDKC210_ULCON_DEFAULT,
60 .ufcon = SMDKC210_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = SMDKC210_UCON_DEFAULT,
66 .ulcon = SMDKC210_ULCON_DEFAULT,
67 .ufcon = SMDKC210_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = SMDKC210_UCON_DEFAULT,
73 .ulcon = SMDKC210_ULCON_DEFAULT,
74 .ufcon = SMDKC210_UFCON_DEFAULT,
75 },
76};
77
78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2),
81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif
87};
88
89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2),
92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94};
95
96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2),
99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif
105};
106
107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2),
110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112};
113
114static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_EINT(5),
122 .end = IRQ_EINT(5),
123 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
124 },
125};
126
127static struct smsc911x_platform_config smsc9215_config = {
128 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
131 .phy_interface = PHY_INTERFACE_MODE_MII,
132 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
133};
134
135static struct platform_device smdkc210_smsc911x = {
136 .name = "smsc911x",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
139 .resource = smdkc210_smsc911x_resources,
140 .dev = {
141 .platform_data = &smsc9215_config,
142 },
143};
144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
149static struct platform_device *smdkc210_devices[] __initdata = {
150 &s3c_device_hsmmc0,
151 &s3c_device_hsmmc1,
152 &s3c_device_hsmmc2,
153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
155 &s3c_device_rtc,
156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
166 &s5pv310_device_sysmmu,
167 &samsung_asoc_dma,
168 &smdkc210_smsc911x,
169};
170
171static void __init smdkc210_smsc911x_init(void)
172{
173 u32 cs1;
174
175 /* configure nCS1 width to 16 bits */
176 cs1 = __raw_readl(S5P_SROM_BW) &
177 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
178 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
179 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
180 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
181 S5P_SROM_BW__NCS1__SHIFT;
182 __raw_writel(cs1, S5P_SROM_BW);
183
184 /* set timing for nCS1 suitable for ethernet chip */
185 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
186 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
187 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
188 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
189 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
190 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
191 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
192}
193
194static void __init smdkc210_map_io(void)
195{
196 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
197 s3c24xx_init_clocks(24000000);
198 s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
199}
200
201static void __init smdkc210_machine_init(void)
202{
203 s3c_i2c1_set_platdata(NULL);
204 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
205
206 smdkc210_smsc911x_init();
207
208 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
209 s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
210 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
212
213 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
214}
215
216MACHINE_START(SMDKC210, "SMDKC210")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 .boot_params = S5P_PA_SDRAM + 0x100,
219 .init_irq = s5pv310_init_irq,
220 .map_io = smdkc210_map_io,
221 .init_machine = smdkc210_machine_init,
222 .timer = &s5pv310_timer,
223MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
deleted file mode 100644
index b1cddbf3c616..000000000000
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach-types.h>
21
22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
24#include <plat/s5pv310.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
30
31#include <mach/map.h>
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = SMDKV310_UCON_DEFAULT,
52 .ulcon = SMDKV310_ULCON_DEFAULT,
53 .ufcon = SMDKV310_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = SMDKV310_UCON_DEFAULT,
59 .ulcon = SMDKV310_ULCON_DEFAULT,
60 .ufcon = SMDKV310_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = SMDKV310_UCON_DEFAULT,
66 .ulcon = SMDKV310_ULCON_DEFAULT,
67 .ufcon = SMDKV310_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = SMDKV310_UCON_DEFAULT,
73 .ulcon = SMDKV310_ULCON_DEFAULT,
74 .ufcon = SMDKV310_UFCON_DEFAULT,
75 },
76};
77
78static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2),
81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif
87};
88
89static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2),
92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94};
95
96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2),
99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif
105};
106
107static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2),
110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112};
113
114static struct resource smdkv310_smsc911x_resources[] = {
115 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_EINT(5),
122 .end = IRQ_EINT(5),
123 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
124 },
125};
126
127static struct smsc911x_platform_config smsc9215_config = {
128 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
129 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
130 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
131 .phy_interface = PHY_INTERFACE_MODE_MII,
132 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
133};
134
135static struct platform_device smdkv310_smsc911x = {
136 .name = "smsc911x",
137 .id = -1,
138 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
139 .resource = smdkv310_smsc911x_resources,
140 .dev = {
141 .platform_data = &smsc9215_config,
142 },
143};
144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
149static struct platform_device *smdkv310_devices[] __initdata = {
150 &s3c_device_hsmmc0,
151 &s3c_device_hsmmc1,
152 &s3c_device_hsmmc2,
153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
155 &s3c_device_rtc,
156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
166 &s5pv310_device_sysmmu,
167 &samsung_asoc_dma,
168 &smdkv310_smsc911x,
169};
170
171static void __init smdkv310_smsc911x_init(void)
172{
173 u32 cs1;
174
175 /* configure nCS1 width to 16 bits */
176 cs1 = __raw_readl(S5P_SROM_BW) &
177 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
178 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
179 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
180 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
181 S5P_SROM_BW__NCS1__SHIFT;
182 __raw_writel(cs1, S5P_SROM_BW);
183
184 /* set timing for nCS1 suitable for ethernet chip */
185 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
186 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
187 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
188 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
189 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
190 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
191 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
192}
193
194static void __init smdkv310_map_io(void)
195{
196 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
197 s3c24xx_init_clocks(24000000);
198 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
199}
200
201static void __init smdkv310_machine_init(void)
202{
203 s3c_i2c1_set_platdata(NULL);
204 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
205
206 smdkv310_smsc911x_init();
207
208 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
209 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
210 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
211 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
212
213 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
214}
215
216MACHINE_START(SMDKV310, "SMDKV310")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
219 .boot_params = S5P_PA_SDRAM + 0x100,
220 .init_irq = s5pv310_init_irq,
221 .map_io = smdkv310_map_io,
222 .init_machine = smdkv310_machine_init,
223 .timer = &s5pv310_timer,
224MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
deleted file mode 100644
index 36bc3cf825e3..000000000000
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach-types.h>
22
23#include <plat/regs-serial.h>
24#include <plat/s5pv310.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG256 | \
43 S5PV210_UFCON_RXTRIG256)
44
45static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .ucon = UNIVERSAL_UCON_DEFAULT,
49 .ulcon = UNIVERSAL_ULCON_DEFAULT,
50 .ufcon = UNIVERSAL_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .ucon = UNIVERSAL_UCON_DEFAULT,
55 .ulcon = UNIVERSAL_ULCON_DEFAULT,
56 .ufcon = UNIVERSAL_UFCON_DEFAULT,
57 },
58 [2] = {
59 .hwport = 2,
60 .ucon = UNIVERSAL_UCON_DEFAULT,
61 .ulcon = UNIVERSAL_ULCON_DEFAULT,
62 .ufcon = UNIVERSAL_UFCON_DEFAULT,
63 },
64 [3] = {
65 .hwport = 3,
66 .ucon = UNIVERSAL_UCON_DEFAULT,
67 .ulcon = UNIVERSAL_ULCON_DEFAULT,
68 .ufcon = UNIVERSAL_UFCON_DEFAULT,
69 },
70};
71
72static struct gpio_keys_button universal_gpio_keys_tables[] = {
73 {
74 .code = KEY_VOLUMEUP,
75 .gpio = S5PV310_GPX2(0), /* XEINT16 */
76 .desc = "gpio-keys: KEY_VOLUMEUP",
77 .type = EV_KEY,
78 .active_low = 1,
79 .debounce_interval = 1,
80 }, {
81 .code = KEY_VOLUMEDOWN,
82 .gpio = S5PV310_GPX2(1), /* XEINT17 */
83 .desc = "gpio-keys: KEY_VOLUMEDOWN",
84 .type = EV_KEY,
85 .active_low = 1,
86 .debounce_interval = 1,
87 }, {
88 .code = KEY_CONFIG,
89 .gpio = S5PV310_GPX2(2), /* XEINT18 */
90 .desc = "gpio-keys: KEY_CONFIG",
91 .type = EV_KEY,
92 .active_low = 1,
93 .debounce_interval = 1,
94 }, {
95 .code = KEY_CAMERA,
96 .gpio = S5PV310_GPX2(3), /* XEINT19 */
97 .desc = "gpio-keys: KEY_CAMERA",
98 .type = EV_KEY,
99 .active_low = 1,
100 .debounce_interval = 1,
101 }, {
102 .code = KEY_OK,
103 .gpio = S5PV310_GPX3(5), /* XEINT29 */
104 .desc = "gpio-keys: KEY_OK",
105 .type = EV_KEY,
106 .active_low = 1,
107 .debounce_interval = 1,
108 },
109};
110
111static struct gpio_keys_platform_data universal_gpio_keys_data = {
112 .buttons = universal_gpio_keys_tables,
113 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
114};
115
116static struct platform_device universal_gpio_keys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &universal_gpio_keys_data,
120 },
121};
122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = S5PV310_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
190/* I2C0 */
191static struct i2c_board_info i2c0_devs[] __initdata = {
192 /* Camera, To be updated */
193};
194
195/* I2C1 */
196static struct i2c_board_info i2c1_devs[] __initdata = {
197 /* Gyro, To be updated */
198};
199
200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
208 &universal_gpio_keys,
209 &s5p_device_onenand,
210};
211
212static void __init universal_map_io(void)
213{
214 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
215 s3c24xx_init_clocks(24000000);
216 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
217}
218
219static void __init universal_machine_init(void)
220{
221 universal_sdhci_init();
222
223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
225
226 /* Last */
227 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
228}
229
230MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
231 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
232 .boot_params = S5P_PA_SDRAM + 0x100,
233 .init_irq = s5pv310_init_irq,
234 .map_io = universal_map_io,
235 .init_machine = universal_machine_init,
236 .timer = &s5pv310_timer,
237MACHINE_END
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
deleted file mode 100644
index 34093b069f67..000000000000
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ /dev/null
@@ -1,172 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/platsmp.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 *
8 * Copyright (C) 2002 ARM Ltd.
9 * All Rights Reserved
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/jiffies.h>
21#include <linux/smp.h>
22#include <linux/io.h>
23
24#include <asm/cacheflush.h>
25#include <asm/smp_scu.h>
26#include <asm/unified.h>
27
28#include <mach/hardware.h>
29#include <mach/regs-clock.h>
30
31extern void s5pv310_secondary_startup(void);
32
33/*
34 * control for which core is the next to come out of the secondary
35 * boot "holding pen"
36 */
37
38volatile int __cpuinitdata pen_release = -1;
39
40/*
41 * Write pen_release in a way that is guaranteed to be visible to all
42 * observers, irrespective of whether they're taking part in coherency
43 * or not. This is necessary for the hotplug code to work reliably.
44 */
45static void write_pen_release(int val)
46{
47 pen_release = val;
48 smp_wmb();
49 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
50 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
51}
52
53static void __iomem *scu_base_addr(void)
54{
55 return (void __iomem *)(S5P_VA_SCU);
56}
57
58static DEFINE_SPINLOCK(boot_lock);
59
60void __cpuinit platform_secondary_init(unsigned int cpu)
61{
62 /*
63 * if any interrupts are already enabled for the primary
64 * core (e.g. timer irq), then they will not have been enabled
65 * for us: do so
66 */
67 gic_secondary_init(0);
68
69 /*
70 * let the primary processor know we're out of the
71 * pen, then head off into the C entry point
72 */
73 write_pen_release(-1);
74
75 /*
76 * Synchronise with the boot thread.
77 */
78 spin_lock(&boot_lock);
79 spin_unlock(&boot_lock);
80}
81
82int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
83{
84 unsigned long timeout;
85
86 /*
87 * Set synchronisation state between this boot processor
88 * and the secondary one
89 */
90 spin_lock(&boot_lock);
91
92 /*
93 * The secondary processor is waiting to be released from
94 * the holding pen - release it, then wait for it to flag
95 * that it has been released by resetting pen_release.
96 *
97 * Note that "pen_release" is the hardware CPU ID, whereas
98 * "cpu" is Linux's internal ID.
99 */
100 write_pen_release(cpu);
101
102 /*
103 * Send the secondary CPU a soft interrupt, thereby causing
104 * the boot monitor to read the system wide flags register,
105 * and branch to the address found there.
106 */
107 smp_cross_call(cpumask_of(cpu), 1);
108
109 timeout = jiffies + (1 * HZ);
110 while (time_before(jiffies, timeout)) {
111 smp_rmb();
112 if (pen_release == -1)
113 break;
114
115 udelay(10);
116 }
117
118 /*
119 * now the secondary core is starting up let it run its
120 * calibrations, then wait for it to finish
121 */
122 spin_unlock(&boot_lock);
123
124 return pen_release != -1 ? -ENOSYS : 0;
125}
126
127/*
128 * Initialise the CPU possible map early - this describes the CPUs
129 * which may be present or become present in the system.
130 */
131
132void __init smp_init_cpus(void)
133{
134 void __iomem *scu_base = scu_base_addr();
135 unsigned int i, ncores;
136
137 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
138
139 /* sanity check */
140 if (ncores > NR_CPUS) {
141 printk(KERN_WARNING
142 "S5PV310: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n",
144 ncores, NR_CPUS);
145 ncores = NR_CPUS;
146 }
147
148 for (i = 0; i < ncores; i++)
149 set_cpu_possible(i, true);
150}
151
152void __init platform_smp_prepare_cpus(unsigned int max_cpus)
153{
154 int i;
155
156 /*
157 * Initialise the present map, which describes the set of CPUs
158 * actually populated at the present time.
159 */
160 for (i = 0; i < max_cpus; i++)
161 set_cpu_present(i, true);
162
163 scu_enable(scu_base_addr());
164
165 /*
166 * Write the address of secondary startup into the
167 * system-wide flags register. The boot monitor waits
168 * until it receives a soft interrupt, and then the
169 * secondary CPU branches to this address.
170 */
171 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
172}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c
deleted file mode 100644
index f47f8f3152ec..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c0.c
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * I2C0 GPIO configuration.
8 *
9 * Based on plat-s3c64xx/setup-i2c0.c
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16struct platform_device; /* don't need the contents */
17
18#include <linux/gpio.h>
19#include <plat/iic.h>
20#include <plat/gpio-cfg.h>
21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{
24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26}
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c
deleted file mode 100644
index 9d07e4e2f14c..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c1.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C1 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c
deleted file mode 100644
index 4163b1233daf..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c2.c
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C2 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-s5pv310/setup-i2c3.c
deleted file mode 100644
index 180f153d2a20..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c3.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c3.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C3 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-s5pv310/setup-i2c4.c
deleted file mode 100644
index 909e8dfc5316..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c4.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c4.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C4 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-s5pv310/setup-i2c5.c
deleted file mode 100644
index 5d0fa4ac0283..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c5.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c5.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C5 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-s5pv310/setup-i2c6.c
deleted file mode 100644
index 34aafab92ac4..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c6.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c6.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C6 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-s5pv310/setup-i2c7.c
deleted file mode 100644
index 9b25b8d18920..000000000000
--- a/arch/arm/mach-s5pv310/setup-i2c7.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c7.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C7 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
deleted file mode 100644
index 86d38cc49135..000000000000
--- a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h>
25
26void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio;
30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
36 }
37
38 switch (width) {
39 case 8:
40 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 }
46 case 4:
47 for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
51 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
52 }
53 default:
54 break;
55 }
56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 }
62}
63
64void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio;
68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 }
75
76 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
80 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 }
88}
89
90void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio;
94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
100 }
101
102 switch (width) {
103 case 8:
104 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 }
110 case 4:
111 for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
115 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
116 }
117 default:
118 break;
119 }
120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 }
126}
127
128void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio;
132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 }
139
140 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
144 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
145 }
146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 }
152}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
deleted file mode 100644
index db8358fc4662..000000000000
--- a/arch/arm/mach-s5pv310/setup-sdhci.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <linux/mmc/card.h>
20#include <linux/mmc/host.h>
21
22#include <plat/regs-sdhci.h>
23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25
26char *s5pv310_hsmmc_clksrcs[4] = {
27 [0] = NULL,
28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL,
31};
32
33void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card)
35{
36 u32 ctrl2, ctrl3;
37
38 /* don't need to alter anything acording to card-type */
39
40 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
41
42 /* select base clock source to HCLK */
43
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45
46 /*
47 * clear async mode, enable conflict mask, rx feedback ctrl, SD
48 * clk hold and no use debounce count
49 */
50
51 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
52 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
53 S3C_SDHCI_CTRL2_ENFBCLKRX |
54 S3C_SDHCI_CTRL2_DFCNT_NONE |
55 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
56
57 /* Tx and Rx feedback clock delay control */
58
59 if (ios->clock < 25 * 1000000)
60 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
61 S3C_SDHCI_CTRL3_FCSEL2 |
62 S3C_SDHCI_CTRL3_FCSEL1 |
63 S3C_SDHCI_CTRL3_FCSEL0);
64 else
65 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
66
67 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
68 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
69}
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-s5pv310/time.c
deleted file mode 100644
index b262d4615331..000000000000
--- a/arch/arm/mach-s5pv310/time.c
+++ /dev/null
@@ -1,283 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/time.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 (and compatible) HRT support
7 * PWM 2/4 is used for this feature
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/clockchips.h>
20#include <linux/platform_device.h>
21
22#include <asm/smp_twd.h>
23
24#include <mach/map.h>
25#include <plat/regs-timer.h>
26#include <asm/mach/time.h>
27
28static unsigned long clock_count_per_tick;
29
30static struct clk *tin2;
31static struct clk *tin4;
32static struct clk *tdiv2;
33static struct clk *tdiv4;
34static struct clk *timerclk;
35
36static void s5pv310_pwm_stop(unsigned int pwm_id)
37{
38 unsigned long tcon;
39
40 tcon = __raw_readl(S3C2410_TCON);
41
42 switch (pwm_id) {
43 case 2:
44 tcon &= ~S3C2410_TCON_T2START;
45 break;
46 case 4:
47 tcon &= ~S3C2410_TCON_T4START;
48 break;
49 default:
50 break;
51 }
52 __raw_writel(tcon, S3C2410_TCON);
53}
54
55static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{
57 unsigned long tcon;
58
59 tcon = __raw_readl(S3C2410_TCON);
60
61 /* timers reload after counting zero, so reduce the count by 1 */
62 tcnt--;
63
64 /* ensure timer is stopped... */
65 switch (pwm_id) {
66 case 2:
67 tcon &= ~(0xf<<12);
68 tcon |= S3C2410_TCON_T2MANUALUPD;
69
70 __raw_writel(tcnt, S3C2410_TCNTB(2));
71 __raw_writel(tcnt, S3C2410_TCMPB(2));
72 __raw_writel(tcon, S3C2410_TCON);
73
74 break;
75 case 4:
76 tcon &= ~(7<<20);
77 tcon |= S3C2410_TCON_T4MANUALUPD;
78
79 __raw_writel(tcnt, S3C2410_TCNTB(4));
80 __raw_writel(tcnt, S3C2410_TCMPB(4));
81 __raw_writel(tcon, S3C2410_TCON);
82
83 break;
84 default:
85 break;
86 }
87}
88
89static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
90{
91 unsigned long tcon;
92
93 tcon = __raw_readl(S3C2410_TCON);
94
95 switch (pwm_id) {
96 case 2:
97 tcon |= S3C2410_TCON_T2START;
98 tcon &= ~S3C2410_TCON_T2MANUALUPD;
99
100 if (periodic)
101 tcon |= S3C2410_TCON_T2RELOAD;
102 else
103 tcon &= ~S3C2410_TCON_T2RELOAD;
104 break;
105 case 4:
106 tcon |= S3C2410_TCON_T4START;
107 tcon &= ~S3C2410_TCON_T4MANUALUPD;
108
109 if (periodic)
110 tcon |= S3C2410_TCON_T4RELOAD;
111 else
112 tcon &= ~S3C2410_TCON_T4RELOAD;
113 break;
114 default:
115 break;
116 }
117 __raw_writel(tcon, S3C2410_TCON);
118}
119
120static int s5pv310_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122{
123 s5pv310_pwm_init(2, cycles);
124 s5pv310_pwm_start(2, 0);
125 return 0;
126}
127
128static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
130{
131 s5pv310_pwm_stop(2);
132
133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC:
135 s5pv310_pwm_init(2, clock_count_per_tick);
136 s5pv310_pwm_start(2, 1);
137 break;
138 case CLOCK_EVT_MODE_ONESHOT:
139 break;
140 case CLOCK_EVT_MODE_UNUSED:
141 case CLOCK_EVT_MODE_SHUTDOWN:
142 case CLOCK_EVT_MODE_RESUME:
143 break;
144 }
145}
146
147static struct clock_event_device pwm_event_device = {
148 .name = "pwm_timer2",
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200,
151 .shift = 32,
152 .set_next_event = s5pv310_pwm_set_next_event,
153 .set_mode = s5pv310_pwm_set_mode,
154};
155
156irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &pwm_event_device;
159
160 evt->event_handler(evt);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction s5pv310_clock_event_irq = {
166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = s5pv310_clock_event_isr,
169};
170
171static void __init s5pv310_clockevent_init(void)
172{
173 unsigned long pclk;
174 unsigned long clock_rate;
175 struct clk *tscaler;
176
177 pclk = clk_get_rate(timerclk);
178
179 /* configure clock tick */
180
181 tscaler = clk_get_parent(tdiv2);
182
183 clk_set_rate(tscaler, pclk / 2);
184 clk_set_rate(tdiv2, pclk / 2);
185 clk_set_parent(tin2, tdiv2);
186
187 clock_rate = clk_get_rate(tin2);
188
189 clock_count_per_tick = clock_rate / HZ;
190
191 pwm_event_device.mult =
192 div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
193 pwm_event_device.max_delta_ns =
194 clockevent_delta2ns(-1, &pwm_event_device);
195 pwm_event_device.min_delta_ns =
196 clockevent_delta2ns(1, &pwm_event_device);
197
198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device);
200
201 setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
202}
203
204static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207}
208
209struct clocksource pwm_clocksource = {
210 .name = "pwm_timer4",
211 .rating = 250,
212 .read = s5pv310_pwm4_read,
213 .mask = CLOCKSOURCE_MASK(32),
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
215};
216
217static void __init s5pv310_clocksource_init(void)
218{
219 unsigned long pclk;
220 unsigned long clock_rate;
221
222 pclk = clk_get_rate(timerclk);
223
224 clk_set_rate(tdiv4, pclk / 2);
225 clk_set_parent(tin4, tdiv4);
226
227 clock_rate = clk_get_rate(tin4);
228
229 s5pv310_pwm_init(4, ~0);
230 s5pv310_pwm_start(4, 1);
231
232 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
233 panic("%s: can't register clocksource\n", pwm_clocksource.name);
234}
235
236static void __init s5pv310_timer_resources(void)
237{
238 struct platform_device tmpdev;
239
240 tmpdev.dev.bus = &platform_bus_type;
241
242 timerclk = clk_get(NULL, "timers");
243 if (IS_ERR(timerclk))
244 panic("failed to get timers clock for system timer");
245
246 clk_enable(timerclk);
247
248 tmpdev.id = 2;
249 tin2 = clk_get(&tmpdev.dev, "pwm-tin");
250 if (IS_ERR(tin2))
251 panic("failed to get pwm-tin2 clock for system timer");
252
253 tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
254 if (IS_ERR(tdiv2))
255 panic("failed to get pwm-tdiv2 clock for system timer");
256 clk_enable(tin2);
257
258 tmpdev.id = 4;
259 tin4 = clk_get(&tmpdev.dev, "pwm-tin");
260 if (IS_ERR(tin4))
261 panic("failed to get pwm-tin4 clock for system timer");
262
263 tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
264 if (IS_ERR(tdiv4))
265 panic("failed to get pwm-tdiv4 clock for system timer");
266
267 clk_enable(tin4);
268}
269
270static void __init s5pv310_timer_init(void)
271{
272#ifdef CONFIG_LOCAL_TIMERS
273 twd_base = S5P_VA_TWD;
274#endif
275
276 s5pv310_timer_resources();
277 s5pv310_clockevent_init();
278 s5pv310_clocksource_init();
279}
280
281struct sys_timer s5pv310_timer = {
282 .init = s5pv310_timer_init,
283};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 14:46:07 -0500