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-rw-r--r--arch/arm/mach-s5pv310/Kconfig21
-rw-r--r--arch/arm/mach-s5pv310/Makefile6
-rw-r--r--arch/arm/mach-s5pv310/clock.c77
-rw-r--r--arch/arm/mach-s5pv310/cpu.c21
-rw-r--r--arch/arm/mach-s5pv310/cpufreq.c580
-rw-r--r--arch/arm/mach-s5pv310/dev-pd.c139
-rw-r--r--arch/arm/mach-s5pv310/dev-sysmmu.c187
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h34
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h29
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h80
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-mem.h23
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-pmu.h30
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-srom.h50
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h24
-rw-r--r--arch/arm/mach-s5pv310/include/mach/sysmmu.h119
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c32
-rw-r--r--arch/arm/mach-s5pv310/irq-eint.c55
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkc210.c52
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkv310.c52
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c80
20 files changed, 1540 insertions, 151 deletions
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index d64efe0d4c97..09c4c21b70cc 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -15,6 +15,11 @@ config CPU_S5PV310
15 help 15 help
16 Enable S5PV310 CPU support 16 Enable S5PV310 CPU support
17 17
18config S5PV310_DEV_PD
19 bool
20 help
21 Compile in platform device definitions for Power Domain
22
18config S5PV310_SETUP_I2C1 23config S5PV310_SETUP_I2C1
19 bool 24 bool
20 help 25 help
@@ -61,6 +66,11 @@ config S5PV310_SETUP_SDHCI_GPIO
61 help 66 help
62 Common setup code for SDHCI gpio. 67 Common setup code for SDHCI gpio.
63 68
69config S5PV310_DEV_SYSMMU
70 bool
71 help
72 Common setup code for SYSTEM MMU in S5PV310
73
64# machine support 74# machine support
65 75
66menu "S5PC210 Machines" 76menu "S5PC210 Machines"
@@ -70,11 +80,15 @@ config MACH_SMDKC210
70 select CPU_S5PV310 80 select CPU_S5PV310
71 select S3C_DEV_RTC 81 select S3C_DEV_RTC
72 select S3C_DEV_WDT 82 select S3C_DEV_WDT
83 select S3C_DEV_I2C1
73 select S3C_DEV_HSMMC 84 select S3C_DEV_HSMMC
74 select S3C_DEV_HSMMC1 85 select S3C_DEV_HSMMC1
75 select S3C_DEV_HSMMC2 86 select S3C_DEV_HSMMC2
76 select S3C_DEV_HSMMC3 87 select S3C_DEV_HSMMC3
88 select S5PV310_DEV_PD
89 select S5PV310_SETUP_I2C1
77 select S5PV310_SETUP_SDHCI 90 select S5PV310_SETUP_SDHCI
91 select S5PV310_DEV_SYSMMU
78 help 92 help
79 Machine support for Samsung SMDKC210 93 Machine support for Samsung SMDKC210
80 S5PC210(MCP) is one of package option of S5PV310 94 S5PC210(MCP) is one of package option of S5PV310
@@ -83,6 +97,10 @@ config MACH_UNIVERSAL_C210
83 bool "Mobile UNIVERSAL_C210 Board" 97 bool "Mobile UNIVERSAL_C210 Board"
84 select CPU_S5PV310 98 select CPU_S5PV310
85 select S5P_DEV_ONENAND 99 select S5P_DEV_ONENAND
100 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC2
102 select S3C_DEV_HSMMC3
103 select S5PV310_SETUP_SDHCI
86 select S3C_DEV_I2C1 104 select S3C_DEV_I2C1
87 select S5PV310_SETUP_I2C1 105 select S5PV310_SETUP_I2C1
88 help 106 help
@@ -98,10 +116,13 @@ config MACH_SMDKV310
98 select CPU_S5PV310 116 select CPU_S5PV310
99 select S3C_DEV_RTC 117 select S3C_DEV_RTC
100 select S3C_DEV_WDT 118 select S3C_DEV_WDT
119 select S3C_DEV_I2C1
101 select S3C_DEV_HSMMC 120 select S3C_DEV_HSMMC
102 select S3C_DEV_HSMMC1 121 select S3C_DEV_HSMMC1
103 select S3C_DEV_HSMMC2 122 select S3C_DEV_HSMMC2
104 select S3C_DEV_HSMMC3 123 select S3C_DEV_HSMMC3
124 select S5PV310_DEV_PD
125 select S5PV310_SETUP_I2C1
105 select S5PV310_SETUP_SDHCI 126 select S5PV310_SETUP_SDHCI
106 help 127 help
107 Machine support for Samsung SMDKV310 128 Machine support for Samsung SMDKV310
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 61e3cb654269..036fb383b830 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -14,6 +14,7 @@ obj- :=
14 14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o 16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
17 18
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 20obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
@@ -27,7 +28,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
27 28
28# device support 29# device support
29 30
30obj-y += dev-audio.o 31obj-y += dev-audio.o
32obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
33obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
34
31obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o 35obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
32obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o 36obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
33obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o 37obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 58c9d33f36fe..fc7c2f8d165e 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
244 .id = -1, 244 .id = -1,
245 }, 245 },
246 .sources = &clkset_mout_corebus, 246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, 247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
248}; 248};
249 249
250static struct clksrc_clk clk_sclk_dmc = { 250static struct clksrc_clk clk_sclk_dmc = {
@@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
253 .id = -1, 253 .id = -1,
254 .parent = &clk_mout_corebus.clk, 254 .parent = &clk_mout_corebus.clk,
255 }, 255 },
256 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, 256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
257}; 257};
258 258
259static struct clksrc_clk clk_aclk_cored = { 259static struct clksrc_clk clk_aclk_cored = {
@@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
262 .id = -1, 262 .id = -1,
263 .parent = &clk_sclk_dmc.clk, 263 .parent = &clk_sclk_dmc.clk,
264 }, 264 },
265 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, 265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
266}; 266};
267 267
268static struct clksrc_clk clk_aclk_corep = { 268static struct clksrc_clk clk_aclk_corep = {
@@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
271 .id = -1, 271 .id = -1,
272 .parent = &clk_aclk_cored.clk, 272 .parent = &clk_aclk_cored.clk,
273 }, 273 },
274 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
275}; 275};
276 276
277static struct clksrc_clk clk_aclk_acp = { 277static struct clksrc_clk clk_aclk_acp = {
@@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
280 .id = -1, 280 .id = -1,
281 .parent = &clk_mout_corebus.clk, 281 .parent = &clk_mout_corebus.clk,
282 }, 282 },
283 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, 283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
284}; 284};
285 285
286static struct clksrc_clk clk_pclk_acp = { 286static struct clksrc_clk clk_pclk_acp = {
@@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
289 .id = -1, 289 .id = -1,
290 .parent = &clk_aclk_acp.clk, 290 .parent = &clk_aclk_acp.clk,
291 }, 291 },
292 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, 292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
293}; 293};
294 294
295/* Core list of CMU_TOP side */ 295/* Core list of CMU_TOP side */
@@ -384,7 +384,7 @@ static struct clksrc_clk clk_sclk_vpll = {
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
385}; 385};
386 386
387static struct clk init_clocks_disable[] = { 387static struct clk init_clocks_off[] = {
388 { 388 {
389 .name = "timers", 389 .name = "timers",
390 .id = -1, 390 .id = -1,
@@ -467,6 +467,16 @@ static struct clk init_clocks_disable[] = {
467 .enable = s5pv310_clk_ip_fsys_ctrl, 467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10), 468 .ctrlbit = (1 << 10),
469 }, { 469 }, {
470 .name = "pdma",
471 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0),
474 }, {
475 .name = "pdma",
476 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1),
479 }, {
470 .name = "adc", 480 .name = "adc",
471 .id = -1, 481 .id = -1,
472 .enable = s5pv310_clk_ip_peril_ctrl, 482 .enable = s5pv310_clk_ip_peril_ctrl,
@@ -507,6 +517,26 @@ static struct clk init_clocks_disable[] = {
507 .enable = s5pv310_clk_ip_peril_ctrl, 517 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 18), 518 .ctrlbit = (1 << 18),
509 }, { 519 }, {
520 .name = "iis",
521 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19),
524 }, {
525 .name = "iis",
526 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20),
529 }, {
530 .name = "iis",
531 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21),
534 }, {
535 .name = "ac97",
536 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27),
539 }, {
510 .name = "fimg2d", 540 .name = "fimg2d",
511 .id = -1, 541 .id = -1,
512 .enable = s5pv310_clk_ip_image_ctrl, 542 .enable = s5pv310_clk_ip_image_ctrl,
@@ -990,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = {
990 &clk_dout_mmc4, 1020 &clk_dout_mmc4,
991}; 1021};
992 1022
1023static int xtal_rate;
1024
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
1026{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028}
1029
1030static struct clk_ops s5pv310_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate,
1032};
1033
993void __init_or_cpufreq s5pv310_setup_clocks(void) 1034void __init_or_cpufreq s5pv310_setup_clocks(void)
994{ 1035{
995 struct clk *xtal_clk; 1036 struct clk *xtal_clk;
@@ -1013,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1013 BUG_ON(IS_ERR(xtal_clk)); 1054 BUG_ON(IS_ERR(xtal_clk));
1014 1055
1015 xtal = clk_get_rate(xtal_clk); 1056 xtal = clk_get_rate(xtal_clk);
1057
1058 xtal_rate = xtal;
1059
1016 clk_put(xtal_clk); 1060 clk_put(xtal_clk);
1017 1061
1018 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1062 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
@@ -1026,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1026 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1027 __raw_readl(S5P_VPLL_CON1), pll_4650); 1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1028 1072
1029 clk_fout_apll.rate = apll; 1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops;
1030 clk_fout_mpll.rate = mpll; 1074 clk_fout_mpll.rate = mpll;
1031 clk_fout_epll.rate = epll; 1075 clk_fout_epll.rate = epll;
1032 clk_fout_vpll.rate = vpll; 1076 clk_fout_vpll.rate = vpll;
@@ -1061,13 +1105,9 @@ static struct clk *clks[] __initdata = {
1061 1105
1062void __init s5pv310_register_clocks(void) 1106void __init s5pv310_register_clocks(void)
1063{ 1107{
1064 struct clk *clkp;
1065 int ret;
1066 int ptr; 1108 int ptr;
1067 1109
1068 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 1110 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1069 if (ret > 0)
1070 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1071 1111
1072 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 1112 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1073 s3c_register_clksrc(sysclks[ptr], 1); 1113 s3c_register_clksrc(sysclks[ptr], 1);
@@ -1075,15 +1115,8 @@ void __init s5pv310_register_clocks(void)
1075 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1115 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1076 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1116 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1077 1117
1078 clkp = init_clocks_disable; 1118 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1079 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 1119 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1080 ret = s3c24xx_register_clock(clkp);
1081 if (ret < 0) {
1082 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1083 clkp->name, ret);
1084 }
1085 (clkp->enable)(clkp, 0);
1086 }
1087 1120
1088 s3c_pwmclk_init(); 1121 s3c_pwmclk_init();
1089} 1122}
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 72ab289e7816..0db0fb65bd70 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -41,6 +41,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
41 .length = SZ_128K, 41 .length = SZ_128K,
42 .type = MT_DEVICE, 42 .type = MT_DEVICE,
43 }, { 43 }, {
44 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU),
46 .length = SZ_64K,
47 .type = MT_DEVICE,
48 }, {
44 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
45 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), 50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
46 .length = SZ_4K, 51 .length = SZ_4K,
@@ -71,6 +76,11 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
71 .length = SZ_256, 76 .length = SZ_256,
72 .type = MT_DEVICE, 77 .type = MT_DEVICE,
73 }, { 78 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 }, {
74 .virtual = (unsigned long)S3C_VA_UART, 84 .virtual = (unsigned long)S3C_VA_UART,
75 .pfn = __phys_to_pfn(S3C_PA_UART), 85 .pfn = __phys_to_pfn(S3C_PA_UART),
76 .length = SZ_512K, 86 .length = SZ_512K,
@@ -123,6 +133,15 @@ void __init s5pv310_init_irq(void)
123 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 133 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
124 134
125 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 135 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
136
137 /*
138 * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
139 * connected to the interrupt combiner. These irqs
140 * should be initialized to support cascade interrupt.
141 */
142 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
143 continue;
144
126 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 145 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
127 COMBINER_IRQ(irq, 0)); 146 COMBINER_IRQ(irq, 0));
128 combiner_cascade_irq(irq, IRQ_SPI(irq)); 147 combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -164,7 +183,7 @@ static int __init s5pv310_l2x0_cache_init(void)
164 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 183 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
165 S5P_VA_L2CC + L2X0_POWER_CTRL); 184 S5P_VA_L2CC + L2X0_POWER_CTRL);
166 185
167 l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); 186 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
168 187
169 return 0; 188 return 0;
170} 189}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-s5pv310/cpufreq.c
new file mode 100644
index 000000000000..b04cbc731128
--- /dev/null
+++ b/arch/arm/mach-s5pv310/cpufreq.c
@@ -0,0 +1,580 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - CPU frequency scaling support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/regulator/consumer.h>
20#include <linux/cpufreq.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24#include <mach/regs-mem.h>
25
26#include <plat/clock.h>
27#include <plat/pm.h>
28
29static struct clk *cpu_clk;
30static struct clk *moutcore;
31static struct clk *mout_mpll;
32static struct clk *mout_apll;
33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator;
36static struct regulator *int_regulator;
37#endif
38
39static struct cpufreq_freqs freqs;
40static unsigned int memtype;
41
42enum s5pv310_memory_type {
43 DDR2 = 4,
44 LPDDR2,
45 DDR3,
46};
47
48enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50};
51
52static struct cpufreq_frequency_table s5pv310_freq_table[] = {
53 {L0, 1000*1000},
54 {L1, 800*1000},
55 {L2, 400*1000},
56 {L3, 100*1000},
57 {0, CPUFREQ_TABLE_END},
58};
59
60static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
61 /*
62 * Clock divider value for following
63 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
64 * DIVATB, DIVPCLK_DBG, DIVAPLL }
65 */
66
67 /* ARM L0: 1000MHz */
68 { 0, 3, 7, 3, 3, 0, 1 },
69
70 /* ARM L1: 800MHz */
71 { 0, 3, 7, 3, 3, 0, 1 },
72
73 /* ARM L2: 400MHz */
74 { 0, 1, 3, 1, 3, 0, 1 },
75
76 /* ARM L3: 100MHz */
77 { 0, 0, 1, 0, 3, 1, 1 },
78};
79
80static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
81 /*
82 * Clock divider value for following
83 * { DIVCOPY, DIVHPM }
84 */
85
86 /* ARM L0: 1000MHz */
87 { 3, 0 },
88
89 /* ARM L1: 800MHz */
90 { 3, 0 },
91
92 /* ARM L2: 400MHz */
93 { 3, 0 },
94
95 /* ARM L3: 100MHz */
96 { 3, 0 },
97};
98
99static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
100 /*
101 * Clock divider value for following
102 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
103 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
104 */
105
106 /* DMC L0: 400MHz */
107 { 3, 1, 1, 1, 1, 1, 3, 1 },
108
109 /* DMC L1: 400MHz */
110 { 3, 1, 1, 1, 1, 1, 3, 1 },
111
112 /* DMC L2: 266.7MHz */
113 { 7, 1, 1, 2, 1, 1, 3, 1 },
114
115 /* DMC L3: 200MHz */
116 { 7, 1, 1, 3, 1, 1, 3, 1 },
117};
118
119static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
120 /*
121 * Clock divider value for following
122 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
123 */
124
125 /* ACLK200 L0: 200MHz */
126 { 3, 7, 4, 5, 1 },
127
128 /* ACLK200 L1: 200MHz */
129 { 3, 7, 4, 5, 1 },
130
131 /* ACLK200 L2: 160MHz */
132 { 4, 7, 5, 7, 1 },
133
134 /* ACLK200 L3: 133.3MHz */
135 { 5, 7, 7, 7, 1 },
136};
137
138static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
139 /*
140 * Clock divider value for following
141 * { DIVGDL/R, DIVGPL/R }
142 */
143
144 /* ACLK_GDL/R L0: 200MHz */
145 { 3, 1 },
146
147 /* ACLK_GDL/R L1: 200MHz */
148 { 3, 1 },
149
150 /* ACLK_GDL/R L2: 160MHz */
151 { 4, 1 },
152
153 /* ACLK_GDL/R L3: 133.3MHz */
154 { 5, 1 },
155};
156
157struct cpufreq_voltage_table {
158 unsigned int index; /* any */
159 unsigned int arm_volt; /* uV */
160 unsigned int int_volt;
161};
162
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
164 {
165 .index = L0,
166 .arm_volt = 1200000,
167 .int_volt = 1100000,
168 }, {
169 .index = L1,
170 .arm_volt = 1100000,
171 .int_volt = 1100000,
172 }, {
173 .index = L2,
174 .arm_volt = 1000000,
175 .int_volt = 1000000,
176 }, {
177 .index = L3,
178 .arm_volt = 900000,
179 .int_volt = 1000000,
180 },
181};
182
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1),
186
187 /* APLL FOUT L1: 800MHz */
188 ((200 << 16) | (6 << 8) | 1),
189
190 /* APLL FOUT L2 : 400MHz */
191 ((200 << 16) | (6 << 8) | 2),
192
193 /* APLL FOUT L3: 100MHz */
194 ((200 << 16) | (6 << 8) | 4),
195};
196
197int s5pv310_verify_speed(struct cpufreq_policy *policy)
198{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
200}
201
202unsigned int s5pv310_getspeed(unsigned int cpu)
203{
204 return clk_get_rate(cpu_clk) / 1000;
205}
206
207void s5pv310_set_clkdiv(unsigned int div_index)
208{
209 unsigned int tmp;
210
211 /* Change Divider - CPU0 */
212
213 tmp = __raw_readl(S5P_CLKDIV_CPU);
214
215 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
216 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
217 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
218 S5P_CLKDIV_CPU0_APLL_MASK);
219
220 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
221 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
222 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
223 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
224 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
225 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
226 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
227
228 __raw_writel(tmp, S5P_CLKDIV_CPU);
229
230 do {
231 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
232 } while (tmp & 0x1111111);
233
234 /* Change Divider - CPU1 */
235
236 tmp = __raw_readl(S5P_CLKDIV_CPU1);
237
238 tmp &= ~((0x7 << 4) | 0x7);
239
240 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
241 (clkdiv_cpu1[div_index][1] << 0));
242
243 __raw_writel(tmp, S5P_CLKDIV_CPU1);
244
245 do {
246 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
247 } while (tmp & 0x11);
248
249 /* Change Divider - DMC0 */
250
251 tmp = __raw_readl(S5P_CLKDIV_DMC0);
252
253 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
254 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
255 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
256 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
257
258 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
259 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
260 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
261 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
262 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
263 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
264 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
265 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
266
267 __raw_writel(tmp, S5P_CLKDIV_DMC0);
268
269 do {
270 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
271 } while (tmp & 0x11111111);
272
273 /* Change Divider - TOP */
274
275 tmp = __raw_readl(S5P_CLKDIV_TOP);
276
277 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
278 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
279 S5P_CLKDIV_TOP_ONENAND_MASK);
280
281 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
282 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
283 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
284 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
285 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
286
287 __raw_writel(tmp, S5P_CLKDIV_TOP);
288
289 do {
290 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
291 } while (tmp & 0x11111);
292
293 /* Change Divider - LEFTBUS */
294
295 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
296
297 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
298
299 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
300 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
301
302 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
303
304 do {
305 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
306 } while (tmp & 0x11);
307
308 /* Change Divider - RIGHTBUS */
309
310 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
311
312 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
313
314 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
315 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
316
317 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
318
319 do {
320 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
321 } while (tmp & 0x11);
322}
323
324static void s5pv310_set_apll(unsigned int index)
325{
326 unsigned int tmp;
327
328 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
329 clk_set_parent(moutcore, mout_mpll);
330
331 do {
332 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
333 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
334 tmp &= 0x7;
335 } while (tmp != 0x2);
336
337 /* 2. Set APLL Lock time */
338 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
339
340 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0);
345
346 /* 4. wait_lock_time */
347 do {
348 tmp = __raw_readl(S5P_APLL_CON0);
349 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
350
351 /* 5. MUX_CORE_SEL = APLL */
352 clk_set_parent(moutcore, mout_apll);
353
354 do {
355 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
356 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358}
359
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
361{
362 unsigned int tmp;
363
364 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index);
369
370 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index);
372 } else {
373 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index);
375
376 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0);
381 }
382 }
383
384 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index);
389
390 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index);
392 } else {
393 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0);
398
399 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index);
401 }
402 }
403}
404
405static int s5pv310_target(struct cpufreq_policy *policy,
406 unsigned int target_freq,
407 unsigned int relation)
408{
409 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt;
411
412 freqs.old = s5pv310_getspeed(policy->cpu);
413
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
415 freqs.old, relation, &old_index))
416 return -EINVAL;
417
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
419 target_freq, relation, &index))
420 return -EINVAL;
421
422 freqs.new = s5pv310_freq_table[index].frequency;
423 freqs.cpu = policy->cpu;
424
425 if (freqs.new == freqs.old)
426 return 0;
427
428 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt;
431
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433
434 /* control regulator */
435 if (freqs.new > freqs.old) {
436 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 }
442
443 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index);
445
446 /* control regulator */
447 if (freqs.new < freqs.old) {
448 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 }
454
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
456
457 return 0;
458}
459
460#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg)
463{
464 return 0;
465}
466
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
468{
469 return 0;
470}
471#endif
472
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
476
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
478
479 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000;
481
482 /*
483 * S5PV310 multi-core processors has 2 cores
484 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus.
487 */
488 cpumask_setall(policy->cpus);
489
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
491}
492
493static struct cpufreq_driver s5pv310_driver = {
494 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed,
496 .target = s5pv310_target,
497 .get = s5pv310_getspeed,
498 .init = s5pv310_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq",
500#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume,
503#endif
504};
505
506static int __init s5pv310_cpufreq_init(void)
507{
508 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk))
510 return PTR_ERR(cpu_clk);
511
512 moutcore = clk_get(NULL, "moutcore");
513 if (IS_ERR(moutcore))
514 goto out;
515
516 mout_mpll = clk_get(NULL, "mout_mpll");
517 if (IS_ERR(mout_mpll))
518 goto out;
519
520 mout_apll = clk_get(NULL, "mout_apll");
521 if (IS_ERR(mout_apll))
522 goto out;
523
524#ifdef CONFIG_REGULATOR
525 arm_regulator = regulator_get(NULL, "vdd_arm");
526 if (IS_ERR(arm_regulator)) {
527 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
528 goto out;
529 }
530
531 int_regulator = regulator_get(NULL, "vdd_int");
532 if (IS_ERR(int_regulator)) {
533 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
534 goto out;
535 }
536#endif
537
538 /*
539 * Check DRAM type.
540 * Because DVFS level is different according to DRAM type.
541 */
542 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
543 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
544 memtype &= S5P_DMC0_MEMTYPE_MASK;
545
546 if ((memtype < DDR2) && (memtype > DDR3)) {
547 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
548 goto out;
549 } else {
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 }
552
553 return cpufreq_register_driver(&s5pv310_driver);
554
555out:
556 if (!IS_ERR(cpu_clk))
557 clk_put(cpu_clk);
558
559 if (!IS_ERR(moutcore))
560 clk_put(moutcore);
561
562 if (!IS_ERR(mout_mpll))
563 clk_put(mout_mpll);
564
565 if (!IS_ERR(mout_apll))
566 clk_put(mout_apll);
567
568#ifdef CONFIG_REGULATOR
569 if (!IS_ERR(arm_regulator))
570 regulator_put(arm_regulator);
571
572 if (!IS_ERR(int_regulator))
573 regulator_put(int_regulator);
574#endif
575
576 printk(KERN_ERR "%s: failed initialization\n", __func__);
577
578 return -EINVAL;
579}
580late_initcall(s5pv310_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-s5pv310/dev-pd.c
new file mode 100644
index 000000000000..58a50c2d0b67
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-pd.c
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5pv310/dev-pd.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power Domain support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17
18#include <mach/regs-pmu.h>
19
20#include <plat/pd.h>
21
22static int s5pv310_pd_enable(struct device *dev)
23{
24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout;
26
27 __raw_writel(S5P_INT_LOCAL_PWR_EN, pdata->base);
28
29 /* Wait max 1ms */
30 timeout = 10;
31 while ((__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN)
32 != S5P_INT_LOCAL_PWR_EN) {
33 if (timeout == 0) {
34 printk(KERN_ERR "Power domain %s enable failed.\n",
35 dev_name(dev));
36 return -ETIMEDOUT;
37 }
38 timeout--;
39 udelay(100);
40 }
41
42 return 0;
43}
44
45static int s5pv310_pd_disable(struct device *dev)
46{
47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout;
49
50 __raw_writel(0, pdata->base);
51
52 /* Wait max 1ms */
53 timeout = 10;
54 while (__raw_readl(pdata->base + 0x4) & S5P_INT_LOCAL_PWR_EN) {
55 if (timeout == 0) {
56 printk(KERN_ERR "Power domain %s disable failed.\n",
57 dev_name(dev));
58 return -ETIMEDOUT;
59 }
60 timeout--;
61 udelay(100);
62 }
63
64 return 0;
65}
66
67struct platform_device s5pv310_device_pd[] = {
68 {
69 .name = "samsung-pd",
70 .id = 0,
71 .dev = {
72 .platform_data = &(struct samsung_pd_info) {
73 .enable = s5pv310_pd_enable,
74 .disable = s5pv310_pd_disable,
75 .base = S5P_PMU_MFC_CONF,
76 },
77 },
78 }, {
79 .name = "samsung-pd",
80 .id = 1,
81 .dev = {
82 .platform_data = &(struct samsung_pd_info) {
83 .enable = s5pv310_pd_enable,
84 .disable = s5pv310_pd_disable,
85 .base = S5P_PMU_G3D_CONF,
86 },
87 },
88 }, {
89 .name = "samsung-pd",
90 .id = 2,
91 .dev = {
92 .platform_data = &(struct samsung_pd_info) {
93 .enable = s5pv310_pd_enable,
94 .disable = s5pv310_pd_disable,
95 .base = S5P_PMU_LCD0_CONF,
96 },
97 },
98 }, {
99 .name = "samsung-pd",
100 .id = 3,
101 .dev = {
102 .platform_data = &(struct samsung_pd_info) {
103 .enable = s5pv310_pd_enable,
104 .disable = s5pv310_pd_disable,
105 .base = S5P_PMU_LCD1_CONF,
106 },
107 },
108 }, {
109 .name = "samsung-pd",
110 .id = 4,
111 .dev = {
112 .platform_data = &(struct samsung_pd_info) {
113 .enable = s5pv310_pd_enable,
114 .disable = s5pv310_pd_disable,
115 .base = S5P_PMU_TV_CONF,
116 },
117 },
118 }, {
119 .name = "samsung-pd",
120 .id = 5,
121 .dev = {
122 .platform_data = &(struct samsung_pd_info) {
123 .enable = s5pv310_pd_enable,
124 .disable = s5pv310_pd_disable,
125 .base = S5P_PMU_CAM_CONF,
126 },
127 },
128 }, {
129 .name = "samsung-pd",
130 .id = 6,
131 .dev = {
132 .platform_data = &(struct samsung_pd_info) {
133 .enable = s5pv310_pd_enable,
134 .disable = s5pv310_pd_disable,
135 .base = S5P_PMU_GPS_CONF,
136 },
137 },
138 },
139};
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-s5pv310/dev-sysmmu.c
new file mode 100644
index 000000000000..e1bb200ac0f0
--- /dev/null
+++ b/arch/arm/mach-s5pv310/dev-sysmmu.c
@@ -0,0 +1,187 @@
1/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13
14#include <mach/map.h>
15#include <mach/irqs.h>
16
17static struct resource s5pv310_sysmmu_resource[] = {
18 [0] = {
19 .start = S5PV310_PA_SYSMMU_MDMA,
20 .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
21 .flags = IORESOURCE_MEM,
22 },
23 [1] = {
24 .start = IRQ_SYSMMU_MDMA0_0,
25 .end = IRQ_SYSMMU_MDMA0_0,
26 .flags = IORESOURCE_IRQ,
27 },
28 [2] = {
29 .start = S5PV310_PA_SYSMMU_SSS,
30 .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
31 .flags = IORESOURCE_MEM,
32 },
33 [3] = {
34 .start = IRQ_SYSMMU_SSS_0,
35 .end = IRQ_SYSMMU_SSS_0,
36 .flags = IORESOURCE_IRQ,
37 },
38 [4] = {
39 .start = S5PV310_PA_SYSMMU_FIMC0,
40 .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [5] = {
44 .start = IRQ_SYSMMU_FIMC0_0,
45 .end = IRQ_SYSMMU_FIMC0_0,
46 .flags = IORESOURCE_IRQ,
47 },
48 [6] = {
49 .start = S5PV310_PA_SYSMMU_FIMC1,
50 .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
51 .flags = IORESOURCE_MEM,
52 },
53 [7] = {
54 .start = IRQ_SYSMMU_FIMC1_0,
55 .end = IRQ_SYSMMU_FIMC1_0,
56 .flags = IORESOURCE_IRQ,
57 },
58 [8] = {
59 .start = S5PV310_PA_SYSMMU_FIMC2,
60 .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
61 .flags = IORESOURCE_MEM,
62 },
63 [9] = {
64 .start = IRQ_SYSMMU_FIMC2_0,
65 .end = IRQ_SYSMMU_FIMC2_0,
66 .flags = IORESOURCE_IRQ,
67 },
68 [10] = {
69 .start = S5PV310_PA_SYSMMU_FIMC3,
70 .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
71 .flags = IORESOURCE_MEM,
72 },
73 [11] = {
74 .start = IRQ_SYSMMU_FIMC3_0,
75 .end = IRQ_SYSMMU_FIMC3_0,
76 .flags = IORESOURCE_IRQ,
77 },
78 [12] = {
79 .start = S5PV310_PA_SYSMMU_JPEG,
80 .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
81 .flags = IORESOURCE_MEM,
82 },
83 [13] = {
84 .start = IRQ_SYSMMU_JPEG_0,
85 .end = IRQ_SYSMMU_JPEG_0,
86 .flags = IORESOURCE_IRQ,
87 },
88 [14] = {
89 .start = S5PV310_PA_SYSMMU_FIMD0,
90 .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [15] = {
94 .start = IRQ_SYSMMU_LCD0_M0_0,
95 .end = IRQ_SYSMMU_LCD0_M0_0,
96 .flags = IORESOURCE_IRQ,
97 },
98 [16] = {
99 .start = S5PV310_PA_SYSMMU_FIMD1,
100 .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [17] = {
104 .start = IRQ_SYSMMU_LCD1_M1_0,
105 .end = IRQ_SYSMMU_LCD1_M1_0,
106 .flags = IORESOURCE_IRQ,
107 },
108 [18] = {
109 .start = S5PV310_PA_SYSMMU_PCIe,
110 .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
111 .flags = IORESOURCE_MEM,
112 },
113 [19] = {
114 .start = IRQ_SYSMMU_PCIE_0,
115 .end = IRQ_SYSMMU_PCIE_0,
116 .flags = IORESOURCE_IRQ,
117 },
118 [20] = {
119 .start = S5PV310_PA_SYSMMU_G2D,
120 .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
121 .flags = IORESOURCE_MEM,
122 },
123 [21] = {
124 .start = IRQ_SYSMMU_2D_0,
125 .end = IRQ_SYSMMU_2D_0,
126 .flags = IORESOURCE_IRQ,
127 },
128 [22] = {
129 .start = S5PV310_PA_SYSMMU_ROTATOR,
130 .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 [23] = {
134 .start = IRQ_SYSMMU_ROTATOR_0,
135 .end = IRQ_SYSMMU_ROTATOR_0,
136 .flags = IORESOURCE_IRQ,
137 },
138 [24] = {
139 .start = S5PV310_PA_SYSMMU_MDMA2,
140 .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
141 .flags = IORESOURCE_MEM,
142 },
143 [25] = {
144 .start = IRQ_SYSMMU_MDMA1_0,
145 .end = IRQ_SYSMMU_MDMA1_0,
146 .flags = IORESOURCE_IRQ,
147 },
148 [26] = {
149 .start = S5PV310_PA_SYSMMU_TV,
150 .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 [27] = {
154 .start = IRQ_SYSMMU_TV_M0_0,
155 .end = IRQ_SYSMMU_TV_M0_0,
156 .flags = IORESOURCE_IRQ,
157 },
158 [28] = {
159 .start = S5PV310_PA_SYSMMU_MFC_L,
160 .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 [29] = {
164 .start = IRQ_SYSMMU_MFC_M0_0,
165 .end = IRQ_SYSMMU_MFC_M0_0,
166 .flags = IORESOURCE_IRQ,
167 },
168 [30] = {
169 .start = S5PV310_PA_SYSMMU_MFC_R,
170 .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 [31] = {
174 .start = IRQ_SYSMMU_MFC_M1_0,
175 .end = IRQ_SYSMMU_MFC_M1_0,
176 .flags = IORESOURCE_IRQ,
177 },
178};
179
180struct platform_device s5pv310_device_sysmmu = {
181 .name = "s5p-sysmmu",
182 .id = 32,
183 .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource),
184 .resource = s5pv310_sysmmu_resource,
185};
186
187EXPORT_SYMBOL(s5pv310_device_sysmmu);
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 3c05c58b5392..536b0b59fc83 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -25,6 +25,8 @@
25 25
26#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) S5P_IRQ(x+32)
27 27
28#define IRQ_MCT1 IRQ_SPI(35)
29
28#define IRQ_EINT0 IRQ_SPI(40) 30#define IRQ_EINT0 IRQ_SPI(40)
29#define IRQ_EINT1 IRQ_SPI(41) 31#define IRQ_EINT1 IRQ_SPI(41)
30#define IRQ_EINT2 IRQ_SPI(42) 32#define IRQ_EINT2 IRQ_SPI(42)
@@ -36,9 +38,8 @@
36#define IRQ_JPEG IRQ_SPI(48) 38#define IRQ_JPEG IRQ_SPI(48)
37#define IRQ_2D IRQ_SPI(49) 39#define IRQ_2D IRQ_SPI(49)
38#define IRQ_PCIE IRQ_SPI(50) 40#define IRQ_PCIE IRQ_SPI(50)
39#define IRQ_SYSTEM_TIMER IRQ_SPI(51) 41#define IRQ_MCT0 IRQ_SPI(51)
40#define IRQ_MFC IRQ_SPI(52) 42#define IRQ_MFC IRQ_SPI(52)
41#define IRQ_WDT IRQ_SPI(53)
42#define IRQ_AUDIO_SS IRQ_SPI(54) 43#define IRQ_AUDIO_SS IRQ_SPI(54)
43#define IRQ_AC97 IRQ_SPI(55) 44#define IRQ_AC97 IRQ_SPI(55)
44#define IRQ_SPDIF IRQ_SPI(56) 45#define IRQ_SPDIF IRQ_SPI(56)
@@ -54,6 +55,24 @@
54#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) 55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
55#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
56 57
58#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
59#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
60#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
61#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
62#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
63#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
64#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
65#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
66
67#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
68#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
69#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
70#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
71#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
72#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
73#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
74#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
75
57#define IRQ_PDMA0 COMBINER_IRQ(21, 0) 76#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
58#define IRQ_PDMA1 COMBINER_IRQ(21, 1) 77#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
59 78
@@ -86,8 +105,13 @@
86#define IRQ_HSMMC2 COMBINER_IRQ(29, 2) 105#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
87#define IRQ_HSMMC3 COMBINER_IRQ(29, 3) 106#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
88 107
108#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
109#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
110
89#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) 111#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
90 112
113#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
114
91#define IRQ_EINT4 COMBINER_IRQ(37, 0) 115#define IRQ_EINT4 COMBINER_IRQ(37, 0)
92#define IRQ_EINT5 COMBINER_IRQ(37, 1) 116#define IRQ_EINT5 COMBINER_IRQ(37, 1)
93#define IRQ_EINT6 COMBINER_IRQ(37, 2) 117#define IRQ_EINT6 COMBINER_IRQ(37, 2)
@@ -104,7 +128,11 @@
104 128
105#define IRQ_EINT16_31 COMBINER_IRQ(39, 0) 129#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
106 130
107#define MAX_COMBINER_NR 40 131#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
132
133#define IRQ_WDT COMBINER_IRQ(53, 0)
134
135#define MAX_COMBINER_NR 54
108 136
109#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 137#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
110 138
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 53994467605d..74d400625a23 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -39,11 +39,15 @@
39#define S5PV310_PA_SYSCON (0x10010000) 39#define S5PV310_PA_SYSCON (0x10010000)
40#define S5P_PA_SYSCON S5PV310_PA_SYSCON 40#define S5P_PA_SYSCON S5PV310_PA_SYSCON
41 41
42#define S5PV310_PA_PMU (0x10020000)
43
42#define S5PV310_PA_CMU (0x10030000) 44#define S5PV310_PA_CMU (0x10030000)
43 45
44#define S5PV310_PA_WATCHDOG (0x10060000) 46#define S5PV310_PA_WATCHDOG (0x10060000)
45#define S5PV310_PA_RTC (0x10070000) 47#define S5PV310_PA_RTC (0x10070000)
46 48
49#define S5PV310_PA_DMC0 (0x10400000)
50
47#define S5PV310_PA_COMBINER (0x10448000) 51#define S5PV310_PA_COMBINER (0x10448000)
48 52
49#define S5PV310_PA_COREPERI (0x10500000) 53#define S5PV310_PA_COREPERI (0x10500000)
@@ -61,9 +65,13 @@
61#define S5PV310_PA_GPIO2 (0x11000000) 65#define S5PV310_PA_GPIO2 (0x11000000)
62#define S5PV310_PA_GPIO3 (0x03860000) 66#define S5PV310_PA_GPIO3 (0x03860000)
63 67
68#define S5PV310_PA_MIPI_CSIS0 0x11880000
69#define S5PV310_PA_MIPI_CSIS1 0x11890000
70
64#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 71#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
65 72
66#define S5PV310_PA_SROMC (0x12570000) 73#define S5PV310_PA_SROMC (0x12570000)
74#define S5P_PA_SROMC S5PV310_PA_SROMC
67 75
68/* S/PDIF */ 76/* S/PDIF */
69#define S5PV310_PA_SPDIF 0xE1100000 77#define S5PV310_PA_SPDIF 0xE1100000
@@ -100,6 +108,25 @@
100#define S5PV310_PA_SDRAM (0x40000000) 108#define S5PV310_PA_SDRAM (0x40000000)
101#define S5P_PA_SDRAM S5PV310_PA_SDRAM 109#define S5P_PA_SDRAM S5PV310_PA_SDRAM
102 110
111#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
112#define S5PV310_PA_SYSMMU_SSS 0x10A50000
113#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
114#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
115#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
116#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
117#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
118#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
119#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
120#define S5PV310_PA_SYSMMU_PCIe 0x12620000
121#define S5PV310_PA_SYSMMU_G2D 0x12A20000
122#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
123#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
124#define S5PV310_PA_SYSMMU_TV 0x12E20000
125#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
126#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
127#define S5PV310_SYSMMU_TOTAL_IPNUM 16
128#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
129
103/* compatibiltiy defines. */ 130/* compatibiltiy defines. */
104#define S3C_PA_UART S5PV310_PA_UART 131#define S3C_PA_UART S5PV310_PA_UART
105#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) 132#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
@@ -116,5 +143,7 @@
116#define S3C_PA_IIC7 S5PV310_PA_IIC(7) 143#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
117#define S3C_PA_RTC S5PV310_PA_RTC 144#define S3C_PA_RTC S5PV310_PA_RTC
118#define S3C_PA_WDT S5PV310_PA_WATCHDOG 145#define S3C_PA_WDT S5PV310_PA_WATCHDOG
146#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
147#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
119 148
120#endif /* __ASM_ARCH_MAP_H */ 149#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index f1028cad9788..b5c4ada1cff5 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -19,6 +19,12 @@
19 19
20#define S5P_INFORM0 S5P_CLKREG(0x800) 20#define S5P_INFORM0 S5P_CLKREG(0x800)
21 21
22#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
23#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
24
25#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
26#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
27
22#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -58,6 +64,8 @@
58#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 64#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
59#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) 65#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
60 66
67#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
68
61#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) 69#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
62#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 70#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
63#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 71#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
@@ -66,8 +74,9 @@
66#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 74#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
67#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 75#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
68 76
69#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) 77#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
70#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) 78#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
79#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
71 80
72#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 81#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
73#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 82#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
@@ -80,10 +89,77 @@
80#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 89#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
81 90
82#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) 91#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
92#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
83#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) 93#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
94#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
84 95
85#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 96#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
86 97
98/* APLL_LOCK */
99#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
100
101/* APLL_CON0 */
102#define S5P_APLLCON0_ENABLE_SHIFT (31)
103#define S5P_APLLCON0_LOCKED_SHIFT (29)
104#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
105#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
106
107/* CLK_SRC_CPU */
108#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
109#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
110
111/* CLKDIV_CPU0 */
112#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
113#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
114#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
115#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
116#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
117#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
118#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
119#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
120#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
121#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
122#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
123#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
124#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
125#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
126
127/* CLKDIV_DMC0 */
128#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
129#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
130#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
131#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
132#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
133#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
134#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
135#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
136#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
137#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
138#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
139#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
140#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
141#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
142#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
143#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
144
145/* CLKDIV_TOP */
146#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
147#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
148#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
149#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
150#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
151#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
152#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
153#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
154#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
155#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
156
157/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
158#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
159#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
160#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
161#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
162
87/* Compatibility defines */ 163/* Compatibility defines */
88 164
89#define S5P_EPLL_CON S5P_EPLL_CON0 165#define S5P_EPLL_CON S5P_EPLL_CON0
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
new file mode 100644
index 000000000000..834227140eaa
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-mem.h
@@ -0,0 +1,23 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC and DMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MEM_H
14#define __ASM_ARCH_REGS_MEM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_DMC0_MEMCON_OFFSET 0x04
19
20#define S5P_DMC0_MEMTYPE_SHIFT 8
21#define S5P_DMC0_MEMTYPE_MASK 0xF
22
23#endif /* __ASM_ARCH_REGS_MEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
new file mode 100644
index 000000000000..fb333d0f6073
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - Power management unit definition
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_PMU_H
14#define __ASM_ARCH_REGS_PMU_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
25#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
26#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
27
28#define S5P_INT_LOCAL_PWR_EN 0x7
29
30#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
deleted file mode 100644
index 1898b3e10550..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-srom.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SROM_H
14#define __ASM_ARCH_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
21#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
22#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
23#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
24#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
25
26/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
27
28#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
29#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
30#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
31#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
32
33#define S5PV310_SROM_BW__CS_MASK 0xf
34
35#define S5PV310_SROM_BW__NCS0__SHIFT 0
36#define S5PV310_SROM_BW__NCS1__SHIFT 4
37#define S5PV310_SROM_BW__NCS2__SHIFT 8
38#define S5PV310_SROM_BW__NCS3__SHIFT 12
39
40/* applies to same to BCS0 - BCS3 */
41
42#define S5PV310_SROM_BCX__PMC__SHIFT 0
43#define S5PV310_SROM_BCX__TACP__SHIFT 4
44#define S5PV310_SROM_BCX__TCAH__SHIFT 8
45#define S5PV310_SROM_BCX__TCOH__SHIFT 12
46#define S5PV310_SROM_BCX__TACC__SHIFT 16
47#define S5PV310_SROM_BCX__TCOS__SHIFT 24
48#define S5PV310_SROM_BCX__TACS__SHIFT 28
49
50#endif /* __ASM_ARCH_REGS_SROM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
new file mode 100644
index 000000000000..0b28e81a16f7
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
@@ -0,0 +1,24 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - System MMU register
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SYSMMU_H
14#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
15
16#define S5P_MMU_CTRL 0x000
17#define S5P_MMU_CFG 0x004
18#define S5P_MMU_STATUS 0x008
19#define S5P_MMU_FLUSH 0x00C
20#define S5P_PT_BASE_ADDR 0x014
21#define S5P_INT_STATUS 0x018
22#define S5P_PAGE_FAULT_ADDR 0x024
23
24#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
new file mode 100644
index 000000000000..662fe85ff4d5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
@@ -0,0 +1,119 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Samsung sysmmu driver for S5PV310
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15
16enum s5pv310_sysmmu_ips {
17 SYSMMU_MDMA,
18 SYSMMU_SSS,
19 SYSMMU_FIMC0,
20 SYSMMU_FIMC1,
21 SYSMMU_FIMC2,
22 SYSMMU_FIMC3,
23 SYSMMU_JPEG,
24 SYSMMU_FIMD0,
25 SYSMMU_FIMD1,
26 SYSMMU_PCIe,
27 SYSMMU_G2D,
28 SYSMMU_ROTATOR,
29 SYSMMU_MDMA2,
30 SYSMMU_TV,
31 SYSMMU_MFC_L,
32 SYSMMU_MFC_R,
33};
34
35static char *sysmmu_ips_name[S5P_SYSMMU_TOTAL_IPNUM] = {
36 "SYSMMU_MDMA" ,
37 "SYSMMU_SSS" ,
38 "SYSMMU_FIMC0" ,
39 "SYSMMU_FIMC1" ,
40 "SYSMMU_FIMC2" ,
41 "SYSMMU_FIMC3" ,
42 "SYSMMU_JPEG" ,
43 "SYSMMU_FIMD0" ,
44 "SYSMMU_FIMD1" ,
45 "SYSMMU_PCIe" ,
46 "SYSMMU_G2D" ,
47 "SYSMMU_ROTATOR",
48 "SYSMMU_MDMA2" ,
49 "SYSMMU_TV" ,
50 "SYSMMU_MFC_L" ,
51 "SYSMMU_MFC_R" ,
52};
53
54typedef enum s5pv310_sysmmu_ips sysmmu_ips;
55
56struct sysmmu_tt_info {
57 unsigned long *pgd;
58 unsigned long pgd_paddr;
59 unsigned long *pte;
60};
61
62struct sysmmu_controller {
63 const char *name;
64
65 /* channels registers */
66 void __iomem *regs;
67
68 /* channel irq */
69 unsigned int irq;
70
71 sysmmu_ips ips;
72
73 /* Translation Table Info. */
74 struct sysmmu_tt_info *tt_info;
75
76 struct resource *mem;
77 struct device *dev;
78
79 /* SysMMU controller enable - true : enable */
80 bool enable;
81};
82
83/**
84 * s5p_sysmmu_enable() - enable system mmu of ip
85 * @ips: The ip connected system mmu.
86 *
87 * This function enable system mmu to transfer address
88 * from virtual address to physical address
89 */
90int s5p_sysmmu_enable(sysmmu_ips ips);
91
92/**
93 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
94 * @ips: The ip connected system mmu.
95 *
96 * This function disable system mmu to transfer address
97 * from virtual address to physical address
98 */
99int s5p_sysmmu_disable(sysmmu_ips ips);
100
101/**
102 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
103 * @ips: The ip connected system mmu.
104 * @pgd: The page table base address.
105 *
106 * This function set page table base address
107 * When system mmu transfer address from virtaul address to physical address,
108 * system mmu refer address information from page table
109 */
110int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
111
112/**
113 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
114 * @ips: The ip connected system mmu.
115 *
116 * This function flush all TLB entry in system mmu
117 */
118int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
119#endif /* __ASM_ARM_ARCH_SYSMMU_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index c3f88c3faf6c..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -24,29 +24,32 @@ static DEFINE_SPINLOCK(irq_controller_lock);
24 24
25struct combiner_chip_data { 25struct combiner_chip_data {
26 unsigned int irq_offset; 26 unsigned int irq_offset;
27 unsigned int irq_mask;
27 void __iomem *base; 28 void __iomem *base;
28}; 29};
29 30
30static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
31 32
32static inline void __iomem *combiner_base(unsigned int irq) 33static inline void __iomem *combiner_base(struct irq_data *data)
33{ 34{
34 struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); 35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
35 return combiner_data->base; 38 return combiner_data->base;
36} 39}
37 40
38static void combiner_mask_irq(unsigned int irq) 41static void combiner_mask_irq(struct irq_data *data)
39{ 42{
40 u32 mask = 1 << (irq % 32); 43 u32 mask = 1 << (data->irq % 32);
41 44
42 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); 45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
43} 46}
44 47
45static void combiner_unmask_irq(unsigned int irq) 48static void combiner_unmask_irq(struct irq_data *data)
46{ 49{
47 u32 mask = 1 << (irq % 32); 50 u32 mask = 1 << (data->irq % 32);
48 51
49 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); 52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
50} 53}
51 54
52static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -57,11 +60,12 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
57 unsigned long status; 60 unsigned long status;
58 61
59 /* primary controller ack'ing */ 62 /* primary controller ack'ing */
60 chip->ack(irq); 63 chip->irq_ack(&desc->irq_data);
61 64
62 spin_lock(&irq_controller_lock); 65 spin_lock(&irq_controller_lock);
63 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
64 spin_unlock(&irq_controller_lock); 67 spin_unlock(&irq_controller_lock);
68 status &= chip_data->irq_mask;
65 69
66 if (status == 0) 70 if (status == 0)
67 goto out; 71 goto out;
@@ -76,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
76 80
77 out: 81 out:
78 /* primary controller unmasking */ 82 /* primary controller unmasking */
79 chip->unmask(irq); 83 chip->irq_unmask(&desc->irq_data);
80} 84}
81 85
82static struct irq_chip combiner_chip = { 86static struct irq_chip combiner_chip = {
83 .name = "COMBINER", 87 .name = "COMBINER",
84 .mask = combiner_mask_irq, 88 .irq_mask = combiner_mask_irq,
85 .unmask = combiner_unmask_irq, 89 .irq_unmask = combiner_unmask_irq,
86}; 90};
87 91
88void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 92void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -104,10 +108,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
104 108
105 combiner_data[combiner_nr].base = base; 109 combiner_data[combiner_nr].base = base;
106 combiner_data[combiner_nr].irq_offset = irq_start; 110 combiner_data[combiner_nr].irq_offset = irq_start;
111 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
107 112
108 /* Disable all interrupts */ 113 /* Disable all interrupts */
109 114
110 __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); 115 __raw_writel(combiner_data[combiner_nr].irq_mask,
116 base + COMBINER_ENABLE_CLEAR);
111 117
112 /* Setup the Linux IRQ subsystem */ 118 /* Setup the Linux IRQ subsystem */
113 119
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
index 5877503e92c3..477bd9e97f0f 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
48 return ret; 48 return ret;
49} 49}
50 50
51static inline void s5pv310_irq_eint_mask(unsigned int irq) 51static inline void s5pv310_irq_eint_mask(struct irq_data *data)
52{ 52{
53 u32 mask; 53 u32 mask;
54 54
55 spin_lock(&eint_lock); 55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
57 mask |= eint_irq_to_bit(irq); 57 mask |= eint_irq_to_bit(data->irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 spin_unlock(&eint_lock); 59 spin_unlock(&eint_lock);
60} 60}
61 61
62static void s5pv310_irq_eint_unmask(unsigned int irq) 62static void s5pv310_irq_eint_unmask(struct irq_data *data)
63{ 63{
64 u32 mask; 64 u32 mask;
65 65
66 spin_lock(&eint_lock); 66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
68 mask &= ~(eint_irq_to_bit(irq)); 68 mask &= ~(eint_irq_to_bit(data->irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 spin_unlock(&eint_lock); 70 spin_unlock(&eint_lock);
71} 71}
72 72
73static inline void s5pv310_irq_eint_ack(unsigned int irq) 73static inline void s5pv310_irq_eint_ack(struct irq_data *data)
74{ 74{
75 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); 75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
76} 77}
77 78
78static void s5pv310_irq_eint_maskack(unsigned int irq) 79static void s5pv310_irq_eint_maskack(struct irq_data *data)
79{ 80{
80 s5pv310_irq_eint_mask(irq); 81 s5pv310_irq_eint_mask(data);
81 s5pv310_irq_eint_ack(irq); 82 s5pv310_irq_eint_ack(data);
82} 83}
83 84
84static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) 85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
85{ 86{
86 int offs = EINT_OFFSET(irq); 87 int offs = EINT_OFFSET(data->irq);
87 int shift; 88 int shift;
88 u32 ctrl, mask; 89 u32 ctrl, mask;
89 u32 newvalue = 0; 90 u32 newvalue = 0;
@@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
118 mask = 0x7 << shift; 119 mask = 0x7 << shift;
119 120
120 spin_lock(&eint_lock); 121 spin_lock(&eint_lock);
121 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); 122 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
122 ctrl &= ~mask; 123 ctrl &= ~mask;
123 ctrl |= newvalue << shift; 124 ctrl |= newvalue << shift;
124 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); 125 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 spin_unlock(&eint_lock); 126 spin_unlock(&eint_lock);
126 127
127 switch (offs) { 128 switch (offs) {
@@ -146,13 +147,13 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
146 147
147static struct irq_chip s5pv310_irq_eint = { 148static struct irq_chip s5pv310_irq_eint = {
148 .name = "s5pv310-eint", 149 .name = "s5pv310-eint",
149 .mask = s5pv310_irq_eint_mask, 150 .irq_mask = s5pv310_irq_eint_mask,
150 .unmask = s5pv310_irq_eint_unmask, 151 .irq_unmask = s5pv310_irq_eint_unmask,
151 .mask_ack = s5pv310_irq_eint_maskack, 152 .irq_mask_ack = s5pv310_irq_eint_maskack,
152 .ack = s5pv310_irq_eint_ack, 153 .irq_ack = s5pv310_irq_eint_ack,
153 .set_type = s5pv310_irq_eint_set_type, 154 .irq_set_type = s5pv310_irq_eint_set_type,
154#ifdef CONFIG_PM 155#ifdef CONFIG_PM
155 .set_wake = s3c_irqext_wake, 156 .irq_set_wake = s3c_irqext_wake,
156#endif 157#endif
157}; 158};
158 159
@@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = get_irq_data(irq);
193 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = get_irq_chip(irq);
194 195
195 chip->mask(irq); 196 chip->irq_mask(&desc->irq_data);
196 197
197 if (chip->ack) 198 if (chip->irq_ack)
198 chip->ack(irq); 199 chip->irq_ack(&desc->irq_data);
199 200
200 generic_handle_irq(*irq_data); 201 generic_handle_irq(*irq_data);
201 202
202 chip->unmask(irq); 203 chip->irq_unmask(&desc->irq_data);
203} 204}
204 205
205int __init s5pv310_init_irq_eint(void) 206int __init s5pv310_init_irq_eint(void)
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
index 2b8d4fc52d7c..2d49273c0a26 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -14,18 +14,21 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h>
17 18
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
22#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
23#include <plat/cpu.h> 25#include <plat/cpu.h>
24#include <plat/devs.h> 26#include <plat/devs.h>
25#include <plat/sdhci.h> 27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
26 30
27#include <mach/map.h> 31#include <mach/map.h>
28#include <mach/regs-srom.h>
29 32
30/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -139,14 +142,29 @@ static struct platform_device smdkc210_smsc911x = {
139 }, 142 },
140}; 143};
141 144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
142static struct platform_device *smdkc210_devices[] __initdata = { 149static struct platform_device *smdkc210_devices[] __initdata = {
143 &s3c_device_hsmmc0, 150 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1, 151 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2, 152 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3, 153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
147 &s3c_device_rtc, 155 &s3c_device_rtc,
148 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
149 &smdkc210_smsc911x, 166 &smdkc210_smsc911x,
167 &s5pv310_device_sysmmu,
150}; 168};
151 169
152static void __init smdkc210_smsc911x_init(void) 170static void __init smdkc210_smsc911x_init(void)
@@ -154,23 +172,22 @@ static void __init smdkc210_smsc911x_init(void)
154 u32 cs1; 172 u32 cs1;
155 173
156 /* configure nCS1 width to 16 bits */ 174 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) & 175 cs1 = __raw_readl(S5P_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK << 176 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
159 S5PV310_SROM_BW__NCS1__SHIFT); 177 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | 178 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | 179 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << 180 S5P_SROM_BW__NCS1__SHIFT;
163 S5PV310_SROM_BW__NCS1__SHIFT; 181 __raw_writel(cs1, S5P_SROM_BW);
164 __raw_writel(cs1, S5PV310_SROM_BW);
165 182
166 /* set timing for nCS1 suitable for ethernet chip */ 183 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | 184 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | 185 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | 186 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | 187 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | 188 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | 189 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); 190 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
174} 191}
175 192
176static void __init smdkc210_map_io(void) 193static void __init smdkc210_map_io(void)
@@ -182,6 +199,9 @@ static void __init smdkc210_map_io(void)
182 199
183static void __init smdkc210_machine_init(void) 200static void __init smdkc210_machine_init(void)
184{ 201{
202 s3c_i2c1_set_platdata(NULL);
203 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
204
185 smdkc210_smsc911x_init(); 205 smdkc210_smsc911x_init();
186 206
187 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata); 207 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 35826d66632c..28680cf9a72c 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -14,18 +14,21 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/smsc911x.h> 15#include <linux/smsc911x.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h>
17 18
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20 21
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h>
22#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
23#include <plat/cpu.h> 25#include <plat/cpu.h>
24#include <plat/devs.h> 26#include <plat/devs.h>
25#include <plat/sdhci.h> 27#include <plat/sdhci.h>
28#include <plat/iic.h>
29#include <plat/pd.h>
26 30
27#include <mach/map.h> 31#include <mach/map.h>
28#include <mach/regs-srom.h>
29 32
30/* Following are default values for UCON, ULCON and UFCON UART registers */ 33/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 34#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -139,14 +142,29 @@ static struct platform_device smdkv310_smsc911x = {
139 }, 142 },
140}; 143};
141 144
145static struct i2c_board_info i2c_devs1[] __initdata = {
146 {I2C_BOARD_INFO("wm8994", 0x1a),},
147};
148
142static struct platform_device *smdkv310_devices[] __initdata = { 149static struct platform_device *smdkv310_devices[] __initdata = {
143 &s3c_device_hsmmc0, 150 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1, 151 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2, 152 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3, 153 &s3c_device_hsmmc3,
154 &s3c_device_i2c1,
147 &s3c_device_rtc, 155 &s3c_device_rtc,
148 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97,
158 &s5pv310_device_i2s0,
159 &s5pv310_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS],
149 &smdkv310_smsc911x, 166 &smdkv310_smsc911x,
167 &s5pv310_device_sysmmu,
150}; 168};
151 169
152static void __init smdkv310_smsc911x_init(void) 170static void __init smdkv310_smsc911x_init(void)
@@ -154,23 +172,22 @@ static void __init smdkv310_smsc911x_init(void)
154 u32 cs1; 172 u32 cs1;
155 173
156 /* configure nCS1 width to 16 bits */ 174 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) & 175 cs1 = __raw_readl(S5P_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK << 176 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
159 S5PV310_SROM_BW__NCS1__SHIFT); 177 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | 178 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | 179 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << 180 S5P_SROM_BW__NCS1__SHIFT;
163 S5PV310_SROM_BW__NCS1__SHIFT; 181 __raw_writel(cs1, S5P_SROM_BW);
164 __raw_writel(cs1, S5PV310_SROM_BW);
165 182
166 /* set timing for nCS1 suitable for ethernet chip */ 183 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | 184 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | 185 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | 186 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | 187 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | 188 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | 189 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); 190 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
174} 191}
175 192
176static void __init smdkv310_map_io(void) 193static void __init smdkv310_map_io(void)
@@ -182,6 +199,9 @@ static void __init smdkv310_map_io(void)
182 199
183static void __init smdkv310_machine_init(void) 200static void __init smdkv310_machine_init(void)
184{ 201{
202 s3c_i2c1_set_platdata(NULL);
203 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
204
185 smdkv310_smsc911x_init(); 205 smdkv310_smsc911x_init();
186 206
187 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); 207 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index 16d8fc00cafd..36bc3cf825e3 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -13,6 +13,9 @@
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/gpio_keys.h> 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
16 19
17#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
18#include <asm/mach-types.h> 21#include <asm/mach-types.h>
@@ -21,6 +24,7 @@
21#include <plat/s5pv310.h> 24#include <plat/s5pv310.h>
22#include <plat/cpu.h> 25#include <plat/cpu.h>
23#include <plat/devs.h> 26#include <plat/devs.h>
27#include <plat/sdhci.h>
24 28
25#include <mach/map.h> 29#include <mach/map.h>
26 30
@@ -116,6 +120,73 @@ static struct platform_device universal_gpio_keys = {
116 }, 120 },
117}; 121};
118 122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = S5PV310_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
119/* I2C0 */ 190/* I2C0 */
120static struct i2c_board_info i2c0_devs[] __initdata = { 191static struct i2c_board_info i2c0_devs[] __initdata = {
121 /* Camera, To be updated */ 192 /* Camera, To be updated */
@@ -127,6 +198,13 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
127}; 198};
128 199
129static struct platform_device *universal_devices[] __initdata = { 200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
130 &universal_gpio_keys, 208 &universal_gpio_keys,
131 &s5p_device_onenand, 209 &s5p_device_onenand,
132}; 210};
@@ -140,6 +218,8 @@ static void __init universal_map_io(void)
140 218
141static void __init universal_machine_init(void) 219static void __init universal_machine_init(void)
142{ 220{
221 universal_sdhci_init();
222
143 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
144 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); 224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
145 225
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 01:24:23 -0500