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Diffstat (limited to 'arch/arm/mach-s5pv310/irq-combiner.c')
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c32
1 files changed, 19 insertions, 13 deletions
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index c3f88c3faf6c..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -24,29 +24,32 @@ static DEFINE_SPINLOCK(irq_controller_lock);
24 24
25struct combiner_chip_data { 25struct combiner_chip_data {
26 unsigned int irq_offset; 26 unsigned int irq_offset;
27 unsigned int irq_mask;
27 void __iomem *base; 28 void __iomem *base;
28}; 29};
29 30
30static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
31 32
32static inline void __iomem *combiner_base(unsigned int irq) 33static inline void __iomem *combiner_base(struct irq_data *data)
33{ 34{
34 struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); 35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
35 return combiner_data->base; 38 return combiner_data->base;
36} 39}
37 40
38static void combiner_mask_irq(unsigned int irq) 41static void combiner_mask_irq(struct irq_data *data)
39{ 42{
40 u32 mask = 1 << (irq % 32); 43 u32 mask = 1 << (data->irq % 32);
41 44
42 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); 45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
43} 46}
44 47
45static void combiner_unmask_irq(unsigned int irq) 48static void combiner_unmask_irq(struct irq_data *data)
46{ 49{
47 u32 mask = 1 << (irq % 32); 50 u32 mask = 1 << (data->irq % 32);
48 51
49 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); 52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
50} 53}
51 54
52static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -57,11 +60,12 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
57 unsigned long status; 60 unsigned long status;
58 61
59 /* primary controller ack'ing */ 62 /* primary controller ack'ing */
60 chip->ack(irq); 63 chip->irq_ack(&desc->irq_data);
61 64
62 spin_lock(&irq_controller_lock); 65 spin_lock(&irq_controller_lock);
63 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
64 spin_unlock(&irq_controller_lock); 67 spin_unlock(&irq_controller_lock);
68 status &= chip_data->irq_mask;
65 69
66 if (status == 0) 70 if (status == 0)
67 goto out; 71 goto out;
@@ -76,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
76 80
77 out: 81 out:
78 /* primary controller unmasking */ 82 /* primary controller unmasking */
79 chip->unmask(irq); 83 chip->irq_unmask(&desc->irq_data);
80} 84}
81 85
82static struct irq_chip combiner_chip = { 86static struct irq_chip combiner_chip = {
83 .name = "COMBINER", 87 .name = "COMBINER",
84 .mask = combiner_mask_irq, 88 .irq_mask = combiner_mask_irq,
85 .unmask = combiner_unmask_irq, 89 .irq_unmask = combiner_unmask_irq,
86}; 90};
87 91
88void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 92void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -104,10 +108,12 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
104 108
105 combiner_data[combiner_nr].base = base; 109 combiner_data[combiner_nr].base = base;
106 combiner_data[combiner_nr].irq_offset = irq_start; 110 combiner_data[combiner_nr].irq_offset = irq_start;
111 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
107 112
108 /* Disable all interrupts */ 113 /* Disable all interrupts */
109 114
110 __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); 115 __raw_writel(combiner_data[combiner_nr].irq_mask,
116 base + COMBINER_ENABLE_CLEAR);
111 117
112 /* Setup the Linux IRQ subsystem */ 118 /* Setup the Linux IRQ subsystem */
113 119