aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv310/clock.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pv310/clock.c')
-rw-r--r--arch/arm/mach-s5pv310/clock.c635
1 files changed, 568 insertions, 67 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 26a0f03df8ea..58c9d33f36fe 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,16 +30,92 @@ static struct clk clk_sclk_hdmi27m = {
30 .rate = 27000000, 30 .rate = 27000000,
31}; 31};
32 32
33static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
35 .id = -1,
36};
37
38static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
40 .id = -1,
41 .rate = 27000000,
42};
43
44static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
46 .id = -1,
47};
48
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52}
53
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57}
58
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62}
63
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67}
68
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72}
73
33static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34{ 75{
35 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36} 77}
37 78
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82}
83
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87}
88
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
90{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92}
93
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97}
98
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102}
103
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107}
108
38static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39{ 110{
40 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41} 112}
42 113
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117}
118
43/* Core list of CMU_CPU side */ 119/* Core list of CMU_CPU side */
44 120
45static struct clksrc_clk clk_mout_apll = { 121static struct clksrc_clk clk_mout_apll = {
@@ -79,7 +155,7 @@ static struct clksrc_clk clk_mout_mpll = {
79}; 155};
80 156
81static struct clk *clkset_moutcore_list[] = { 157static struct clk *clkset_moutcore_list[] = {
82 [0] = &clk_sclk_apll.clk, 158 [0] = &clk_mout_apll.clk,
83 [1] = &clk_mout_mpll.clk, 159 [1] = &clk_mout_mpll.clk,
84}; 160};
85 161
@@ -150,24 +226,6 @@ static struct clksrc_clk clk_periphclk = {
150 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
151}; 227};
152 228
153static struct clksrc_clk clk_atclk = {
154 .clk = {
155 .name = "atclk",
156 .id = -1,
157 .parent = &clk_moutcore.clk,
158 },
159 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
160};
161
162static struct clksrc_clk clk_pclk_dbg = {
163 .clk = {
164 .name = "pclk_dbg",
165 .id = -1,
166 .parent = &clk_atclk.clk,
167 },
168 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
169};
170
171/* Core list of CMU_CORE side */ 229/* Core list of CMU_CORE side */
172 230
173static struct clk *clkset_corebus_list[] = { 231static struct clk *clkset_corebus_list[] = {
@@ -241,7 +299,7 @@ static struct clk *clkset_aclk_top_list[] = {
241 [1] = &clk_sclk_apll.clk, 299 [1] = &clk_sclk_apll.clk,
242}; 300};
243 301
244static struct clksrc_sources clkset_aclk_200 = { 302static struct clksrc_sources clkset_aclk = {
245 .sources = clkset_aclk_top_list, 303 .sources = clkset_aclk_top_list,
246 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
247}; 305};
@@ -251,52 +309,37 @@ static struct clksrc_clk clk_aclk_200 = {
251 .name = "aclk_200", 309 .name = "aclk_200",
252 .id = -1, 310 .id = -1,
253 }, 311 },
254 .sources = &clkset_aclk_200, 312 .sources = &clkset_aclk,
255 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
256 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, 314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
257}; 315};
258 316
259static struct clksrc_sources clkset_aclk_100 = {
260 .sources = clkset_aclk_top_list,
261 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
262};
263
264static struct clksrc_clk clk_aclk_100 = { 317static struct clksrc_clk clk_aclk_100 = {
265 .clk = { 318 .clk = {
266 .name = "aclk_100", 319 .name = "aclk_100",
267 .id = -1, 320 .id = -1,
268 }, 321 },
269 .sources = &clkset_aclk_100, 322 .sources = &clkset_aclk,
270 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
271 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, 324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
272}; 325};
273 326
274static struct clksrc_sources clkset_aclk_160 = {
275 .sources = clkset_aclk_top_list,
276 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
277};
278
279static struct clksrc_clk clk_aclk_160 = { 327static struct clksrc_clk clk_aclk_160 = {
280 .clk = { 328 .clk = {
281 .name = "aclk_160", 329 .name = "aclk_160",
282 .id = -1, 330 .id = -1,
283 }, 331 },
284 .sources = &clkset_aclk_160, 332 .sources = &clkset_aclk,
285 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
286 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
287}; 335};
288 336
289static struct clksrc_sources clkset_aclk_133 = {
290 .sources = clkset_aclk_top_list,
291 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
292};
293
294static struct clksrc_clk clk_aclk_133 = { 337static struct clksrc_clk clk_aclk_133 = {
295 .clk = { 338 .clk = {
296 .name = "aclk_133", 339 .name = "aclk_133",
297 .id = -1, 340 .id = -1,
298 }, 341 },
299 .sources = &clkset_aclk_133, 342 .sources = &clkset_aclk,
300 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
301 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, 344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
302}; 345};
@@ -315,6 +358,8 @@ static struct clksrc_clk clk_vpllsrc = {
315 .clk = { 358 .clk = {
316 .name = "vpll_src", 359 .name = "vpll_src",
317 .id = -1, 360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0),
318 }, 363 },
319 .sources = &clkset_vpllsrc, 364 .sources = &clkset_vpllsrc,
320 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, 365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
@@ -346,7 +391,175 @@ static struct clk init_clocks_disable[] = {
346 .parent = &clk_aclk_100.clk, 391 .parent = &clk_aclk_100.clk,
347 .enable = s5pv310_clk_ip_peril_ctrl, 392 .enable = s5pv310_clk_ip_peril_ctrl,
348 .ctrlbit = (1<<24), 393 .ctrlbit = (1<<24),
349 } 394 }, {
395 .name = "csis",
396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "csis",
401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5),
404 }, {
405 .name = "fimc",
406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0),
409 }, {
410 .name = "fimc",
411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1),
414 }, {
415 .name = "fimc",
416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "fimc",
421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3),
424 }, {
425 .name = "fimd",
426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0),
429 }, {
430 .name = "fimd",
431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0),
434 }, {
435 .name = "hsmmc",
436 .id = 0,
437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5),
440 }, {
441 .name = "hsmmc",
442 .id = 1,
443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6),
446 }, {
447 .name = "hsmmc",
448 .id = 2,
449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7),
452 }, {
453 .name = "hsmmc",
454 .id = 3,
455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8),
458 }, {
459 .name = "hsmmc",
460 .id = 4,
461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9),
464 }, {
465 .name = "sata",
466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
469 }, {
470 .name = "adc",
471 .id = -1,
472 .enable = s5pv310_clk_ip_peril_ctrl,
473 .ctrlbit = (1 << 15),
474 }, {
475 .name = "rtc",
476 .id = -1,
477 .enable = s5pv310_clk_ip_perir_ctrl,
478 .ctrlbit = (1 << 15),
479 }, {
480 .name = "watchdog",
481 .id = -1,
482 .enable = s5pv310_clk_ip_perir_ctrl,
483 .ctrlbit = (1 << 14),
484 }, {
485 .name = "usbhost",
486 .id = -1,
487 .enable = s5pv310_clk_ip_fsys_ctrl ,
488 .ctrlbit = (1 << 12),
489 }, {
490 .name = "otg",
491 .id = -1,
492 .enable = s5pv310_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 13),
494 }, {
495 .name = "spi",
496 .id = 0,
497 .enable = s5pv310_clk_ip_peril_ctrl,
498 .ctrlbit = (1 << 16),
499 }, {
500 .name = "spi",
501 .id = 1,
502 .enable = s5pv310_clk_ip_peril_ctrl,
503 .ctrlbit = (1 << 17),
504 }, {
505 .name = "spi",
506 .id = 2,
507 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 18),
509 }, {
510 .name = "fimg2d",
511 .id = -1,
512 .enable = s5pv310_clk_ip_image_ctrl,
513 .ctrlbit = (1 << 0),
514 }, {
515 .name = "i2c",
516 .id = 0,
517 .parent = &clk_aclk_100.clk,
518 .enable = s5pv310_clk_ip_peril_ctrl,
519 .ctrlbit = (1 << 6),
520 }, {
521 .name = "i2c",
522 .id = 1,
523 .parent = &clk_aclk_100.clk,
524 .enable = s5pv310_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 7),
526 }, {
527 .name = "i2c",
528 .id = 2,
529 .parent = &clk_aclk_100.clk,
530 .enable = s5pv310_clk_ip_peril_ctrl,
531 .ctrlbit = (1 << 8),
532 }, {
533 .name = "i2c",
534 .id = 3,
535 .parent = &clk_aclk_100.clk,
536 .enable = s5pv310_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 9),
538 }, {
539 .name = "i2c",
540 .id = 4,
541 .parent = &clk_aclk_100.clk,
542 .enable = s5pv310_clk_ip_peril_ctrl,
543 .ctrlbit = (1 << 10),
544 }, {
545 .name = "i2c",
546 .id = 5,
547 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 11),
550 }, {
551 .name = "i2c",
552 .id = 6,
553 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 12),
556 }, {
557 .name = "i2c",
558 .id = 7,
559 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 13),
562 },
350}; 563};
351 564
352static struct clk init_clocks[] = { 565static struct clk init_clocks[] = {
@@ -387,6 +600,9 @@ static struct clk *clkset_group_list[] = {
387 [0] = &clk_ext_xtal_mux, 600 [0] = &clk_ext_xtal_mux,
388 [1] = &clk_xusbxti, 601 [1] = &clk_xusbxti,
389 [2] = &clk_sclk_hdmi27m, 602 [2] = &clk_sclk_hdmi27m,
603 [3] = &clk_sclk_usbphy0,
604 [4] = &clk_sclk_usbphy1,
605 [5] = &clk_sclk_hdmiphy,
390 [6] = &clk_mout_mpll.clk, 606 [6] = &clk_mout_mpll.clk,
391 [7] = &clk_mout_epll.clk, 607 [7] = &clk_mout_epll.clk,
392 [8] = &clk_sclk_vpll.clk, 608 [8] = &clk_sclk_vpll.clk,
@@ -397,6 +613,104 @@ static struct clksrc_sources clkset_group = {
397 .nr_sources = ARRAY_SIZE(clkset_group_list), 613 .nr_sources = ARRAY_SIZE(clkset_group_list),
398}; 614};
399 615
616static struct clk *clkset_mout_g2d0_list[] = {
617 [0] = &clk_mout_mpll.clk,
618 [1] = &clk_sclk_apll.clk,
619};
620
621static struct clksrc_sources clkset_mout_g2d0 = {
622 .sources = clkset_mout_g2d0_list,
623 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
624};
625
626static struct clksrc_clk clk_mout_g2d0 = {
627 .clk = {
628 .name = "mout_g2d0",
629 .id = -1,
630 },
631 .sources = &clkset_mout_g2d0,
632 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
633};
634
635static struct clk *clkset_mout_g2d1_list[] = {
636 [0] = &clk_mout_epll.clk,
637 [1] = &clk_sclk_vpll.clk,
638};
639
640static struct clksrc_sources clkset_mout_g2d1 = {
641 .sources = clkset_mout_g2d1_list,
642 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
643};
644
645static struct clksrc_clk clk_mout_g2d1 = {
646 .clk = {
647 .name = "mout_g2d1",
648 .id = -1,
649 },
650 .sources = &clkset_mout_g2d1,
651 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
652};
653
654static struct clk *clkset_mout_g2d_list[] = {
655 [0] = &clk_mout_g2d0.clk,
656 [1] = &clk_mout_g2d1.clk,
657};
658
659static struct clksrc_sources clkset_mout_g2d = {
660 .sources = clkset_mout_g2d_list,
661 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
662};
663
664static struct clksrc_clk clk_dout_mmc0 = {
665 .clk = {
666 .name = "dout_mmc0",
667 .id = -1,
668 },
669 .sources = &clkset_group,
670 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
671 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
672};
673
674static struct clksrc_clk clk_dout_mmc1 = {
675 .clk = {
676 .name = "dout_mmc1",
677 .id = -1,
678 },
679 .sources = &clkset_group,
680 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
681 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
682};
683
684static struct clksrc_clk clk_dout_mmc2 = {
685 .clk = {
686 .name = "dout_mmc2",
687 .id = -1,
688 },
689 .sources = &clkset_group,
690 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
691 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
692};
693
694static struct clksrc_clk clk_dout_mmc3 = {
695 .clk = {
696 .name = "dout_mmc3",
697 .id = -1,
698 },
699 .sources = &clkset_group,
700 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
701 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
702};
703
704static struct clksrc_clk clk_dout_mmc4 = {
705 .clk = {
706 .name = "dout_mmc4",
707 .id = -1,
708 },
709 .sources = &clkset_group,
710 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
711 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
712};
713
400static struct clksrc_clk clksrcs[] = { 714static struct clksrc_clk clksrcs[] = {
401 { 715 {
402 .clk = { 716 .clk = {
@@ -448,7 +762,200 @@ static struct clksrc_clk clksrcs[] = {
448 .sources = &clkset_group, 762 .sources = &clkset_group,
449 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, 763 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
450 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, 764 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
451 }, 765 }, {
766 .clk = {
767 .name = "sclk_csis",
768 .id = 0,
769 .enable = s5pv310_clksrc_mask_cam_ctrl,
770 .ctrlbit = (1 << 24),
771 },
772 .sources = &clkset_group,
773 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
774 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_csis",
778 .id = 1,
779 .enable = s5pv310_clksrc_mask_cam_ctrl,
780 .ctrlbit = (1 << 28),
781 },
782 .sources = &clkset_group,
783 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
784 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
785 }, {
786 .clk = {
787 .name = "sclk_cam",
788 .id = 0,
789 .enable = s5pv310_clksrc_mask_cam_ctrl,
790 .ctrlbit = (1 << 16),
791 },
792 .sources = &clkset_group,
793 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
794 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
795 }, {
796 .clk = {
797 .name = "sclk_cam",
798 .id = 1,
799 .enable = s5pv310_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 20),
801 },
802 .sources = &clkset_group,
803 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
804 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
805 }, {
806 .clk = {
807 .name = "sclk_fimc",
808 .id = 0,
809 .enable = s5pv310_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 0),
811 },
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
815 }, {
816 .clk = {
817 .name = "sclk_fimc",
818 .id = 1,
819 .enable = s5pv310_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 4),
821 },
822 .sources = &clkset_group,
823 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
824 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
825 }, {
826 .clk = {
827 .name = "sclk_fimc",
828 .id = 2,
829 .enable = s5pv310_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 8),
831 },
832 .sources = &clkset_group,
833 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
834 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
835 }, {
836 .clk = {
837 .name = "sclk_fimc",
838 .id = 3,
839 .enable = s5pv310_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 12),
841 },
842 .sources = &clkset_group,
843 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
844 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
845 }, {
846 .clk = {
847 .name = "sclk_fimd",
848 .id = 0,
849 .enable = s5pv310_clksrc_mask_lcd0_ctrl,
850 .ctrlbit = (1 << 0),
851 },
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
855 }, {
856 .clk = {
857 .name = "sclk_fimd",
858 .id = 1,
859 .enable = s5pv310_clksrc_mask_lcd1_ctrl,
860 .ctrlbit = (1 << 0),
861 },
862 .sources = &clkset_group,
863 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
864 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
865 }, {
866 .clk = {
867 .name = "sclk_sata",
868 .id = -1,
869 .enable = s5pv310_clksrc_mask_fsys_ctrl,
870 .ctrlbit = (1 << 24),
871 },
872 .sources = &clkset_mout_corebus,
873 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
874 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
875 }, {
876 .clk = {
877 .name = "sclk_spi",
878 .id = 0,
879 .enable = s5pv310_clksrc_mask_peril1_ctrl,
880 .ctrlbit = (1 << 16),
881 },
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
885 }, {
886 .clk = {
887 .name = "sclk_spi",
888 .id = 1,
889 .enable = s5pv310_clksrc_mask_peril1_ctrl,
890 .ctrlbit = (1 << 20),
891 },
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
895 }, {
896 .clk = {
897 .name = "sclk_spi",
898 .id = 2,
899 .enable = s5pv310_clksrc_mask_peril1_ctrl,
900 .ctrlbit = (1 << 24),
901 },
902 .sources = &clkset_group,
903 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
904 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
905 }, {
906 .clk = {
907 .name = "sclk_fimg2d",
908 .id = -1,
909 },
910 .sources = &clkset_mout_g2d,
911 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
912 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
913 }, {
914 .clk = {
915 .name = "sclk_mmc",
916 .id = 0,
917 .parent = &clk_dout_mmc0.clk,
918 .enable = s5pv310_clksrc_mask_fsys_ctrl,
919 .ctrlbit = (1 << 0),
920 },
921 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
922 }, {
923 .clk = {
924 .name = "sclk_mmc",
925 .id = 1,
926 .parent = &clk_dout_mmc1.clk,
927 .enable = s5pv310_clksrc_mask_fsys_ctrl,
928 .ctrlbit = (1 << 4),
929 },
930 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
931 }, {
932 .clk = {
933 .name = "sclk_mmc",
934 .id = 2,
935 .parent = &clk_dout_mmc2.clk,
936 .enable = s5pv310_clksrc_mask_fsys_ctrl,
937 .ctrlbit = (1 << 8),
938 },
939 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
940 }, {
941 .clk = {
942 .name = "sclk_mmc",
943 .id = 3,
944 .parent = &clk_dout_mmc3.clk,
945 .enable = s5pv310_clksrc_mask_fsys_ctrl,
946 .ctrlbit = (1 << 12),
947 },
948 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
949 }, {
950 .clk = {
951 .name = "sclk_mmc",
952 .id = 4,
953 .parent = &clk_dout_mmc4.clk,
954 .enable = s5pv310_clksrc_mask_fsys_ctrl,
955 .ctrlbit = (1 << 16),
956 },
957 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
958 }
452}; 959};
453 960
454/* Clock initialization code */ 961/* Clock initialization code */
@@ -464,8 +971,6 @@ static struct clksrc_clk *sysclks[] = {
464 &clk_aclk_cores, 971 &clk_aclk_cores,
465 &clk_aclk_corem1, 972 &clk_aclk_corem1,
466 &clk_periphclk, 973 &clk_periphclk,
467 &clk_atclk,
468 &clk_pclk_dbg,
469 &clk_mout_corebus, 974 &clk_mout_corebus,
470 &clk_sclk_dmc, 975 &clk_sclk_dmc,
471 &clk_aclk_cored, 976 &clk_aclk_cored,
@@ -478,6 +983,11 @@ static struct clksrc_clk *sysclks[] = {
478 &clk_aclk_100, 983 &clk_aclk_100,
479 &clk_aclk_160, 984 &clk_aclk_160,
480 &clk_aclk_133, 985 &clk_aclk_133,
986 &clk_dout_mmc0,
987 &clk_dout_mmc1,
988 &clk_dout_mmc2,
989 &clk_dout_mmc3,
990 &clk_dout_mmc4,
481}; 991};
482 992
483void __init_or_cpufreq s5pv310_setup_clocks(void) 993void __init_or_cpufreq s5pv310_setup_clocks(void)
@@ -490,15 +1000,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
490 unsigned long vpllsrc; 1000 unsigned long vpllsrc;
491 unsigned long xtal; 1001 unsigned long xtal;
492 unsigned long armclk; 1002 unsigned long armclk;
493 unsigned long aclk_corem0;
494 unsigned long aclk_cores;
495 unsigned long aclk_corem1;
496 unsigned long periphclk;
497 unsigned long sclk_dmc; 1003 unsigned long sclk_dmc;
498 unsigned long aclk_cored; 1004 unsigned long aclk_200;
499 unsigned long aclk_corep; 1005 unsigned long aclk_100;
500 unsigned long aclk_acp; 1006 unsigned long aclk_160;
501 unsigned long pclk_acp; 1007 unsigned long aclk_133;
502 unsigned int ptr; 1008 unsigned int ptr;
503 1009
504 printk(KERN_DEBUG "%s: registering clocks\n", __func__); 1010 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -529,26 +1035,21 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
529 apll, mpll, epll, vpll); 1035 apll, mpll, epll, vpll);
530 1036
531 armclk = clk_get_rate(&clk_armclk.clk); 1037 armclk = clk_get_rate(&clk_armclk.clk);
532 aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
533 aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
534 aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
535 periphclk = clk_get_rate(&clk_periphclk.clk);
536 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); 1038 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
537 aclk_cored = clk_get_rate(&clk_aclk_cored.clk); 1039
538 aclk_corep = clk_get_rate(&clk_aclk_corep.clk); 1040 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
539 aclk_acp = clk_get_rate(&clk_aclk_acp.clk); 1041 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
540 pclk_acp = clk_get_rate(&clk_pclk_acp.clk); 1042 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
541 1043 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
542 printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n" 1044
543 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n" 1045 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
544 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld", 1046 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
545 armclk, aclk_corem0, aclk_cores, aclk_corem1, 1047 armclk, sclk_dmc, aclk_200,
546 periphclk, sclk_dmc, aclk_cored, aclk_corep, 1048 aclk_100, aclk_160, aclk_133);
547 aclk_acp, pclk_acp);
548 1049
549 clk_f.rate = armclk; 1050 clk_f.rate = armclk;
550 clk_h.rate = sclk_dmc; 1051 clk_h.rate = sclk_dmc;
551 clk_p.rate = periphclk; 1052 clk_p.rate = aclk_100;
552 1053
553 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 1054 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
554 s3c_set_clksrc(&clksrcs[ptr], true); 1055 s3c_set_clksrc(&clksrcs[ptr], true);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 06:52:04 -0500