aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv210
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/clock.c37
-rw-r--r--arch/arm/mach-s5pv210/cpufreq.c485
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-fb.h21
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c1
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c56
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c1
-rw-r--r--arch/arm/mach-s5pv210/sleep.S21
11 files changed, 18 insertions, 610 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index a06acce7b731..69dd87cd8e22 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -135,6 +135,7 @@ config MACH_SMDKV210
135 select S3C_DEV_RTC 135 select S3C_DEV_RTC
136 select S3C_DEV_WDT 136 select S3C_DEV_WDT
137 select SAMSUNG_DEV_ADC 137 select SAMSUNG_DEV_ADC
138 select SAMSUNG_DEV_BACKLIGHT
138 select SAMSUNG_DEV_IDE 139 select SAMSUNG_DEV_IDE
139 select SAMSUNG_DEV_KEYPAD 140 select SAMSUNG_DEV_KEYPAD
140 select SAMSUNG_DEV_PWM 141 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 50907aca006c..599a3c0e8f6c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -15,7 +15,6 @@ obj- :=
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o 16obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o 17obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_FREQ) += cpufreq.o
19 18
20# machine support 19# machine support
21 20
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 1404a4c43770..52a8e607bcc2 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -692,47 +692,12 @@ static struct clksrc_sources clkset_sclk_spdif = {
692 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), 692 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
693}; 693};
694 694
695static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
696{
697 struct clk *pclk;
698 int ret;
699
700 pclk = clk_get_parent(clk);
701 if (IS_ERR(pclk))
702 return -EINVAL;
703
704 ret = pclk->ops->set_rate(pclk, rate);
705 clk_put(pclk);
706
707 return ret;
708}
709
710static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
711{
712 struct clk *pclk;
713 int rate;
714
715 pclk = clk_get_parent(clk);
716 if (IS_ERR(pclk))
717 return -EINVAL;
718
719 rate = pclk->ops->get_rate(clk);
720 clk_put(pclk);
721
722 return rate;
723}
724
725static struct clk_ops s5pv210_sclk_spdif_ops = {
726 .set_rate = s5pv210_spdif_set_rate,
727 .get_rate = s5pv210_spdif_get_rate,
728};
729
730static struct clksrc_clk clk_sclk_spdif = { 695static struct clksrc_clk clk_sclk_spdif = {
731 .clk = { 696 .clk = {
732 .name = "sclk_spdif", 697 .name = "sclk_spdif",
733 .enable = s5pv210_clk_mask0_ctrl, 698 .enable = s5pv210_clk_mask0_ctrl,
734 .ctrlbit = (1 << 27), 699 .ctrlbit = (1 << 27),
735 .ops = &s5pv210_sclk_spdif_ops, 700 .ops = &s5p_sclk_spdif_ops,
736 }, 701 },
737 .sources = &clkset_sclk_spdif, 702 .sources = &clkset_sclk_spdif,
738 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, 703 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
deleted file mode 100644
index 153af8b359ec..000000000000
--- a/arch/arm/mach-s5pv210/cpufreq.c
+++ /dev/null
@@ -1,485 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/cpufreq.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * CPU frequency scaling for S5PC110/S5PV210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/cpufreq.h>
20
21#include <mach/map.h>
22#include <mach/regs-clock.h>
23
24static struct clk *cpu_clk;
25static struct clk *dmc0_clk;
26static struct clk *dmc1_clk;
27static struct cpufreq_freqs freqs;
28
29/* APLL M,P,S values for 1G/800Mhz */
30#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
31#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
32
33/*
34 * DRAM configurations to calculate refresh counter for changing
35 * frequency of memory.
36 */
37struct dram_conf {
38 unsigned long freq; /* HZ */
39 unsigned long refresh; /* DRAM refresh counter * 1000 */
40};
41
42/* DRAM configuration (DMC0 and DMC1) */
43static struct dram_conf s5pv210_dram_conf[2];
44
45enum perf_level {
46 L0, L1, L2, L3, L4,
47};
48
49enum s5pv210_mem_type {
50 LPDDR = 0x1,
51 LPDDR2 = 0x2,
52 DDR2 = 0x4,
53};
54
55enum s5pv210_dmc_port {
56 DMC0 = 0,
57 DMC1,
58};
59
60static struct cpufreq_frequency_table s5pv210_freq_table[] = {
61 {L0, 1000*1000},
62 {L1, 800*1000},
63 {L2, 400*1000},
64 {L3, 200*1000},
65 {L4, 100*1000},
66 {0, CPUFREQ_TABLE_END},
67};
68
69static u32 clkdiv_val[5][11] = {
70 /*
71 * Clock divider value for following
72 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
73 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
74 * ONEDRAM, MFC, G3D }
75 */
76
77 /* L0 : [1000/200/100][166/83][133/66][200/200] */
78 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
79
80 /* L1 : [800/200/100][166/83][133/66][200/200] */
81 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
82
83 /* L2 : [400/200/100][166/83][133/66][200/200] */
84 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
85
86 /* L3 : [200/200/100][166/83][133/66][200/200] */
87 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
88
89 /* L4 : [100/100/100][83/83][66/66][100/100] */
90 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
91};
92
93/*
94 * This function set DRAM refresh counter
95 * accoriding to operating frequency of DRAM
96 * ch: DMC port number 0 or 1
97 * freq: Operating frequency of DRAM(KHz)
98 */
99static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
100{
101 unsigned long tmp, tmp1;
102 void __iomem *reg = NULL;
103
104 if (ch == DMC0) {
105 reg = (S5P_VA_DMC0 + 0x30);
106 } else if (ch == DMC1) {
107 reg = (S5P_VA_DMC1 + 0x30);
108 } else {
109 printk(KERN_ERR "Cannot find DMC port\n");
110 return;
111 }
112
113 /* Find current DRAM frequency */
114 tmp = s5pv210_dram_conf[ch].freq;
115
116 do_div(tmp, freq);
117
118 tmp1 = s5pv210_dram_conf[ch].refresh;
119
120 do_div(tmp1, tmp);
121
122 __raw_writel(tmp1, reg);
123}
124
125int s5pv210_verify_speed(struct cpufreq_policy *policy)
126{
127 if (policy->cpu)
128 return -EINVAL;
129
130 return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
131}
132
133unsigned int s5pv210_getspeed(unsigned int cpu)
134{
135 if (cpu)
136 return 0;
137
138 return clk_get_rate(cpu_clk) / 1000;
139}
140
141static int s5pv210_target(struct cpufreq_policy *policy,
142 unsigned int target_freq,
143 unsigned int relation)
144{
145 unsigned long reg;
146 unsigned int index, priv_index;
147 unsigned int pll_changing = 0;
148 unsigned int bus_speed_changing = 0;
149
150 freqs.old = s5pv210_getspeed(0);
151
152 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
153 target_freq, relation, &index))
154 return -EINVAL;
155
156 freqs.new = s5pv210_freq_table[index].frequency;
157 freqs.cpu = 0;
158
159 if (freqs.new == freqs.old)
160 return 0;
161
162 /* Finding current running level index */
163 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
164 freqs.old, relation, &priv_index))
165 return -EINVAL;
166
167 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
168
169 if (freqs.new > freqs.old) {
170 /* Voltage up: will be implemented */
171 }
172
173 /* Check if there need to change PLL */
174 if ((index == L0) || (priv_index == L0))
175 pll_changing = 1;
176
177 /* Check if there need to change System bus clock */
178 if ((index == L4) || (priv_index == L4))
179 bus_speed_changing = 1;
180
181 if (bus_speed_changing) {
182 /*
183 * Reconfigure DRAM refresh counter value for minimum
184 * temporary clock while changing divider.
185 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
186 */
187 if (pll_changing)
188 s5pv210_set_refresh(DMC1, 83000);
189 else
190 s5pv210_set_refresh(DMC1, 100000);
191
192 s5pv210_set_refresh(DMC0, 83000);
193 }
194
195 /*
196 * APLL should be changed in this level
197 * APLL -> MPLL(for stable transition) -> APLL
198 * Some clock source's clock API are not prepared.
199 * Do not use clock API in below code.
200 */
201 if (pll_changing) {
202 /*
203 * 1. Temporary Change divider for MFC and G3D
204 * SCLKA2M(200/1=200)->(200/4=50)Mhz
205 */
206 reg = __raw_readl(S5P_CLK_DIV2);
207 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
208 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
209 (3 << S5P_CLKDIV2_MFC_SHIFT);
210 __raw_writel(reg, S5P_CLK_DIV2);
211
212 /* For MFC, G3D dividing */
213 do {
214 reg = __raw_readl(S5P_CLKDIV_STAT0);
215 } while (reg & ((1 << 16) | (1 << 17)));
216
217 /*
218 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
219 * (200/4=50)->(667/4=166)Mhz
220 */
221 reg = __raw_readl(S5P_CLK_SRC2);
222 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
223 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
224 (1 << S5P_CLKSRC2_MFC_SHIFT);
225 __raw_writel(reg, S5P_CLK_SRC2);
226
227 do {
228 reg = __raw_readl(S5P_CLKMUX_STAT1);
229 } while (reg & ((1 << 7) | (1 << 3)));
230
231 /*
232 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
233 * true refresh counter is already programed in upper
234 * code. 0x287@83Mhz
235 */
236 if (!bus_speed_changing)
237 s5pv210_set_refresh(DMC1, 133000);
238
239 /* 4. SCLKAPLL -> SCLKMPLL */
240 reg = __raw_readl(S5P_CLK_SRC0);
241 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
242 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
243 __raw_writel(reg, S5P_CLK_SRC0);
244
245 do {
246 reg = __raw_readl(S5P_CLKMUX_STAT0);
247 } while (reg & (0x1 << 18));
248
249 }
250
251 /* Change divider */
252 reg = __raw_readl(S5P_CLK_DIV0);
253
254 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
255 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
256 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
257 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
258
259 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
260 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
261 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
262 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
263 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
264 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
265 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
266 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
267
268 __raw_writel(reg, S5P_CLK_DIV0);
269
270 do {
271 reg = __raw_readl(S5P_CLKDIV_STAT0);
272 } while (reg & 0xff);
273
274 /* ARM MCS value changed */
275 reg = __raw_readl(S5P_ARM_MCS_CON);
276 reg &= ~0x3;
277 if (index >= L3)
278 reg |= 0x3;
279 else
280 reg |= 0x1;
281
282 __raw_writel(reg, S5P_ARM_MCS_CON);
283
284 if (pll_changing) {
285 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
286 __raw_writel(0x2cf, S5P_APLL_LOCK);
287
288 /*
289 * 6. Turn on APLL
290 * 6-1. Set PMS values
291 * 6-2. Wait untile the PLL is locked
292 */
293 if (index == L0)
294 __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
295 else
296 __raw_writel(APLL_VAL_800, S5P_APLL_CON);
297
298 do {
299 reg = __raw_readl(S5P_APLL_CON);
300 } while (!(reg & (0x1 << 29)));
301
302 /*
303 * 7. Change souce clock from SCLKMPLL(667Mhz)
304 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
305 * (667/4=166)->(200/4=50)Mhz
306 */
307 reg = __raw_readl(S5P_CLK_SRC2);
308 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
309 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
310 (0 << S5P_CLKSRC2_MFC_SHIFT);
311 __raw_writel(reg, S5P_CLK_SRC2);
312
313 do {
314 reg = __raw_readl(S5P_CLKMUX_STAT1);
315 } while (reg & ((1 << 7) | (1 << 3)));
316
317 /*
318 * 8. Change divider for MFC and G3D
319 * (200/4=50)->(200/1=200)Mhz
320 */
321 reg = __raw_readl(S5P_CLK_DIV2);
322 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
323 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
324 (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
325 __raw_writel(reg, S5P_CLK_DIV2);
326
327 /* For MFC, G3D dividing */
328 do {
329 reg = __raw_readl(S5P_CLKDIV_STAT0);
330 } while (reg & ((1 << 16) | (1 << 17)));
331
332 /* 9. Change MPLL to APLL in MSYS_MUX */
333 reg = __raw_readl(S5P_CLK_SRC0);
334 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
335 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
336 __raw_writel(reg, S5P_CLK_SRC0);
337
338 do {
339 reg = __raw_readl(S5P_CLKMUX_STAT0);
340 } while (reg & (0x1 << 18));
341
342 /*
343 * 10. DMC1 refresh counter
344 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
345 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
346 */
347 if (!bus_speed_changing)
348 s5pv210_set_refresh(DMC1, 200000);
349 }
350
351 /*
352 * L4 level need to change memory bus speed, hence onedram clock divier
353 * and memory refresh parameter should be changed
354 */
355 if (bus_speed_changing) {
356 reg = __raw_readl(S5P_CLK_DIV6);
357 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
358 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
359 __raw_writel(reg, S5P_CLK_DIV6);
360
361 do {
362 reg = __raw_readl(S5P_CLKDIV_STAT1);
363 } while (reg & (1 << 15));
364
365 /* Reconfigure DRAM refresh counter value */
366 if (index != L4) {
367 /*
368 * DMC0 : 166Mhz
369 * DMC1 : 200Mhz
370 */
371 s5pv210_set_refresh(DMC0, 166000);
372 s5pv210_set_refresh(DMC1, 200000);
373 } else {
374 /*
375 * DMC0 : 83Mhz
376 * DMC1 : 100Mhz
377 */
378 s5pv210_set_refresh(DMC0, 83000);
379 s5pv210_set_refresh(DMC1, 100000);
380 }
381 }
382
383 if (freqs.new < freqs.old) {
384 /* Voltage down: will be implemented */
385 }
386
387 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
388
389 printk(KERN_DEBUG "Perf changed[L%d]\n", index);
390
391 return 0;
392}
393
394#ifdef CONFIG_PM
395static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
396{
397 return 0;
398}
399
400static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
401{
402 return 0;
403}
404#endif
405
406static int check_mem_type(void __iomem *dmc_reg)
407{
408 unsigned long val;
409
410 val = __raw_readl(dmc_reg + 0x4);
411 val = (val & (0xf << 8));
412
413 return val >> 8;
414}
415
416static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
417{
418 unsigned long mem_type;
419
420 cpu_clk = clk_get(NULL, "armclk");
421 if (IS_ERR(cpu_clk))
422 return PTR_ERR(cpu_clk);
423
424 dmc0_clk = clk_get(NULL, "sclk_dmc0");
425 if (IS_ERR(dmc0_clk)) {
426 clk_put(cpu_clk);
427 return PTR_ERR(dmc0_clk);
428 }
429
430 dmc1_clk = clk_get(NULL, "hclk_msys");
431 if (IS_ERR(dmc1_clk)) {
432 clk_put(dmc0_clk);
433 clk_put(cpu_clk);
434 return PTR_ERR(dmc1_clk);
435 }
436
437 if (policy->cpu != 0)
438 return -EINVAL;
439
440 /*
441 * check_mem_type : This driver only support LPDDR & LPDDR2.
442 * other memory type is not supported.
443 */
444 mem_type = check_mem_type(S5P_VA_DMC0);
445
446 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
447 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
448 return -EINVAL;
449 }
450
451 /* Find current refresh counter and frequency each DMC */
452 s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
453 s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
454
455 s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
456 s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
457
458 policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
459
460 cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
461
462 policy->cpuinfo.transition_latency = 40000;
463
464 return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
465}
466
467static struct cpufreq_driver s5pv210_driver = {
468 .flags = CPUFREQ_STICKY,
469 .verify = s5pv210_verify_speed,
470 .target = s5pv210_target,
471 .get = s5pv210_getspeed,
472 .init = s5pv210_cpu_init,
473 .name = "s5pv210",
474#ifdef CONFIG_PM
475 .suspend = s5pv210_cpufreq_suspend,
476 .resume = s5pv210_cpufreq_resume,
477#endif
478};
479
480static int __init s5pv210_cpufreq_init(void)
481{
482 return cpufreq_register_driver(&s5pv210_driver);
483}
484
485late_initcall(s5pv210_cpufreq_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
deleted file mode 100644
index 60d992989bdc..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
3 *
4 * Dummy framebuffer to allow build for the moment.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_MACH_REGS_FB_H
12#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
13
14#include <plat/regs-fb-v4.h>
15
16static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
17{
18 return 0x2400 + (window * 256 *4 ) + reg;
19}
20
21#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 4e1d8ff5ae59..509627f25111 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/gpio-cfg.h> 33#include <plat/gpio-cfg.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
@@ -40,6 +39,7 @@
40#include <plat/fimc-core.h> 39#include <plat/fimc-core.h>
41#include <plat/sdhci.h> 40#include <plat/sdhci.h>
42#include <plat/s5p-time.h> 41#include <plat/s5p-time.h>
42#include <plat/regs-fb-v4.h>
43 43
44/* Following are default values for UCON, ULCON and UFCON UART registers */ 44/* Following are default values for UCON, ULCON and UFCON UART registers */
45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e9b1406cb566..85c2d51a0956 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -34,7 +34,6 @@
34 34
35#include <mach/map.h> 35#include <mach/map.h>
36#include <mach/regs-clock.h> 36#include <mach/regs-clock.h>
37#include <mach/regs-fb.h>
38 37
39#include <plat/gpio-cfg.h> 38#include <plat/gpio-cfg.h>
40#include <plat/regs-serial.h> 39#include <plat/regs-serial.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index c6900f8bf3ce..5e011fc6720d 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
35#include <plat/regs-srom.h> 34#include <plat/regs-srom.h>
@@ -45,6 +44,8 @@
45#include <plat/pm.h> 44#include <plat/pm.h>
46#include <plat/fb.h> 45#include <plat/fb.h>
47#include <plat/s5p-time.h> 46#include <plat/s5p-time.h>
47#include <plat/backlight.h>
48#include <plat/regs-fb-v4.h>
48 49
49/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
50#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
210 .setup_gpio = s5pv210_fb_gpio_setup_24bpp, 211 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
211}; 212};
212 213
213static int smdkv210_backlight_init(struct device *dev)
214{
215 int ret;
216
217 ret = gpio_request(S5PV210_GPD0(3), "Backlight");
218 if (ret) {
219 printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
220 return ret;
221 }
222
223 /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
224 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
225
226 return 0;
227}
228
229static void smdkv210_backlight_exit(struct device *dev)
230{
231 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
232 gpio_free(S5PV210_GPD0(3));
233}
234
235static struct platform_pwm_backlight_data smdkv210_backlight_data = {
236 .pwm_id = 3,
237 .max_brightness = 255,
238 .dft_brightness = 255,
239 .pwm_period_ns = 78770,
240 .init = smdkv210_backlight_init,
241 .exit = smdkv210_backlight_exit,
242};
243
244static struct platform_device smdkv210_backlight_device = {
245 .name = "pwm-backlight",
246 .dev = {
247 .parent = &s3c_device_timer[3].dev,
248 .platform_data = &smdkv210_backlight_data,
249 },
250};
251
252static struct platform_device *smdkv210_devices[] __initdata = { 214static struct platform_device *smdkv210_devices[] __initdata = {
253 &s3c_device_adc, 215 &s3c_device_adc,
254 &s3c_device_cfcon, 216 &s3c_device_cfcon,
@@ -271,8 +233,6 @@ static struct platform_device *smdkv210_devices[] __initdata = {
271 &samsung_device_keypad, 233 &samsung_device_keypad,
272 &smdkv210_dm9000, 234 &smdkv210_dm9000,
273 &smdkv210_lcd_lte480wv, 235 &smdkv210_lcd_lte480wv,
274 &s3c_device_timer[3],
275 &smdkv210_backlight_device,
276}; 236};
277 237
278static void __init smdkv210_dm9000_init(void) 238static void __init smdkv210_dm9000_init(void)
@@ -311,6 +271,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
311 .oversampling_shift = 2, 271 .oversampling_shift = 2,
312}; 272};
313 273
274/* LCD Backlight data */
275static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
276 .no = S5PV210_GPD0(3),
277 .func = S3C_GPIO_SFN(2),
278};
279
280static struct platform_pwm_backlight_data smdkv210_bl_data = {
281 .pwm_id = 3,
282};
283
314static void __init smdkv210_map_io(void) 284static void __init smdkv210_map_io(void)
315{ 285{
316 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 286 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -342,6 +312,8 @@ static void __init smdkv210_machine_init(void)
342 312
343 s3c_fb_set_platdata(&smdkv210_lcd0_pdata); 313 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
344 314
315 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
316
345 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); 317 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
346} 318}
347 319
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 24febae3d4c0..309e388a8a83 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
88 SAVE_ITEM(S3C2410_TCNTO(0)), 88 SAVE_ITEM(S3C2410_TCNTO(0)),
89}; 89};
90 90
91void s5pv210_cpu_suspend(void) 91void s5pv210_cpu_suspend(unsigned long arg)
92{ 92{
93 unsigned long tmp; 93 unsigned long tmp;
94 94
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index e932ebfac56d..55103c8220b3 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -15,7 +15,6 @@
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17 17
18#include <mach/regs-fb.h>
19#include <mach/map.h> 18#include <mach/map.h>
20#include <plat/fb.h> 19#include <plat/fb.h>
21#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index a3d649466fb1..e3452ccd4b08 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -32,27 +32,6 @@
32 32
33 .text 33 .text
34 34
35 /* s3c_cpu_save
36 *
37 * entry:
38 * r1 = v:p offset
39 */
40
41ENTRY(s3c_cpu_save)
42
43 stmfd sp!, { r3 - r12, lr }
44 ldr r3, =resume_with_mmu
45 bl cpu_suspend
46
47 ldr r0, =pm_cpu_sleep
48 ldr r0, [ r0 ]
49 mov pc, r0
50
51resume_with_mmu:
52 ldmfd sp!, { r3 - r12, pc }
53
54 .ltorg
55
56 /* sleep magic, to allow the bootloader to check for an valid 35 /* sleep magic, to allow the bootloader to check for an valid
57 * image to resume to. Must be the first word before the 36 * image to resume to. Must be the first word before the
58 * s3c_cpu_resume entry. 37 * s3c_cpu_resume entry.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 23:01:04 -0500