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-rw-r--r--arch/arm/mach-s5pv210/Kconfig197
-rw-r--r--arch/arm/mach-s5pv210/Makefile29
-rw-r--r--arch/arm/mach-s5pv210/Makefile.boot2
-rw-r--r--arch/arm/mach-s5pv210/clock.c1365
-rw-r--r--arch/arm/mach-s5pv210/common.c279
-rw-r--r--arch/arm/mach-s5pv210/common.h21
-rw-r--r--arch/arm/mach-s5pv210/dev-audio.c246
-rw-r--r--arch/arm/mach-s5pv210/dma.c130
-rw-r--r--arch/arm/mach-s5pv210/include/mach/debug-macro.S41
-rw-r--r--arch/arm/mach-s5pv210/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pv210/include/mach/gpio.h140
-rw-r--r--arch/arm/mach-s5pv210/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h137
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h158
-rw-r--r--arch/arm/mach-s5pv210/include/mach/memory.h25
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pm-core.h46
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-gpio.h41
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c687
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c916
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c159
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c337
-rw-r--r--arch/arm/mach-s5pv210/mach-torbreck.c135
-rw-r--r--arch/arm/mach-s5pv210/pm.c147
-rw-r--r--arch/arm/mach-s5pv210/s5pv210.c77
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c49
-rw-r--r--arch/arm/mach-s5pv210/setup-fimc.c43
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c0.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c1.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c2.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-ide.c39
-rw-r--r--arch/arm/mach-s5pv210/setup-keypad.c24
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci-gpio.c103
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c34
-rw-r--r--arch/arm/mach-s5pv210/setup-usb-phy.c95
-rw-r--r--arch/arm/mach-s5pv210/sleep.S36
37 files changed, 221 insertions, 5665 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index f60f2862856d..330bfc8fcd52 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -7,193 +7,28 @@
7 7
8# Configuration options for the S5PV210/S5PC110 8# Configuration options for the S5PV210/S5PC110
9 9
10config ARCH_S5PV210
11 bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7
12 select ARCH_HAS_HOLES_MEMORYMODEL
13 select ARCH_REQUIRE_GPIOLIB
14 select ARM_VIC
15 select CLKSRC_SAMSUNG_PWM
16 select COMMON_CLK_SAMSUNG
17 select HAVE_S3C2410_I2C if I2C
18 select HAVE_S3C2410_WATCHDOG if WATCHDOG
19 select HAVE_S3C_RTC if RTC_CLASS
20 select PINCTRL
21 select PINCTRL_EXYNOS
22 help
23 Samsung S5PV210/S5PC110 series based systems
24
10if ARCH_S5PV210 25if ARCH_S5PV210
11 26
12config CPU_S5PV210 27config CPU_S5PV210
13 bool 28 def_bool y
14 select ARM_AMBA 29 select ARM_AMBA
15 select PL330_DMA if DMADEVICES 30 select PL330_DMA if DMADEVICES
16 select S5P_EXT_INT
17 select S5P_PM if PM
18 select S5P_SLEEP if PM
19 help 31 help
20 Enable S5PV210 CPU support 32 Enable S5PV210 CPU support
21 33
22config S5PV210_SETUP_I2C1
23 bool
24 help
25 Common setup code for i2c bus 1.
26
27config S5PV210_SETUP_I2C2
28 bool
29 help
30 Common setup code for i2c bus 2.
31
32config S5PV210_SETUP_IDE
33 bool
34 help
35 Common setup code for S5PV210 IDE GPIO configurations
36
37config S5PV210_SETUP_FB_24BPP
38 bool
39 help
40 Common setup code for S5PV210 with an 24bpp RGB display helper.
41
42config S5PV210_SETUP_KEYPAD
43 bool
44 help
45 Common setup code for keypad.
46
47config S5PV210_SETUP_SDHCI
48 bool
49 select S5PV210_SETUP_SDHCI_GPIO
50 help
51 Internal helper functions for S5PV210 based SDHCI systems
52
53config S5PV210_SETUP_SDHCI_GPIO
54 bool
55 help
56 Common setup code for SDHCI gpio.
57
58config S5PV210_SETUP_FIMC
59 bool
60 help
61 Common setup code for the camera interfaces.
62
63config S5PV210_SETUP_SPI
64 bool
65 help
66 Common setup code for SPI GPIO configurations.
67
68config S5PV210_SETUP_USB_PHY
69 bool
70 help
71 Common setup code for USB PHY controller
72
73menu "S5PC110 Machines"
74
75config MACH_AQUILA
76 bool "Aquila"
77 select CPU_S5PV210
78 select S3C_DEV_FB
79 select S3C_DEV_HSMMC
80 select S3C_DEV_HSMMC1
81 select S3C_DEV_HSMMC2
82 select S5PV210_SETUP_FB_24BPP
83 select S5PV210_SETUP_SDHCI
84 select S5PV210_SETUP_USB_PHY
85 select S5P_DEV_FIMC0
86 select S5P_DEV_FIMC1
87 select S5P_DEV_FIMC2
88 select S5P_DEV_ONENAND
89 help
90 Machine support for the Samsung Aquila target based on S5PC110 SoC
91
92config MACH_GONI
93 bool "GONI"
94 select CPU_S5PV210
95 select S3C_DEV_FB
96 select S3C_DEV_HSMMC
97 select S3C_DEV_HSMMC1
98 select S3C_DEV_HSMMC2
99 select S3C_DEV_I2C1
100 select S3C_DEV_I2C2
101 select S3C_DEV_USB_HSOTG
102 select S5PV210_SETUP_FB_24BPP
103 select S5PV210_SETUP_FIMC
104 select S5PV210_SETUP_I2C1
105 select S5PV210_SETUP_I2C2
106 select S5PV210_SETUP_KEYPAD
107 select S5PV210_SETUP_SDHCI
108 select S5PV210_SETUP_USB_PHY
109 select S5P_DEV_FIMC0
110 select S5P_DEV_FIMC1
111 select S5P_DEV_FIMC2
112 select S5P_DEV_MFC
113 select S5P_DEV_ONENAND
114 select S5P_DEV_TV
115 select S5P_GPIO_INT
116 select SAMSUNG_DEV_KEYPAD
117 help
118 Machine support for Samsung GONI board
119 S5PC110(MCP) is one of package option of S5PV210
120
121config MACH_SMDKC110
122 bool "SMDKC110"
123 select CPU_S5PV210
124 select S3C_DEV_I2C1
125 select S3C_DEV_I2C2
126 select S3C_DEV_RTC
127 select S3C_DEV_WDT
128 select S5PV210_SETUP_I2C1
129 select S5PV210_SETUP_I2C2
130 select S5PV210_SETUP_IDE
131 select S5P_DEV_FIMC0
132 select S5P_DEV_FIMC1
133 select S5P_DEV_FIMC2
134 select S5P_DEV_MFC
135 select SAMSUNG_DEV_IDE
136 help
137 Machine support for Samsung SMDKC110
138 S5PC110(MCP) is one of package option of S5PV210
139
140endmenu
141
142menu "S5PV210 Machines"
143
144config MACH_SMDKV210
145 bool "SMDKV210"
146 select CPU_S5PV210
147 select S3C_DEV_FB
148 select S3C_DEV_HSMMC
149 select S3C_DEV_HSMMC1
150 select S3C_DEV_HSMMC2
151 select S3C_DEV_HSMMC3
152 select S3C_DEV_I2C1
153 select S3C_DEV_I2C2
154 select S3C_DEV_RTC
155 select S3C_DEV_USB_HSOTG
156 select S3C_DEV_WDT
157 select S5PV210_SETUP_FB_24BPP
158 select S5PV210_SETUP_I2C1
159 select S5PV210_SETUP_I2C2
160 select S5PV210_SETUP_IDE
161 select S5PV210_SETUP_KEYPAD
162 select S5PV210_SETUP_SDHCI
163 select S5PV210_SETUP_USB_PHY
164 select S5P_DEV_FIMC0
165 select S5P_DEV_FIMC1
166 select S5P_DEV_FIMC2
167 select S5P_DEV_JPEG
168 select S5P_DEV_MFC
169 select SAMSUNG_DEV_ADC
170 select SAMSUNG_DEV_BACKLIGHT
171 select SAMSUNG_DEV_IDE
172 select SAMSUNG_DEV_KEYPAD
173 select SAMSUNG_DEV_PWM
174 select SAMSUNG_DEV_TS
175 help
176 Machine support for Samsung SMDKV210
177
178config MACH_TORBRECK
179 bool "Torbreck"
180 select ARCH_SPARSEMEM_ENABLE
181 select CPU_S5PV210
182 select S3C_DEV_HSMMC
183 select S3C_DEV_HSMMC1
184 select S3C_DEV_HSMMC2
185 select S3C_DEV_HSMMC3
186 select S3C_DEV_I2C1
187 select S3C_DEV_I2C2
188 select S3C_DEV_RTC
189 select S3C_DEV_WDT
190 select S5PV210_SETUP_I2C1
191 select S5PV210_SETUP_I2C2
192 select S5PV210_SETUP_SDHCI
193 select SAMSUNG_DEV_IDE
194 help
195 Machine support for aESOP Torbreck
196
197endmenu
198
199endif 34endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 1c4e41998a10..7dc2d0e25a83 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -5,6 +5,8 @@
5# 5#
6# Licensed under GPLv2 6# Licensed under GPLv2
7 7
8ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
9
8obj-y := 10obj-y :=
9obj-m := 11obj-m :=
10obj-n := 12obj-n :=
@@ -12,31 +14,8 @@ obj- :=
12 14
13# Core 15# Core
14 16
15obj-y += common.o clock.o 17obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
16
17obj-$(CONFIG_PM) += pm.o
18
19obj-y += dma.o
20 18
21# machine support 19# machine support
22 20
23obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o 21obj-y += s5pv210.o
24obj-$(CONFIG_MACH_GONI) += mach-goni.o
25obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
26obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
27obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
28
29# device support
30
31obj-y += dev-audio.o
32
33obj-y += setup-i2c0.o
34obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
36obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
37obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
38obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
39obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
40obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
41obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
42obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pv210/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
deleted file mode 100644
index ca463724a3df..000000000000
--- a/arch/arm/mach-s5pv210/clock.c
+++ /dev/null
@@ -1,1365 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/map.h>
24
25#include <plat/cpu-freq.h>
26#include <mach/regs-clock.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/pll.h>
30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h>
32
33#include "common.h"
34
35static unsigned long xtal;
36
37static struct clksrc_clk clk_mout_apll = {
38 .clk = {
39 .name = "mout_apll",
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static struct clksrc_clk clk_mout_epll = {
46 .clk = {
47 .name = "mout_epll",
48 },
49 .sources = &clk_src_epll,
50 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
51};
52
53static struct clksrc_clk clk_mout_mpll = {
54 .clk = {
55 .name = "mout_mpll",
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
61static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
64};
65
66static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
69};
70
71static struct clksrc_clk clk_armclk = {
72 .clk = {
73 .name = "armclk",
74 },
75 .sources = &clkset_armclk,
76 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
77 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
78};
79
80static struct clksrc_clk clk_hclk_msys = {
81 .clk = {
82 .name = "hclk_msys",
83 .parent = &clk_armclk.clk,
84 },
85 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
86};
87
88static struct clksrc_clk clk_pclk_msys = {
89 .clk = {
90 .name = "pclk_msys",
91 .parent = &clk_hclk_msys.clk,
92 },
93 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
94};
95
96static struct clksrc_clk clk_sclk_a2m = {
97 .clk = {
98 .name = "sclk_a2m",
99 .parent = &clk_mout_apll.clk,
100 },
101 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
102};
103
104static struct clk *clkset_hclk_sys_list[] = {
105 [0] = &clk_mout_mpll.clk,
106 [1] = &clk_sclk_a2m.clk,
107};
108
109static struct clksrc_sources clkset_hclk_sys = {
110 .sources = clkset_hclk_sys_list,
111 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
112};
113
114static struct clksrc_clk clk_hclk_dsys = {
115 .clk = {
116 .name = "hclk_dsys",
117 },
118 .sources = &clkset_hclk_sys,
119 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
120 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
121};
122
123static struct clksrc_clk clk_pclk_dsys = {
124 .clk = {
125 .name = "pclk_dsys",
126 .parent = &clk_hclk_dsys.clk,
127 },
128 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
129};
130
131static struct clksrc_clk clk_hclk_psys = {
132 .clk = {
133 .name = "hclk_psys",
134 },
135 .sources = &clkset_hclk_sys,
136 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
137 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
138};
139
140static struct clksrc_clk clk_pclk_psys = {
141 .clk = {
142 .name = "pclk_psys",
143 .parent = &clk_hclk_psys.clk,
144 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
146};
147
148static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
149{
150 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
151}
152
153static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
154{
155 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
156}
157
158static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
159{
160 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
161}
162
163static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
164{
165 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
166}
167
168static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
169{
170 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
171}
172
173static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174{
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176}
177
178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181}
182
183static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
184{
185 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
186}
187
188static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m",
190 .rate = 27000000,
191};
192
193static struct clk clk_sclk_hdmiphy = {
194 .name = "sclk_hdmiphy",
195};
196
197static struct clk clk_sclk_usbphy0 = {
198 .name = "sclk_usbphy0",
199};
200
201static struct clk clk_sclk_usbphy1 = {
202 .name = "sclk_usbphy1",
203};
204
205static struct clk clk_pcmcdclk0 = {
206 .name = "pcmcdclk",
207};
208
209static struct clk clk_pcmcdclk1 = {
210 .name = "pcmcdclk",
211};
212
213static struct clk clk_pcmcdclk2 = {
214 .name = "pcmcdclk",
215};
216
217static struct clk *clkset_vpllsrc_list[] = {
218 [0] = &clk_fin_vpll,
219 [1] = &clk_sclk_hdmi27m,
220};
221
222static struct clksrc_sources clkset_vpllsrc = {
223 .sources = clkset_vpllsrc_list,
224 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
225};
226
227static struct clksrc_clk clk_vpllsrc = {
228 .clk = {
229 .name = "vpll_src",
230 .enable = s5pv210_clk_mask0_ctrl,
231 .ctrlbit = (1 << 7),
232 },
233 .sources = &clkset_vpllsrc,
234 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
235};
236
237static struct clk *clkset_sclk_vpll_list[] = {
238 [0] = &clk_vpllsrc.clk,
239 [1] = &clk_fout_vpll,
240};
241
242static struct clksrc_sources clkset_sclk_vpll = {
243 .sources = clkset_sclk_vpll_list,
244 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
245};
246
247static struct clksrc_clk clk_sclk_vpll = {
248 .clk = {
249 .name = "sclk_vpll",
250 },
251 .sources = &clkset_sclk_vpll,
252 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
253};
254
255static struct clk *clkset_moutdmc0src_list[] = {
256 [0] = &clk_sclk_a2m.clk,
257 [1] = &clk_mout_mpll.clk,
258 [2] = NULL,
259 [3] = NULL,
260};
261
262static struct clksrc_sources clkset_moutdmc0src = {
263 .sources = clkset_moutdmc0src_list,
264 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
265};
266
267static struct clksrc_clk clk_mout_dmc0 = {
268 .clk = {
269 .name = "mout_dmc0",
270 },
271 .sources = &clkset_moutdmc0src,
272 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
273};
274
275static struct clksrc_clk clk_sclk_dmc0 = {
276 .clk = {
277 .name = "sclk_dmc0",
278 .parent = &clk_mout_dmc0.clk,
279 },
280 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
281};
282
283static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
284{
285 return clk_get_rate(clk->parent) / 2;
286}
287
288static struct clk_ops clk_hclk_imem_ops = {
289 .get_rate = s5pv210_clk_imem_get_rate,
290};
291
292static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
293{
294 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
295}
296
297static struct clk_ops clk_fout_apll_ops = {
298 .get_rate = s5pv210_clk_fout_apll_get_rate,
299};
300
301static struct clk init_clocks_off[] = {
302 {
303 .name = "rot",
304 .parent = &clk_hclk_dsys.clk,
305 .enable = s5pv210_clk_ip0_ctrl,
306 .ctrlbit = (1<<29),
307 }, {
308 .name = "fimc",
309 .devname = "s5pv210-fimc.0",
310 .parent = &clk_hclk_dsys.clk,
311 .enable = s5pv210_clk_ip0_ctrl,
312 .ctrlbit = (1 << 24),
313 }, {
314 .name = "fimc",
315 .devname = "s5pv210-fimc.1",
316 .parent = &clk_hclk_dsys.clk,
317 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 25),
319 }, {
320 .name = "fimc",
321 .devname = "s5pv210-fimc.2",
322 .parent = &clk_hclk_dsys.clk,
323 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 26),
325 }, {
326 .name = "jpeg",
327 .parent = &clk_hclk_dsys.clk,
328 .enable = s5pv210_clk_ip0_ctrl,
329 .ctrlbit = (1 << 28),
330 }, {
331 .name = "mfc",
332 .devname = "s5p-mfc",
333 .parent = &clk_pclk_psys.clk,
334 .enable = s5pv210_clk_ip0_ctrl,
335 .ctrlbit = (1 << 16),
336 }, {
337 .name = "dac",
338 .devname = "s5p-sdo",
339 .parent = &clk_hclk_dsys.clk,
340 .enable = s5pv210_clk_ip1_ctrl,
341 .ctrlbit = (1 << 10),
342 }, {
343 .name = "mixer",
344 .devname = "s5p-mixer",
345 .parent = &clk_hclk_dsys.clk,
346 .enable = s5pv210_clk_ip1_ctrl,
347 .ctrlbit = (1 << 9),
348 }, {
349 .name = "vp",
350 .devname = "s5p-mixer",
351 .parent = &clk_hclk_dsys.clk,
352 .enable = s5pv210_clk_ip1_ctrl,
353 .ctrlbit = (1 << 8),
354 }, {
355 .name = "hdmi",
356 .devname = "s5pv210-hdmi",
357 .parent = &clk_hclk_dsys.clk,
358 .enable = s5pv210_clk_ip1_ctrl,
359 .ctrlbit = (1 << 11),
360 }, {
361 .name = "hdmiphy",
362 .devname = "s5pv210-hdmi",
363 .enable = s5pv210_clk_hdmiphy_ctrl,
364 .ctrlbit = (1 << 0),
365 }, {
366 .name = "dacphy",
367 .devname = "s5p-sdo",
368 .enable = exynos4_clk_dac_ctrl,
369 .ctrlbit = (1 << 0),
370 }, {
371 .name = "otg",
372 .parent = &clk_hclk_psys.clk,
373 .enable = s5pv210_clk_ip1_ctrl,
374 .ctrlbit = (1<<16),
375 }, {
376 .name = "usb-host",
377 .parent = &clk_hclk_psys.clk,
378 .enable = s5pv210_clk_ip1_ctrl,
379 .ctrlbit = (1<<17),
380 }, {
381 .name = "lcd",
382 .parent = &clk_hclk_dsys.clk,
383 .enable = s5pv210_clk_ip1_ctrl,
384 .ctrlbit = (1<<0),
385 }, {
386 .name = "cfcon",
387 .parent = &clk_hclk_psys.clk,
388 .enable = s5pv210_clk_ip1_ctrl,
389 .ctrlbit = (1<<25),
390 }, {
391 .name = "systimer",
392 .parent = &clk_pclk_psys.clk,
393 .enable = s5pv210_clk_ip3_ctrl,
394 .ctrlbit = (1<<16),
395 }, {
396 .name = "watchdog",
397 .parent = &clk_pclk_psys.clk,
398 .enable = s5pv210_clk_ip3_ctrl,
399 .ctrlbit = (1<<22),
400 }, {
401 .name = "rtc",
402 .parent = &clk_pclk_psys.clk,
403 .enable = s5pv210_clk_ip3_ctrl,
404 .ctrlbit = (1<<15),
405 }, {
406 .name = "i2c",
407 .devname = "s3c2440-i2c.0",
408 .parent = &clk_pclk_psys.clk,
409 .enable = s5pv210_clk_ip3_ctrl,
410 .ctrlbit = (1<<7),
411 }, {
412 .name = "i2c",
413 .devname = "s3c2440-i2c.1",
414 .parent = &clk_pclk_psys.clk,
415 .enable = s5pv210_clk_ip3_ctrl,
416 .ctrlbit = (1 << 10),
417 }, {
418 .name = "i2c",
419 .devname = "s3c2440-i2c.2",
420 .parent = &clk_pclk_psys.clk,
421 .enable = s5pv210_clk_ip3_ctrl,
422 .ctrlbit = (1<<9),
423 }, {
424 .name = "i2c",
425 .devname = "s3c2440-hdmiphy-i2c",
426 .parent = &clk_pclk_psys.clk,
427 .enable = s5pv210_clk_ip3_ctrl,
428 .ctrlbit = (1 << 11),
429 }, {
430 .name = "spi",
431 .devname = "s5pv210-spi.0",
432 .parent = &clk_pclk_psys.clk,
433 .enable = s5pv210_clk_ip3_ctrl,
434 .ctrlbit = (1<<12),
435 }, {
436 .name = "spi",
437 .devname = "s5pv210-spi.1",
438 .parent = &clk_pclk_psys.clk,
439 .enable = s5pv210_clk_ip3_ctrl,
440 .ctrlbit = (1<<13),
441 }, {
442 .name = "spi",
443 .devname = "s5pv210-spi.2",
444 .parent = &clk_pclk_psys.clk,
445 .enable = s5pv210_clk_ip3_ctrl,
446 .ctrlbit = (1<<14),
447 }, {
448 .name = "timers",
449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<23),
452 }, {
453 .name = "adc",
454 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<24),
457 }, {
458 .name = "keypad",
459 .parent = &clk_pclk_psys.clk,
460 .enable = s5pv210_clk_ip3_ctrl,
461 .ctrlbit = (1<<21),
462 }, {
463 .name = "iis",
464 .devname = "samsung-i2s.0",
465 .parent = &clk_p,
466 .enable = s5pv210_clk_ip3_ctrl,
467 .ctrlbit = (1<<4),
468 }, {
469 .name = "iis",
470 .devname = "samsung-i2s.1",
471 .parent = &clk_p,
472 .enable = s5pv210_clk_ip3_ctrl,
473 .ctrlbit = (1 << 5),
474 }, {
475 .name = "iis",
476 .devname = "samsung-i2s.2",
477 .parent = &clk_p,
478 .enable = s5pv210_clk_ip3_ctrl,
479 .ctrlbit = (1 << 6),
480 }, {
481 .name = "spdif",
482 .parent = &clk_p,
483 .enable = s5pv210_clk_ip3_ctrl,
484 .ctrlbit = (1 << 0),
485 },
486};
487
488static struct clk init_clocks[] = {
489 {
490 .name = "hclk_imem",
491 .parent = &clk_hclk_msys.clk,
492 .ctrlbit = (1 << 5),
493 .enable = s5pv210_clk_ip0_ctrl,
494 .ops = &clk_hclk_imem_ops,
495 }, {
496 .name = "uart",
497 .devname = "s5pv210-uart.0",
498 .parent = &clk_pclk_psys.clk,
499 .enable = s5pv210_clk_ip3_ctrl,
500 .ctrlbit = (1 << 17),
501 }, {
502 .name = "uart",
503 .devname = "s5pv210-uart.1",
504 .parent = &clk_pclk_psys.clk,
505 .enable = s5pv210_clk_ip3_ctrl,
506 .ctrlbit = (1 << 18),
507 }, {
508 .name = "uart",
509 .devname = "s5pv210-uart.2",
510 .parent = &clk_pclk_psys.clk,
511 .enable = s5pv210_clk_ip3_ctrl,
512 .ctrlbit = (1 << 19),
513 }, {
514 .name = "uart",
515 .devname = "s5pv210-uart.3",
516 .parent = &clk_pclk_psys.clk,
517 .enable = s5pv210_clk_ip3_ctrl,
518 .ctrlbit = (1 << 20),
519 }, {
520 .name = "sromc",
521 .parent = &clk_hclk_psys.clk,
522 .enable = s5pv210_clk_ip1_ctrl,
523 .ctrlbit = (1 << 26),
524 },
525};
526
527static struct clk clk_hsmmc0 = {
528 .name = "hsmmc",
529 .devname = "s3c-sdhci.0",
530 .parent = &clk_hclk_psys.clk,
531 .enable = s5pv210_clk_ip2_ctrl,
532 .ctrlbit = (1<<16),
533};
534
535static struct clk clk_hsmmc1 = {
536 .name = "hsmmc",
537 .devname = "s3c-sdhci.1",
538 .parent = &clk_hclk_psys.clk,
539 .enable = s5pv210_clk_ip2_ctrl,
540 .ctrlbit = (1<<17),
541};
542
543static struct clk clk_hsmmc2 = {
544 .name = "hsmmc",
545 .devname = "s3c-sdhci.2",
546 .parent = &clk_hclk_psys.clk,
547 .enable = s5pv210_clk_ip2_ctrl,
548 .ctrlbit = (1<<18),
549};
550
551static struct clk clk_hsmmc3 = {
552 .name = "hsmmc",
553 .devname = "s3c-sdhci.3",
554 .parent = &clk_hclk_psys.clk,
555 .enable = s5pv210_clk_ip2_ctrl,
556 .ctrlbit = (1<<19),
557};
558
559static struct clk clk_pdma0 = {
560 .name = "pdma0",
561 .parent = &clk_hclk_psys.clk,
562 .enable = s5pv210_clk_ip0_ctrl,
563 .ctrlbit = (1 << 3),
564};
565
566static struct clk clk_pdma1 = {
567 .name = "pdma1",
568 .parent = &clk_hclk_psys.clk,
569 .enable = s5pv210_clk_ip0_ctrl,
570 .ctrlbit = (1 << 4),
571};
572
573static struct clk *clkset_uart_list[] = {
574 [6] = &clk_mout_mpll.clk,
575 [7] = &clk_mout_epll.clk,
576};
577
578static struct clksrc_sources clkset_uart = {
579 .sources = clkset_uart_list,
580 .nr_sources = ARRAY_SIZE(clkset_uart_list),
581};
582
583static struct clk *clkset_group1_list[] = {
584 [0] = &clk_sclk_a2m.clk,
585 [1] = &clk_mout_mpll.clk,
586 [2] = &clk_mout_epll.clk,
587 [3] = &clk_sclk_vpll.clk,
588};
589
590static struct clksrc_sources clkset_group1 = {
591 .sources = clkset_group1_list,
592 .nr_sources = ARRAY_SIZE(clkset_group1_list),
593};
594
595static struct clk *clkset_sclk_onenand_list[] = {
596 [0] = &clk_hclk_psys.clk,
597 [1] = &clk_hclk_dsys.clk,
598};
599
600static struct clksrc_sources clkset_sclk_onenand = {
601 .sources = clkset_sclk_onenand_list,
602 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
603};
604
605static struct clk *clkset_sclk_dac_list[] = {
606 [0] = &clk_sclk_vpll.clk,
607 [1] = &clk_sclk_hdmiphy,
608};
609
610static struct clksrc_sources clkset_sclk_dac = {
611 .sources = clkset_sclk_dac_list,
612 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
613};
614
615static struct clksrc_clk clk_sclk_dac = {
616 .clk = {
617 .name = "sclk_dac",
618 .enable = s5pv210_clk_mask0_ctrl,
619 .ctrlbit = (1 << 2),
620 },
621 .sources = &clkset_sclk_dac,
622 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
623};
624
625static struct clksrc_clk clk_sclk_pixel = {
626 .clk = {
627 .name = "sclk_pixel",
628 .parent = &clk_sclk_vpll.clk,
629 },
630 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
631};
632
633static struct clk *clkset_sclk_hdmi_list[] = {
634 [0] = &clk_sclk_pixel.clk,
635 [1] = &clk_sclk_hdmiphy,
636};
637
638static struct clksrc_sources clkset_sclk_hdmi = {
639 .sources = clkset_sclk_hdmi_list,
640 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
641};
642
643static struct clksrc_clk clk_sclk_hdmi = {
644 .clk = {
645 .name = "sclk_hdmi",
646 .enable = s5pv210_clk_mask0_ctrl,
647 .ctrlbit = (1 << 0),
648 },
649 .sources = &clkset_sclk_hdmi,
650 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
651};
652
653static struct clk *clkset_sclk_mixer_list[] = {
654 [0] = &clk_sclk_dac.clk,
655 [1] = &clk_sclk_hdmi.clk,
656};
657
658static struct clksrc_sources clkset_sclk_mixer = {
659 .sources = clkset_sclk_mixer_list,
660 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
661};
662
663static struct clksrc_clk clk_sclk_mixer = {
664 .clk = {
665 .name = "sclk_mixer",
666 .enable = s5pv210_clk_mask0_ctrl,
667 .ctrlbit = (1 << 1),
668 },
669 .sources = &clkset_sclk_mixer,
670 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
671};
672
673static struct clksrc_clk *sclk_tv[] = {
674 &clk_sclk_dac,
675 &clk_sclk_pixel,
676 &clk_sclk_hdmi,
677 &clk_sclk_mixer,
678};
679
680static struct clk *clkset_sclk_audio0_list[] = {
681 [0] = &clk_ext_xtal_mux,
682 [1] = &clk_pcmcdclk0,
683 [2] = &clk_sclk_hdmi27m,
684 [3] = &clk_sclk_usbphy0,
685 [4] = &clk_sclk_usbphy1,
686 [5] = &clk_sclk_hdmiphy,
687 [6] = &clk_mout_mpll.clk,
688 [7] = &clk_mout_epll.clk,
689 [8] = &clk_sclk_vpll.clk,
690};
691
692static struct clksrc_sources clkset_sclk_audio0 = {
693 .sources = clkset_sclk_audio0_list,
694 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
695};
696
697static struct clksrc_clk clk_sclk_audio0 = {
698 .clk = {
699 .name = "sclk_audio",
700 .devname = "soc-audio.0",
701 .enable = s5pv210_clk_mask0_ctrl,
702 .ctrlbit = (1 << 24),
703 },
704 .sources = &clkset_sclk_audio0,
705 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
706 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
707};
708
709static struct clk *clkset_sclk_audio1_list[] = {
710 [0] = &clk_ext_xtal_mux,
711 [1] = &clk_pcmcdclk1,
712 [2] = &clk_sclk_hdmi27m,
713 [3] = &clk_sclk_usbphy0,
714 [4] = &clk_sclk_usbphy1,
715 [5] = &clk_sclk_hdmiphy,
716 [6] = &clk_mout_mpll.clk,
717 [7] = &clk_mout_epll.clk,
718 [8] = &clk_sclk_vpll.clk,
719};
720
721static struct clksrc_sources clkset_sclk_audio1 = {
722 .sources = clkset_sclk_audio1_list,
723 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
724};
725
726static struct clksrc_clk clk_sclk_audio1 = {
727 .clk = {
728 .name = "sclk_audio",
729 .devname = "soc-audio.1",
730 .enable = s5pv210_clk_mask0_ctrl,
731 .ctrlbit = (1 << 25),
732 },
733 .sources = &clkset_sclk_audio1,
734 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
735 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
736};
737
738static struct clk *clkset_sclk_audio2_list[] = {
739 [0] = &clk_ext_xtal_mux,
740 [1] = &clk_pcmcdclk0,
741 [2] = &clk_sclk_hdmi27m,
742 [3] = &clk_sclk_usbphy0,
743 [4] = &clk_sclk_usbphy1,
744 [5] = &clk_sclk_hdmiphy,
745 [6] = &clk_mout_mpll.clk,
746 [7] = &clk_mout_epll.clk,
747 [8] = &clk_sclk_vpll.clk,
748};
749
750static struct clksrc_sources clkset_sclk_audio2 = {
751 .sources = clkset_sclk_audio2_list,
752 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
753};
754
755static struct clksrc_clk clk_sclk_audio2 = {
756 .clk = {
757 .name = "sclk_audio",
758 .devname = "soc-audio.2",
759 .enable = s5pv210_clk_mask0_ctrl,
760 .ctrlbit = (1 << 26),
761 },
762 .sources = &clkset_sclk_audio2,
763 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
764 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
765};
766
767static struct clk *clkset_sclk_spdif_list[] = {
768 [0] = &clk_sclk_audio0.clk,
769 [1] = &clk_sclk_audio1.clk,
770 [2] = &clk_sclk_audio2.clk,
771};
772
773static struct clksrc_sources clkset_sclk_spdif = {
774 .sources = clkset_sclk_spdif_list,
775 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
776};
777
778static struct clksrc_clk clk_sclk_spdif = {
779 .clk = {
780 .name = "sclk_spdif",
781 .enable = s5pv210_clk_mask0_ctrl,
782 .ctrlbit = (1 << 27),
783 .ops = &s5p_sclk_spdif_ops,
784 },
785 .sources = &clkset_sclk_spdif,
786 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
787};
788
789static struct clk *clkset_group2_list[] = {
790 [0] = &clk_ext_xtal_mux,
791 [1] = &clk_xusbxti,
792 [2] = &clk_sclk_hdmi27m,
793 [3] = &clk_sclk_usbphy0,
794 [4] = &clk_sclk_usbphy1,
795 [5] = &clk_sclk_hdmiphy,
796 [6] = &clk_mout_mpll.clk,
797 [7] = &clk_mout_epll.clk,
798 [8] = &clk_sclk_vpll.clk,
799};
800
801static struct clksrc_sources clkset_group2 = {
802 .sources = clkset_group2_list,
803 .nr_sources = ARRAY_SIZE(clkset_group2_list),
804};
805
806static struct clksrc_clk clksrcs[] = {
807 {
808 .clk = {
809 .name = "sclk_dmc",
810 },
811 .sources = &clkset_group1,
812 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
813 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
814 }, {
815 .clk = {
816 .name = "sclk_onenand",
817 },
818 .sources = &clkset_sclk_onenand,
819 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
820 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
821 }, {
822 .clk = {
823 .name = "sclk_fimc",
824 .devname = "s5pv210-fimc.0",
825 .enable = s5pv210_clk_mask1_ctrl,
826 .ctrlbit = (1 << 2),
827 },
828 .sources = &clkset_group2,
829 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
830 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
831 }, {
832 .clk = {
833 .name = "sclk_fimc",
834 .devname = "s5pv210-fimc.1",
835 .enable = s5pv210_clk_mask1_ctrl,
836 .ctrlbit = (1 << 3),
837 },
838 .sources = &clkset_group2,
839 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
840 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
841 }, {
842 .clk = {
843 .name = "sclk_fimc",
844 .devname = "s5pv210-fimc.2",
845 .enable = s5pv210_clk_mask1_ctrl,
846 .ctrlbit = (1 << 4),
847 },
848 .sources = &clkset_group2,
849 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
850 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
851 }, {
852 .clk = {
853 .name = "sclk_cam0",
854 .enable = s5pv210_clk_mask0_ctrl,
855 .ctrlbit = (1 << 3),
856 },
857 .sources = &clkset_group2,
858 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
859 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
860 }, {
861 .clk = {
862 .name = "sclk_cam1",
863 .enable = s5pv210_clk_mask0_ctrl,
864 .ctrlbit = (1 << 4),
865 },
866 .sources = &clkset_group2,
867 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
868 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
869 }, {
870 .clk = {
871 .name = "sclk_fimd",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 5),
874 },
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
878 }, {
879 .clk = {
880 .name = "sclk_mfc",
881 .devname = "s5p-mfc",
882 .enable = s5pv210_clk_ip0_ctrl,
883 .ctrlbit = (1 << 16),
884 },
885 .sources = &clkset_group1,
886 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
887 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
888 }, {
889 .clk = {
890 .name = "sclk_g2d",
891 .enable = s5pv210_clk_ip0_ctrl,
892 .ctrlbit = (1 << 12),
893 },
894 .sources = &clkset_group1,
895 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
896 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
897 }, {
898 .clk = {
899 .name = "sclk_g3d",
900 .enable = s5pv210_clk_ip0_ctrl,
901 .ctrlbit = (1 << 8),
902 },
903 .sources = &clkset_group1,
904 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
905 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
906 }, {
907 .clk = {
908 .name = "sclk_csis",
909 .enable = s5pv210_clk_mask0_ctrl,
910 .ctrlbit = (1 << 6),
911 },
912 .sources = &clkset_group2,
913 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
914 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
915 }, {
916 .clk = {
917 .name = "sclk_pwi",
918 .enable = s5pv210_clk_mask0_ctrl,
919 .ctrlbit = (1 << 29),
920 },
921 .sources = &clkset_group2,
922 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
923 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
924 }, {
925 .clk = {
926 .name = "sclk_pwm",
927 .enable = s5pv210_clk_mask0_ctrl,
928 .ctrlbit = (1 << 19),
929 },
930 .sources = &clkset_group2,
931 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
932 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
933 },
934};
935
936static struct clksrc_clk clk_sclk_uart0 = {
937 .clk = {
938 .name = "uclk1",
939 .devname = "s5pv210-uart.0",
940 .enable = s5pv210_clk_mask0_ctrl,
941 .ctrlbit = (1 << 12),
942 },
943 .sources = &clkset_uart,
944 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
945 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
946};
947
948static struct clksrc_clk clk_sclk_uart1 = {
949 .clk = {
950 .name = "uclk1",
951 .devname = "s5pv210-uart.1",
952 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 13),
954 },
955 .sources = &clkset_uart,
956 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
957 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
958};
959
960static struct clksrc_clk clk_sclk_uart2 = {
961 .clk = {
962 .name = "uclk1",
963 .devname = "s5pv210-uart.2",
964 .enable = s5pv210_clk_mask0_ctrl,
965 .ctrlbit = (1 << 14),
966 },
967 .sources = &clkset_uart,
968 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
969 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
970};
971
972static struct clksrc_clk clk_sclk_uart3 = {
973 .clk = {
974 .name = "uclk1",
975 .devname = "s5pv210-uart.3",
976 .enable = s5pv210_clk_mask0_ctrl,
977 .ctrlbit = (1 << 15),
978 },
979 .sources = &clkset_uart,
980 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
981 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
982};
983
984static struct clksrc_clk clk_sclk_mmc0 = {
985 .clk = {
986 .name = "sclk_mmc",
987 .devname = "s3c-sdhci.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 8),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
994};
995
996static struct clksrc_clk clk_sclk_mmc1 = {
997 .clk = {
998 .name = "sclk_mmc",
999 .devname = "s3c-sdhci.1",
1000 .enable = s5pv210_clk_mask0_ctrl,
1001 .ctrlbit = (1 << 9),
1002 },
1003 .sources = &clkset_group2,
1004 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1005 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1006};
1007
1008static struct clksrc_clk clk_sclk_mmc2 = {
1009 .clk = {
1010 .name = "sclk_mmc",
1011 .devname = "s3c-sdhci.2",
1012 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 10),
1014 },
1015 .sources = &clkset_group2,
1016 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1017 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1018};
1019
1020static struct clksrc_clk clk_sclk_mmc3 = {
1021 .clk = {
1022 .name = "sclk_mmc",
1023 .devname = "s3c-sdhci.3",
1024 .enable = s5pv210_clk_mask0_ctrl,
1025 .ctrlbit = (1 << 11),
1026 },
1027 .sources = &clkset_group2,
1028 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1029 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1030};
1031
1032static struct clksrc_clk clk_sclk_spi0 = {
1033 .clk = {
1034 .name = "sclk_spi",
1035 .devname = "s5pv210-spi.0",
1036 .enable = s5pv210_clk_mask0_ctrl,
1037 .ctrlbit = (1 << 16),
1038 },
1039 .sources = &clkset_group2,
1040 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1041 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1042 };
1043
1044static struct clksrc_clk clk_sclk_spi1 = {
1045 .clk = {
1046 .name = "sclk_spi",
1047 .devname = "s5pv210-spi.1",
1048 .enable = s5pv210_clk_mask0_ctrl,
1049 .ctrlbit = (1 << 17),
1050 },
1051 .sources = &clkset_group2,
1052 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1053 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1054 };
1055
1056
1057static struct clksrc_clk *clksrc_cdev[] = {
1058 &clk_sclk_uart0,
1059 &clk_sclk_uart1,
1060 &clk_sclk_uart2,
1061 &clk_sclk_uart3,
1062 &clk_sclk_mmc0,
1063 &clk_sclk_mmc1,
1064 &clk_sclk_mmc2,
1065 &clk_sclk_mmc3,
1066 &clk_sclk_spi0,
1067 &clk_sclk_spi1,
1068};
1069
1070static struct clk *clk_cdev[] = {
1071 &clk_hsmmc0,
1072 &clk_hsmmc1,
1073 &clk_hsmmc2,
1074 &clk_hsmmc3,
1075 &clk_pdma0,
1076 &clk_pdma1,
1077};
1078
1079/* Clock initialisation code */
1080static struct clksrc_clk *sysclks[] = {
1081 &clk_mout_apll,
1082 &clk_mout_epll,
1083 &clk_mout_mpll,
1084 &clk_armclk,
1085 &clk_hclk_msys,
1086 &clk_sclk_a2m,
1087 &clk_hclk_dsys,
1088 &clk_hclk_psys,
1089 &clk_pclk_msys,
1090 &clk_pclk_dsys,
1091 &clk_pclk_psys,
1092 &clk_vpllsrc,
1093 &clk_sclk_vpll,
1094 &clk_mout_dmc0,
1095 &clk_sclk_dmc0,
1096 &clk_sclk_audio0,
1097 &clk_sclk_audio1,
1098 &clk_sclk_audio2,
1099 &clk_sclk_spdif,
1100};
1101
1102static u32 epll_div[][6] = {
1103 { 48000000, 0, 48, 3, 3, 0 },
1104 { 96000000, 0, 48, 3, 2, 0 },
1105 { 144000000, 1, 72, 3, 2, 0 },
1106 { 192000000, 0, 48, 3, 1, 0 },
1107 { 288000000, 1, 72, 3, 1, 0 },
1108 { 32750000, 1, 65, 3, 4, 35127 },
1109 { 32768000, 1, 65, 3, 4, 35127 },
1110 { 45158400, 0, 45, 3, 3, 10355 },
1111 { 45000000, 0, 45, 3, 3, 10355 },
1112 { 45158000, 0, 45, 3, 3, 10355 },
1113 { 49125000, 0, 49, 3, 3, 9961 },
1114 { 49152000, 0, 49, 3, 3, 9961 },
1115 { 67737600, 1, 67, 3, 3, 48366 },
1116 { 67738000, 1, 67, 3, 3, 48366 },
1117 { 73800000, 1, 73, 3, 3, 47710 },
1118 { 73728000, 1, 73, 3, 3, 47710 },
1119 { 36000000, 1, 32, 3, 4, 0 },
1120 { 60000000, 1, 60, 3, 3, 0 },
1121 { 72000000, 1, 72, 3, 3, 0 },
1122 { 80000000, 1, 80, 3, 3, 0 },
1123 { 84000000, 0, 42, 3, 2, 0 },
1124 { 50000000, 0, 50, 3, 3, 0 },
1125};
1126
1127static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1128{
1129 unsigned int epll_con, epll_con_k;
1130 unsigned int i;
1131
1132 /* Return if nothing changed */
1133 if (clk->rate == rate)
1134 return 0;
1135
1136 epll_con = __raw_readl(S5P_EPLL_CON);
1137 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1138
1139 epll_con_k &= ~PLL46XX_KDIV_MASK;
1140 epll_con &= ~(1 << 27 |
1141 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1142 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1143 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1144
1145 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1146 if (epll_div[i][0] == rate) {
1147 epll_con_k |= epll_div[i][5] << 0;
1148 epll_con |= (epll_div[i][1] << 27 |
1149 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1150 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1151 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1152 break;
1153 }
1154 }
1155
1156 if (i == ARRAY_SIZE(epll_div)) {
1157 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1158 __func__);
1159 return -EINVAL;
1160 }
1161
1162 __raw_writel(epll_con, S5P_EPLL_CON);
1163 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1164
1165 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1166 clk->rate, rate);
1167
1168 clk->rate = rate;
1169
1170 return 0;
1171}
1172
1173static struct clk_ops s5pv210_epll_ops = {
1174 .set_rate = s5pv210_epll_set_rate,
1175 .get_rate = s5p_epll_get_rate,
1176};
1177
1178static u32 vpll_div[][5] = {
1179 { 54000000, 3, 53, 3, 0 },
1180 { 108000000, 3, 53, 2, 0 },
1181};
1182
1183static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1184{
1185 return clk->rate;
1186}
1187
1188static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1189{
1190 unsigned int vpll_con;
1191 unsigned int i;
1192
1193 /* Return if nothing changed */
1194 if (clk->rate == rate)
1195 return 0;
1196
1197 vpll_con = __raw_readl(S5P_VPLL_CON);
1198 vpll_con &= ~(0x1 << 27 | \
1199 PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
1200 PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
1201 PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1202
1203 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1204 if (vpll_div[i][0] == rate) {
1205 vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1206 vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1207 vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1208 vpll_con |= vpll_div[i][4] << 27;
1209 break;
1210 }
1211 }
1212
1213 if (i == ARRAY_SIZE(vpll_div)) {
1214 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1215 __func__);
1216 return -EINVAL;
1217 }
1218
1219 __raw_writel(vpll_con, S5P_VPLL_CON);
1220
1221 /* Wait for VPLL lock */
1222 while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1223 continue;
1224
1225 clk->rate = rate;
1226 return 0;
1227}
1228static struct clk_ops s5pv210_vpll_ops = {
1229 .get_rate = s5pv210_vpll_get_rate,
1230 .set_rate = s5pv210_vpll_set_rate,
1231};
1232
1233void __init_or_cpufreq s5pv210_setup_clocks(void)
1234{
1235 struct clk *xtal_clk;
1236 unsigned long vpllsrc;
1237 unsigned long armclk;
1238 unsigned long hclk_msys;
1239 unsigned long hclk_dsys;
1240 unsigned long hclk_psys;
1241 unsigned long pclk_msys;
1242 unsigned long pclk_dsys;
1243 unsigned long pclk_psys;
1244 unsigned long apll;
1245 unsigned long mpll;
1246 unsigned long epll;
1247 unsigned long vpll;
1248 unsigned int ptr;
1249 u32 clkdiv0, clkdiv1;
1250
1251 /* Set functions for clk_fout_epll */
1252 clk_fout_epll.enable = s5p_epll_enable;
1253 clk_fout_epll.ops = &s5pv210_epll_ops;
1254
1255 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1256
1257 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1258 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1259
1260 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1261 __func__, clkdiv0, clkdiv1);
1262
1263 xtal_clk = clk_get(NULL, "xtal");
1264 BUG_ON(IS_ERR(xtal_clk));
1265
1266 xtal = clk_get_rate(xtal_clk);
1267 clk_put(xtal_clk);
1268
1269 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1270
1271 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1272 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1273 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1274 __raw_readl(S5P_EPLL_CON1), pll_4600);
1275 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1276 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1277
1278 clk_fout_apll.ops = &clk_fout_apll_ops;
1279 clk_fout_mpll.rate = mpll;
1280 clk_fout_epll.rate = epll;
1281 clk_fout_vpll.ops = &s5pv210_vpll_ops;
1282 clk_fout_vpll.rate = vpll;
1283
1284 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1285 apll, mpll, epll, vpll);
1286
1287 armclk = clk_get_rate(&clk_armclk.clk);
1288 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1289 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1290 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1291 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1292 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1293 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1294
1295 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1296 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1297 armclk, hclk_msys, hclk_dsys, hclk_psys,
1298 pclk_msys, pclk_dsys, pclk_psys);
1299
1300 clk_f.rate = armclk;
1301 clk_h.rate = hclk_psys;
1302 clk_p.rate = pclk_psys;
1303
1304 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1305 s3c_set_clksrc(&clksrcs[ptr], true);
1306}
1307
1308static struct clk *clks[] __initdata = {
1309 &clk_sclk_hdmi27m,
1310 &clk_sclk_hdmiphy,
1311 &clk_sclk_usbphy0,
1312 &clk_sclk_usbphy1,
1313 &clk_pcmcdclk0,
1314 &clk_pcmcdclk1,
1315 &clk_pcmcdclk2,
1316};
1317
1318static struct clk_lookup s5pv210_clk_lookup[] = {
1319 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1320 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1321 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1322 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1323 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1328 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1329 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1330 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1331 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1332 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1333 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1334 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1335 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1336 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1337};
1338
1339void __init s5pv210_register_clocks(void)
1340{
1341 int ptr;
1342
1343 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1344
1345 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1346 s3c_register_clksrc(sysclks[ptr], 1);
1347
1348 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1349 s3c_register_clksrc(sclk_tv[ptr], 1);
1350
1351 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1352 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1353
1354 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1355 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1356
1357 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1358 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1359 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1360
1361 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1362 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1363 s3c_disable_clocks(clk_cdev[ptr], 1);
1364
1365}
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
deleted file mode 100644
index 7024dcd0e40a..000000000000
--- a/arch/arm/mach-s5pv210/common.c
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for S5PV210
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/device.h>
22#include <clocksource/samsung_pwm.h>
23#include <linux/platform_device.h>
24#include <linux/sched.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial_core.h>
27#include <linux/serial_s3c.h>
28
29#include <asm/proc-fns.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <mach/map.h>
35#include <mach/regs-clock.h>
36
37#include <plat/cpu.h>
38#include <plat/clock.h>
39#include <plat/devs.h>
40#include <plat/sdhci.h>
41#include <plat/adc-core.h>
42#include <plat/ata-core.h>
43#include <plat/fb-core.h>
44#include <plat/fimc-core.h>
45#include <plat/iic-core.h>
46#include <plat/keypad-core.h>
47#include <plat/pwm-core.h>
48#include <plat/tv-core.h>
49#include <plat/spi-core.h>
50
51#include "common.h"
52
53static const char name_s5pv210[] = "S5PV210/S5PC110";
54
55static struct cpu_table cpu_ids[] __initdata = {
56 {
57 .idcode = S5PV210_CPU_ID,
58 .idmask = S5PV210_CPU_MASK,
59 .map_io = s5pv210_map_io,
60 .init_clocks = s5pv210_init_clocks,
61 .init_uarts = s5pv210_init_uarts,
62 .init = s5pv210_init,
63 .name = name_s5pv210,
64 },
65};
66
67/* Initial IO mappings */
68
69static struct map_desc s5pv210_iodesc[] __initdata = {
70 {
71 .virtual = (unsigned long)S5P_VA_CHIPID,
72 .pfn = __phys_to_pfn(S5PV210_PA_CHIPID),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = (unsigned long)S3C_VA_SYS,
77 .pfn = __phys_to_pfn(S5PV210_PA_SYSCON),
78 .length = SZ_64K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S3C_VA_TIMER,
82 .pfn = __phys_to_pfn(S5PV210_PA_TIMER),
83 .length = SZ_16K,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)S3C_VA_WATCHDOG,
87 .pfn = __phys_to_pfn(S5PV210_PA_WATCHDOG),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)S5P_VA_SROMC,
92 .pfn = __phys_to_pfn(S5PV210_PA_SROMC),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S5P_VA_SYSTIMER,
97 .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = (unsigned long)S5P_VA_GPIO,
102 .pfn = __phys_to_pfn(S5PV210_PA_GPIO),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (unsigned long)VA_VIC0,
107 .pfn = __phys_to_pfn(S5PV210_PA_VIC0),
108 .length = SZ_16K,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (unsigned long)VA_VIC1,
112 .pfn = __phys_to_pfn(S5PV210_PA_VIC1),
113 .length = SZ_16K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)VA_VIC2,
117 .pfn = __phys_to_pfn(S5PV210_PA_VIC2),
118 .length = SZ_16K,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (unsigned long)VA_VIC3,
122 .pfn = __phys_to_pfn(S5PV210_PA_VIC3),
123 .length = SZ_16K,
124 .type = MT_DEVICE,
125 }, {
126 .virtual = (unsigned long)S3C_VA_UART,
127 .pfn = __phys_to_pfn(S3C_PA_UART),
128 .length = SZ_512K,
129 .type = MT_DEVICE,
130 }, {
131 .virtual = (unsigned long)S5P_VA_DMC0,
132 .pfn = __phys_to_pfn(S5PV210_PA_DMC0),
133 .length = SZ_4K,
134 .type = MT_DEVICE,
135 }, {
136 .virtual = (unsigned long)S5P_VA_DMC1,
137 .pfn = __phys_to_pfn(S5PV210_PA_DMC1),
138 .length = SZ_4K,
139 .type = MT_DEVICE,
140 }, {
141 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
142 .pfn =__phys_to_pfn(S5PV210_PA_HSPHY),
143 .length = SZ_4K,
144 .type = MT_DEVICE,
145 }
146};
147
148void s5pv210_restart(enum reboot_mode mode, const char *cmd)
149{
150 __raw_writel(0x1, S5P_SWRESET);
151}
152
153static struct samsung_pwm_variant s5pv210_pwm_variant = {
154 .bits = 32,
155 .div_base = 0,
156 .has_tint_cstat = true,
157 .tclk_mask = (1 << 5),
158};
159
160void __init samsung_set_timer_source(unsigned int event, unsigned int source)
161{
162 s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
163 s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
164}
165
166void __init samsung_timer_init(void)
167{
168 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
169 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
170 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
171 };
172
173 samsung_pwm_clocksource_init(S3C_VA_TIMER,
174 timer_irqs, &s5pv210_pwm_variant);
175}
176
177/*
178 * s5pv210_map_io
179 *
180 * register the standard cpu IO areas
181 */
182
183void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
184{
185 /* initialize the io descriptors we need for initialization */
186 iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
187 if (mach_desc)
188 iotable_init(mach_desc, size);
189
190 /* detect cpu id and rev. */
191 s5p_init_cpu(S5P_VA_CHIPID);
192
193 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
194
195 samsung_pwm_set_platdata(&s5pv210_pwm_variant);
196}
197
198void __init s5pv210_map_io(void)
199{
200 /* initialise device information early */
201 s5pv210_default_sdhci0();
202 s5pv210_default_sdhci1();
203 s5pv210_default_sdhci2();
204 s5pv210_default_sdhci3();
205
206 s3c_adc_setname("samsung-adc-v3");
207
208 s3c_cfcon_setname("s5pv210-pata");
209
210 s3c_fimc_setname(0, "s5pv210-fimc");
211 s3c_fimc_setname(1, "s5pv210-fimc");
212 s3c_fimc_setname(2, "s5pv210-fimc");
213
214 /* the i2c devices are directly compatible with s3c2440 */
215 s3c_i2c0_setname("s3c2440-i2c");
216 s3c_i2c1_setname("s3c2440-i2c");
217 s3c_i2c2_setname("s3c2440-i2c");
218
219 s3c_fb_setname("s5pv210-fb");
220
221 /* Use s5pv210-keypad instead of samsung-keypad */
222 samsung_keypad_setname("s5pv210-keypad");
223
224 /* setup TV devices */
225 s5p_hdmi_setname("s5pv210-hdmi");
226
227 s3c64xx_spi_setname("s5pv210-spi");
228}
229
230void __init s5pv210_init_clocks(int xtal)
231{
232 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
233
234 s3c24xx_register_baseclocks(xtal);
235 s5p_register_clocks(xtal);
236 s5pv210_register_clocks();
237 s5pv210_setup_clocks();
238}
239
240void __init s5pv210_init_irq(void)
241{
242 u32 vic[4]; /* S5PV210 supports 4 VIC */
243
244 /* All the VICs are fully populated. */
245 vic[0] = ~0;
246 vic[1] = ~0;
247 vic[2] = ~0;
248 vic[3] = ~0;
249
250 s5p_init_irq(vic, ARRAY_SIZE(vic));
251}
252
253struct bus_type s5pv210_subsys = {
254 .name = "s5pv210-core",
255 .dev_name = "s5pv210-core",
256};
257
258static struct device s5pv210_dev = {
259 .bus = &s5pv210_subsys,
260};
261
262static int __init s5pv210_core_init(void)
263{
264 return subsys_system_register(&s5pv210_subsys, NULL);
265}
266core_initcall(s5pv210_core_init);
267
268int __init s5pv210_init(void)
269{
270 printk(KERN_INFO "S5PV210: Initializing architecture\n");
271 return device_register(&s5pv210_dev);
272}
273
274/* uart registration process */
275
276void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
277{
278 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
279}
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index fe1beb54e548..2ad387c1ecf0 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,19 +12,12 @@
12#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H 12#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
13#define __ARCH_ARM_MACH_S5PV210_COMMON_H 13#define __ARCH_ARM_MACH_S5PV210_COMMON_H
14 14
15#include <linux/reboot.h> 15#ifdef CONFIG_PM_SLEEP
16 16u32 exynos_get_eint_wake_mask(void);
17void s5pv210_init_io(struct map_desc *mach_desc, int size); 17void s5pv210_cpu_resume(void);
18void s5pv210_init_irq(void); 18void s5pv210_pm_init(void);
19 19#else
20void s5pv210_register_clocks(void); 20static inline void s5pv210_pm_init(void) {}
21void s5pv210_setup_clocks(void); 21#endif
22
23void s5pv210_restart(enum reboot_mode mode, const char *cmd);
24
25extern int s5pv210_init(void);
26extern void s5pv210_map_io(void);
27extern void s5pv210_init_clocks(int xtal);
28extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29 22
30#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ 23#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
deleted file mode 100644
index 2d67361ef431..000000000000
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ /dev/null
@@ -1,246 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22#define S5PV210_AUDSS_INT_MEM (0xC0000000)
23
24static int s5pv210_cfg_i2s(struct platform_device *pdev)
25{
26 /* configure GPIO for i2s port */
27 switch (pdev->id) {
28 case 0:
29 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
30 break;
31 case 1:
32 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
33 break;
34 case 2:
35 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
36 break;
37 default:
38 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
39 return -EINVAL;
40 }
41
42 return 0;
43}
44
45static struct s3c_audio_pdata i2sv5_pdata = {
46 .cfg_gpio = s5pv210_cfg_i2s,
47 .type = {
48 .i2s = {
49 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
50 | QUIRK_NEED_RSTCLR,
51 .idma_addr = S5PV210_AUDSS_INT_MEM,
52 },
53 },
54};
55
56static struct resource s5pv210_iis0_resource[] = {
57 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256),
58 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
59 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
60 [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
61};
62
63struct platform_device s5pv210_device_iis0 = {
64 .name = "samsung-i2s",
65 .id = 0,
66 .num_resources = ARRAY_SIZE(s5pv210_iis0_resource),
67 .resource = s5pv210_iis0_resource,
68 .dev = {
69 .platform_data = &i2sv5_pdata,
70 },
71};
72
73static struct s3c_audio_pdata i2sv3_pdata = {
74 .cfg_gpio = s5pv210_cfg_i2s,
75};
76
77static struct resource s5pv210_iis1_resource[] = {
78 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256),
79 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
80 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
81};
82
83struct platform_device s5pv210_device_iis1 = {
84 .name = "samsung-i2s",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(s5pv210_iis1_resource),
87 .resource = s5pv210_iis1_resource,
88 .dev = {
89 .platform_data = &i2sv3_pdata,
90 },
91};
92
93static struct resource s5pv210_iis2_resource[] = {
94 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256),
95 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
96 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
97};
98
99struct platform_device s5pv210_device_iis2 = {
100 .name = "samsung-i2s",
101 .id = 2,
102 .num_resources = ARRAY_SIZE(s5pv210_iis2_resource),
103 .resource = s5pv210_iis2_resource,
104 .dev = {
105 .platform_data = &i2sv3_pdata,
106 },
107};
108
109/* PCM Controller platform_devices */
110
111static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
112{
113 switch (pdev->id) {
114 case 0:
115 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
116 break;
117 case 1:
118 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
119 break;
120 case 2:
121 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
122 break;
123 default:
124 printk(KERN_DEBUG "Invalid PCM Controller number!");
125 return -EINVAL;
126 }
127
128 return 0;
129}
130
131static struct s3c_audio_pdata s3c_pcm_pdata = {
132 .cfg_gpio = s5pv210_pcm_cfg_gpio,
133};
134
135static struct resource s5pv210_pcm0_resource[] = {
136 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256),
137 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
138 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
139};
140
141struct platform_device s5pv210_device_pcm0 = {
142 .name = "samsung-pcm",
143 .id = 0,
144 .num_resources = ARRAY_SIZE(s5pv210_pcm0_resource),
145 .resource = s5pv210_pcm0_resource,
146 .dev = {
147 .platform_data = &s3c_pcm_pdata,
148 },
149};
150
151static struct resource s5pv210_pcm1_resource[] = {
152 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256),
153 [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
154 [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
155};
156
157struct platform_device s5pv210_device_pcm1 = {
158 .name = "samsung-pcm",
159 .id = 1,
160 .num_resources = ARRAY_SIZE(s5pv210_pcm1_resource),
161 .resource = s5pv210_pcm1_resource,
162 .dev = {
163 .platform_data = &s3c_pcm_pdata,
164 },
165};
166
167static struct resource s5pv210_pcm2_resource[] = {
168 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256),
169 [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
170 [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
171};
172
173struct platform_device s5pv210_device_pcm2 = {
174 .name = "samsung-pcm",
175 .id = 2,
176 .num_resources = ARRAY_SIZE(s5pv210_pcm2_resource),
177 .resource = s5pv210_pcm2_resource,
178 .dev = {
179 .platform_data = &s3c_pcm_pdata,
180 },
181};
182
183/* AC97 Controller platform devices */
184
185static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
186{
187 return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
188}
189
190static struct resource s5pv210_ac97_resource[] = {
191 [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256),
192 [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
193 [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
194 [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
195 [4] = DEFINE_RES_IRQ(IRQ_AC97),
196};
197
198static struct s3c_audio_pdata s3c_ac97_pdata = {
199 .cfg_gpio = s5pv210_ac97_cfg_gpio,
200};
201
202static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32);
203
204struct platform_device s5pv210_device_ac97 = {
205 .name = "samsung-ac97",
206 .id = -1,
207 .num_resources = ARRAY_SIZE(s5pv210_ac97_resource),
208 .resource = s5pv210_ac97_resource,
209 .dev = {
210 .platform_data = &s3c_ac97_pdata,
211 .dma_mask = &s5pv210_ac97_dmamask,
212 .coherent_dma_mask = DMA_BIT_MASK(32),
213 },
214};
215
216/* S/PDIF Controller platform_device */
217
218static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
219{
220 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
221
222 return 0;
223}
224
225static struct resource s5pv210_spdif_resource[] = {
226 [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256),
227 [1] = DEFINE_RES_DMA(DMACH_SPDIF),
228};
229
230static struct s3c_audio_pdata samsung_spdif_pdata = {
231 .cfg_gpio = s5pv210_spdif_cfg_gpio,
232};
233
234static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
235
236struct platform_device s5pv210_device_spdif = {
237 .name = "samsung-spdif",
238 .id = -1,
239 .num_resources = ARRAY_SIZE(s5pv210_spdif_resource),
240 .resource = s5pv210_spdif_resource,
241 .dev = {
242 .platform_data = &samsung_spdif_pdata,
243 .dma_mask = &s5pv210_spdif_dmamask,
244 .coherent_dma_mask = DMA_BIT_MASK(32),
245 },
246};
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
deleted file mode 100644
index b8337e248b09..000000000000
--- a/arch/arm/mach-s5pv210/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29#include <plat/devs.h>
30#include <plat/irqs.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <mach/dma.h>
35
36static u8 pdma0_peri[] = {
37 DMACH_UART0_RX,
38 DMACH_UART0_TX,
39 DMACH_UART1_RX,
40 DMACH_UART1_TX,
41 DMACH_UART2_RX,
42 DMACH_UART2_TX,
43 DMACH_UART3_RX,
44 DMACH_UART3_TX,
45 DMACH_MAX,
46 DMACH_I2S0_RX,
47 DMACH_I2S0_TX,
48 DMACH_I2S0S_TX,
49 DMACH_I2S1_RX,
50 DMACH_I2S1_TX,
51 DMACH_MAX,
52 DMACH_MAX,
53 DMACH_SPI0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI1_RX,
56 DMACH_SPI1_TX,
57 DMACH_MAX,
58 DMACH_MAX,
59 DMACH_AC97_MICIN,
60 DMACH_AC97_PCMIN,
61 DMACH_AC97_PCMOUT,
62 DMACH_MAX,
63 DMACH_PWM,
64 DMACH_SPDIF,
65};
66
67static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
68 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
69 .peri_id = pdma0_peri,
70};
71
72static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
73 S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
74
75static u8 pdma1_peri[] = {
76 DMACH_UART0_RX,
77 DMACH_UART0_TX,
78 DMACH_UART1_RX,
79 DMACH_UART1_TX,
80 DMACH_UART2_RX,
81 DMACH_UART2_TX,
82 DMACH_UART3_RX,
83 DMACH_UART3_TX,
84 DMACH_MAX,
85 DMACH_I2S0_RX,
86 DMACH_I2S0_TX,
87 DMACH_I2S0S_TX,
88 DMACH_I2S1_RX,
89 DMACH_I2S1_TX,
90 DMACH_I2S2_RX,
91 DMACH_I2S2_TX,
92 DMACH_SPI0_RX,
93 DMACH_SPI0_TX,
94 DMACH_SPI1_RX,
95 DMACH_SPI1_TX,
96 DMACH_MAX,
97 DMACH_MAX,
98 DMACH_PCM0_RX,
99 DMACH_PCM0_TX,
100 DMACH_PCM1_RX,
101 DMACH_PCM1_TX,
102 DMACH_MSM_REQ0,
103 DMACH_MSM_REQ1,
104 DMACH_MSM_REQ2,
105 DMACH_MSM_REQ3,
106 DMACH_PCM2_RX,
107 DMACH_PCM2_TX,
108};
109
110static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
111 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
112 .peri_id = pdma1_peri,
113};
114
115static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
116 S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
117
118static int __init s5pv210_dma_init(void)
119{
120 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
121 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
122 amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
123
124 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
125 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
126 amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
127
128 return 0;
129}
130arch_initcall(s5pv210_dma_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
deleted file mode 100644
index 30b511a580aa..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <linux/serial_s3c.h>
16#include <mach/map.h>
17
18 /* note, for the boot process to work we have to keep the UART
19 * virtual address aligned to an 1MiB boundary for the L1
20 * mapping the head code makes. We keep the UART virtual address
21 * aligned and add in the offset when we load the value here.
22 */
23
24 .macro addruart, rp, rv, tmp
25 ldr \rp, = S3C_PA_UART
26 ldr \rv, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
30#endif
31 .endm
32
33#define fifo_full fifo_full_s5pv210
34#define fifo_level fifo_level_s5pv210
35
36/* include the reset of the code which will do the work, we're only
37 * compiling for a single cpu processor type so the default of s3c2440
38 * will be fine with us.
39 */
40
41#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
deleted file mode 100644
index 6c8b903c02e4..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
17
18/* GPIO bank sizes */
19#define S5PV210_GPIO_A0_NR (8)
20#define S5PV210_GPIO_A1_NR (4)
21#define S5PV210_GPIO_B_NR (8)
22#define S5PV210_GPIO_C0_NR (5)
23#define S5PV210_GPIO_C1_NR (5)
24#define S5PV210_GPIO_D0_NR (4)
25#define S5PV210_GPIO_D1_NR (6)
26#define S5PV210_GPIO_E0_NR (8)
27#define S5PV210_GPIO_E1_NR (5)
28#define S5PV210_GPIO_F0_NR (8)
29#define S5PV210_GPIO_F1_NR (8)
30#define S5PV210_GPIO_F2_NR (8)
31#define S5PV210_GPIO_F3_NR (6)
32#define S5PV210_GPIO_G0_NR (7)
33#define S5PV210_GPIO_G1_NR (7)
34#define S5PV210_GPIO_G2_NR (7)
35#define S5PV210_GPIO_G3_NR (7)
36#define S5PV210_GPIO_H0_NR (8)
37#define S5PV210_GPIO_H1_NR (8)
38#define S5PV210_GPIO_H2_NR (8)
39#define S5PV210_GPIO_H3_NR (8)
40#define S5PV210_GPIO_I_NR (7)
41#define S5PV210_GPIO_J0_NR (8)
42#define S5PV210_GPIO_J1_NR (6)
43#define S5PV210_GPIO_J2_NR (8)
44#define S5PV210_GPIO_J3_NR (8)
45#define S5PV210_GPIO_J4_NR (5)
46
47#define S5PV210_GPIO_MP01_NR (8)
48#define S5PV210_GPIO_MP02_NR (4)
49#define S5PV210_GPIO_MP03_NR (8)
50#define S5PV210_GPIO_MP04_NR (8)
51#define S5PV210_GPIO_MP05_NR (8)
52
53/* GPIO bank numbers */
54
55/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
56 * space for debugging purposes so that any accidental
57 * change from one gpio bank to another can be caught.
58*/
59
60#define S5PV210_GPIO_NEXT(__gpio) \
61 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
62
63enum s5p_gpio_number {
64 S5PV210_GPIO_A0_START = 0,
65 S5PV210_GPIO_A1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A0),
66 S5PV210_GPIO_B_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A1),
67 S5PV210_GPIO_C0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_B),
68 S5PV210_GPIO_C1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C0),
69 S5PV210_GPIO_D0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C1),
70 S5PV210_GPIO_D1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D0),
71 S5PV210_GPIO_E0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D1),
72 S5PV210_GPIO_E1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E0),
73 S5PV210_GPIO_F0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E1),
74 S5PV210_GPIO_F1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F0),
75 S5PV210_GPIO_F2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F1),
76 S5PV210_GPIO_F3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F2),
77 S5PV210_GPIO_G0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F3),
78 S5PV210_GPIO_G1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G0),
79 S5PV210_GPIO_G2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G1),
80 S5PV210_GPIO_G3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G2),
81 S5PV210_GPIO_H0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G3),
82 S5PV210_GPIO_H1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H0),
83 S5PV210_GPIO_H2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H1),
84 S5PV210_GPIO_H3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H2),
85 S5PV210_GPIO_I_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H3),
86 S5PV210_GPIO_J0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_I),
87 S5PV210_GPIO_J1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J0),
88 S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
89 S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
90 S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
91 S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
92 S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
93 S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
94 S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
95 S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
96};
97
98/* S5PV210 GPIO number definitions */
99#define S5PV210_GPA0(_nr) (S5PV210_GPIO_A0_START + (_nr))
100#define S5PV210_GPA1(_nr) (S5PV210_GPIO_A1_START + (_nr))
101#define S5PV210_GPB(_nr) (S5PV210_GPIO_B_START + (_nr))
102#define S5PV210_GPC0(_nr) (S5PV210_GPIO_C0_START + (_nr))
103#define S5PV210_GPC1(_nr) (S5PV210_GPIO_C1_START + (_nr))
104#define S5PV210_GPD0(_nr) (S5PV210_GPIO_D0_START + (_nr))
105#define S5PV210_GPD1(_nr) (S5PV210_GPIO_D1_START + (_nr))
106#define S5PV210_GPE0(_nr) (S5PV210_GPIO_E0_START + (_nr))
107#define S5PV210_GPE1(_nr) (S5PV210_GPIO_E1_START + (_nr))
108#define S5PV210_GPF0(_nr) (S5PV210_GPIO_F0_START + (_nr))
109#define S5PV210_GPF1(_nr) (S5PV210_GPIO_F1_START + (_nr))
110#define S5PV210_GPF2(_nr) (S5PV210_GPIO_F2_START + (_nr))
111#define S5PV210_GPF3(_nr) (S5PV210_GPIO_F3_START + (_nr))
112#define S5PV210_GPG0(_nr) (S5PV210_GPIO_G0_START + (_nr))
113#define S5PV210_GPG1(_nr) (S5PV210_GPIO_G1_START + (_nr))
114#define S5PV210_GPG2(_nr) (S5PV210_GPIO_G2_START + (_nr))
115#define S5PV210_GPG3(_nr) (S5PV210_GPIO_G3_START + (_nr))
116#define S5PV210_GPH0(_nr) (S5PV210_GPIO_H0_START + (_nr))
117#define S5PV210_GPH1(_nr) (S5PV210_GPIO_H1_START + (_nr))
118#define S5PV210_GPH2(_nr) (S5PV210_GPIO_H2_START + (_nr))
119#define S5PV210_GPH3(_nr) (S5PV210_GPIO_H3_START + (_nr))
120#define S5PV210_GPI(_nr) (S5PV210_GPIO_I_START + (_nr))
121#define S5PV210_GPJ0(_nr) (S5PV210_GPIO_J0_START + (_nr))
122#define S5PV210_GPJ1(_nr) (S5PV210_GPIO_J1_START + (_nr))
123#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
124#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
125#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
126#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
127#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
128#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
129#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr))
130#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr))
131
132/* the end of the S5PV210 specific gpios */
133#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
134#define S3C_GPIO_END S5PV210_GPIO_END
135
136/* define the number of gpios we need to the one after the MP05() range */
137#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \
138 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
139
140#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/hardware.h b/arch/arm/mach-s5pv210/include/mach/hardware.h
deleted file mode 100644
index fada7a392d09..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
deleted file mode 100644
index 5e0de3a31f3d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0: System, DMA, Timer */
19
20#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
21#define IRQ_BATF S5P_IRQ_VIC0(17)
22#define IRQ_MDMA S5P_IRQ_VIC0(18)
23#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
24#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
25#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
26#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
27#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
28#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
29#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
30#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
31#define IRQ_WDT S5P_IRQ_VIC0(27)
32#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
33#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
34#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
35#define IRQ_FIMC3 S5P_IRQ_VIC0(31)
36
37/* VIC1: ARM, Power, Memory, Connectivity, Storage */
38
39#define IRQ_PMU S5P_IRQ_VIC1(0)
40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
43#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
44#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
45#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
46#define IRQ_ONENAND S5P_IRQ_VIC1(7)
47#define IRQ_NFC S5P_IRQ_VIC1(8)
48#define IRQ_CFCON S5P_IRQ_VIC1(9)
49#define IRQ_UART0 S5P_IRQ_VIC1(10)
50#define IRQ_UART1 S5P_IRQ_VIC1(11)
51#define IRQ_UART2 S5P_IRQ_VIC1(12)
52#define IRQ_UART3 S5P_IRQ_VIC1(13)
53#define IRQ_IIC S5P_IRQ_VIC1(14)
54#define IRQ_SPI0 S5P_IRQ_VIC1(15)
55#define IRQ_SPI1 S5P_IRQ_VIC1(16)
56#define IRQ_SPI2 S5P_IRQ_VIC1(17)
57#define IRQ_IRDA S5P_IRQ_VIC1(18)
58#define IRQ_IIC2 S5P_IRQ_VIC1(19)
59#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
60#define IRQ_HSIRX S5P_IRQ_VIC1(21)
61#define IRQ_HSITX S5P_IRQ_VIC1(22)
62#define IRQ_UHOST S5P_IRQ_VIC1(23)
63#define IRQ_OTG S5P_IRQ_VIC1(24)
64#define IRQ_MSM S5P_IRQ_VIC1(25)
65#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
66#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
67#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
68#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29)
69#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
70#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
71
72/* VIC2: Multimedia, Audio, Security */
73
74#define IRQ_LCD0 S5P_IRQ_VIC2(0)
75#define IRQ_LCD1 S5P_IRQ_VIC2(1)
76#define IRQ_LCD2 S5P_IRQ_VIC2(2)
77#define IRQ_LCD3 S5P_IRQ_VIC2(3)
78#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
79#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
80#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
81#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
82#define IRQ_JPEG S5P_IRQ_VIC2(8)
83#define IRQ_2D S5P_IRQ_VIC2(9)
84#define IRQ_3D S5P_IRQ_VIC2(10)
85#define IRQ_MIXER S5P_IRQ_VIC2(11)
86#define IRQ_HDMI S5P_IRQ_VIC2(12)
87#define IRQ_IIC1 S5P_IRQ_VIC2(13)
88#define IRQ_MFC S5P_IRQ_VIC2(14)
89#define IRQ_SDO S5P_IRQ_VIC2(15)
90#define IRQ_I2S0 S5P_IRQ_VIC2(16)
91#define IRQ_I2S1 S5P_IRQ_VIC2(17)
92#define IRQ_I2S2 S5P_IRQ_VIC2(18)
93#define IRQ_AC97 S5P_IRQ_VIC2(19)
94#define IRQ_PCM0 S5P_IRQ_VIC2(20)
95#define IRQ_PCM1 S5P_IRQ_VIC2(21)
96#define IRQ_SPDIF S5P_IRQ_VIC2(22)
97#define IRQ_ADC S5P_IRQ_VIC2(23)
98#define IRQ_PENDN S5P_IRQ_VIC2(24)
99#define IRQ_TC IRQ_PENDN
100#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
101#define IRQ_CG S5P_IRQ_VIC2(26)
102#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
103#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
104#define IRQ_PCM2 S5P_IRQ_VIC2(29)
105#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
106#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
107
108/* VIC3: Etc */
109
110#define IRQ_IPC S5P_IRQ_VIC3(0)
111#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
112#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
113#define IRQ_CEC S5P_IRQ_VIC3(3)
114#define IRQ_TSI S5P_IRQ_VIC3(4)
115#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
116#define IRQ_MDNIE1 S5P_IRQ_VIC3(6)
117#define IRQ_MDNIE2 S5P_IRQ_VIC3(7)
118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
120
121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
123
124/* GPIO interrupt */
125#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
126#define S5P_GPIOINT_GROUP_MAXNR 22
127
128/* Set the default NR_IRQS */
129#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
130
131/* Compatibility */
132#define IRQ_LCD_FIFO IRQ_LCD0
133#define IRQ_LCD_VSYNC IRQ_LCD1
134#define IRQ_LCD_SYSTEM IRQ_LCD2
135#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS
136
137#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
deleted file mode 100644
index 763929aca52d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5PV210_PA_SDRAM 0x20000000
20
21#define S5PV210_PA_SROM_BANK5 0xA8000000
22
23#define S5PC110_PA_ONENAND 0xB0000000
24#define S5PC110_PA_ONENAND_DMA 0xB0600000
25
26#define S5PV210_PA_CHIPID 0xE0000000
27
28#define S5PV210_PA_SYSCON 0xE0100000
29
30#define S5PV210_PA_GPIO 0xE0200000
31
32#define S5PV210_PA_SPDIF 0xE1100000
33
34#define S5PV210_PA_SPI0 0xE1300000
35#define S5PV210_PA_SPI1 0xE1400000
36
37#define S5PV210_PA_KEYPAD 0xE1600000
38
39#define S5PV210_PA_ADC 0xE1700000
40
41#define S5PV210_PA_IIC0 0xE1800000
42#define S5PV210_PA_IIC1 0xFAB00000
43#define S5PV210_PA_IIC2 0xE1A00000
44
45#define S5PV210_PA_AC97 0xE2200000
46
47#define S5PV210_PA_PCM0 0xE2300000
48#define S5PV210_PA_PCM1 0xE1200000
49#define S5PV210_PA_PCM2 0xE2B00000
50
51#define S5PV210_PA_TIMER 0xE2500000
52#define S5PV210_PA_SYSTIMER 0xE2600000
53#define S5PV210_PA_WATCHDOG 0xE2700000
54#define S5PV210_PA_RTC 0xE2800000
55
56#define S5PV210_PA_UART 0xE2900000
57
58#define S5PV210_PA_SROMC 0xE8000000
59
60#define S5PV210_PA_CFCON 0xE8200000
61
62#define S5PV210_PA_MFC 0xF1700000
63
64#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
65
66#define S5PV210_PA_HSOTG 0xEC000000
67#define S5PV210_PA_HSPHY 0xEC100000
68
69#define S5PV210_PA_IIS0 0xEEE30000
70#define S5PV210_PA_IIS1 0xE2100000
71#define S5PV210_PA_IIS2 0xE2A00000
72
73#define S5PV210_PA_DMC0 0xF0000000
74#define S5PV210_PA_DMC1 0xF1400000
75
76#define S5PV210_PA_VIC0 0xF2000000
77#define S5PV210_PA_VIC1 0xF2100000
78#define S5PV210_PA_VIC2 0xF2200000
79#define S5PV210_PA_VIC3 0xF2300000
80
81#define S5PV210_PA_FB 0xF8000000
82
83#define S5PV210_PA_MDMA 0xFA200000
84#define S5PV210_PA_PDMA0 0xE0900000
85#define S5PV210_PA_PDMA1 0xE0A00000
86
87#define S5PV210_PA_MIPI_CSIS 0xFA600000
88
89#define S5PV210_PA_FIMC0 0xFB200000
90#define S5PV210_PA_FIMC1 0xFB300000
91#define S5PV210_PA_FIMC2 0xFB400000
92
93#define S5PV210_PA_JPEG 0xFB600000
94
95#define S5PV210_PA_SDO 0xF9000000
96#define S5PV210_PA_VP 0xF9100000
97#define S5PV210_PA_MIXER 0xF9200000
98#define S5PV210_PA_HDMI 0xFA100000
99#define S5PV210_PA_IIC_HDMIPHY 0xFA900000
100
101/* Compatibiltiy Defines */
102
103#define S3C_PA_FB S5PV210_PA_FB
104#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
105#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
106#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
107#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
108#define S3C_PA_IIC S5PV210_PA_IIC0
109#define S3C_PA_IIC1 S5PV210_PA_IIC1
110#define S3C_PA_IIC2 S5PV210_PA_IIC2
111#define S3C_PA_RTC S5PV210_PA_RTC
112#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
113#define S3C_PA_WDT S5PV210_PA_WATCHDOG
114#define S3C_PA_SPI0 S5PV210_PA_SPI0
115#define S3C_PA_SPI1 S5PV210_PA_SPI1
116
117#define S5P_PA_CHIPID S5PV210_PA_CHIPID
118#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
119#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
120#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
121#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
122#define S5P_PA_MFC S5PV210_PA_MFC
123#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY
124
125#define S5P_PA_SDO S5PV210_PA_SDO
126#define S5P_PA_VP S5PV210_PA_VP
127#define S5P_PA_MIXER S5PV210_PA_MIXER
128#define S5P_PA_HDMI S5PV210_PA_HDMI
129
130#define S5P_PA_ONENAND S5PC110_PA_ONENAND
131#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
132#define S5P_PA_SDRAM S5PV210_PA_SDRAM
133#define S5P_PA_SROMC S5PV210_PA_SROMC
134#define S5P_PA_SYSCON S5PV210_PA_SYSCON
135#define S5P_PA_TIMER S5PV210_PA_TIMER
136
137#define S5P_PA_JPEG S5PV210_PA_JPEG
138
139#define SAMSUNG_PA_ADC S5PV210_PA_ADC
140#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
141#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
142#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER
143
144/* UART */
145
146#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
147
148#define S3C_PA_UART S5PV210_PA_UART
149
150#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
151#define S5P_PA_UART0 S5P_PA_UART(0)
152#define S5P_PA_UART1 S5P_PA_UART(1)
153#define S5P_PA_UART2 S5P_PA_UART(2)
154#define S5P_PA_UART3 S5P_PA_UART(3)
155
156#define S5P_SZ_UART SZ_256
157
158#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
deleted file mode 100644
index d584fac9156b..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/memory.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16/*
17 * Sparsemem support
18 * Physical memory can be located from 0x20000000 to 0x7fffffff,
19 * so MAX_PHYSMEM_BITS is 31.
20 */
21
22#define MAX_PHYSMEM_BITS 31
23#define SECTION_SIZE_BITS 28
24
25#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
deleted file mode 100644
index eba8aea63ed8..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18static inline void s3c_pm_debug_init_uart(void)
19{
20 /* nothing here yet */
21}
22
23static inline void s3c_pm_arch_prepare_irqs(void)
24{
25 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
26 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
27}
28
29static inline void s3c_pm_arch_stop_clocks(void)
30{
31 /* nothing here yet */
32}
33
34static inline void s3c_pm_arch_show_resume_irqs(void)
35{
36 /* nothing here yet */
37}
38
39static inline void s3c_pm_arch_update_uart(void __iomem *regs,
40 struct pm_uart_save *save)
41{
42 /* nothing here yet */
43}
44
45static inline void s3c_pm_restored_gpios(void) { }
46static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index e345584d4c34..b14ffcd7f6cc 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -13,7 +13,7 @@
13#ifndef __ASM_ARCH_REGS_CLOCK_H 13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__ 14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15 15
16#include <mach/map.h> 16#include <plat/map-base.h>
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19 19
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
deleted file mode 100644
index de0c89976078..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV210 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00)
19#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4))
20
21#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
22#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
23
24#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00)
25#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4))
26
27#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
28#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
29
30#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
31
32#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
33
34#define EINT_MODE S3C_GPIO_SFN(0xf)
35
36#define EINT_GPIO_0(x) S5PV210_GPH0(x)
37#define EINT_GPIO_1(x) S5PV210_GPH1(x)
38#define EINT_GPIO_2(x) S5PV210_GPH2(x)
39#define EINT_GPIO_3(x) S5PV210_GPH3(x)
40
41#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
deleted file mode 100644
index d8bc1e6c7aaa..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
deleted file mode 100644
index cc37edacda26..000000000000
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ /dev/null
@@ -1,687 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-aquila.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/fb.h>
17#include <linux/i2c.h>
18#include <linux/i2c-gpio.h>
19#include <linux/mfd/max8998.h>
20#include <linux/mfd/wm8994/pdata.h>
21#include <linux/regulator/fixed.h>
22#include <linux/gpio_keys.h>
23#include <linux/input.h>
24#include <linux/gpio.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/setup.h>
29#include <asm/mach-types.h>
30
31#include <video/samsung_fimd.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34
35#include <plat/gpio-cfg.h>
36#include <plat/devs.h>
37#include <plat/cpu.h>
38#include <plat/fb.h>
39#include <plat/fimc-core.h>
40#include <plat/sdhci.h>
41#include <plat/samsung-time.h>
42
43#include "common.h"
44
45/* Following are default values for UCON, ULCON and UFCON UART registers */
46#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
47 S3C2410_UCON_RXILEVEL | \
48 S3C2410_UCON_TXIRQMODE | \
49 S3C2410_UCON_RXIRQMODE | \
50 S3C2410_UCON_RXFIFO_TOI | \
51 S3C2443_UCON_RXERR_IRQEN)
52
53#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
54
55#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
56
57static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
58 [0] = {
59 .hwport = 0,
60 .flags = 0,
61 .ucon = AQUILA_UCON_DEFAULT,
62 .ulcon = AQUILA_ULCON_DEFAULT,
63 /*
64 * Actually UART0 can support 256 bytes fifo, but aquila board
65 * supports 128 bytes fifo because of initial chip bug
66 */
67 .ufcon = AQUILA_UFCON_DEFAULT |
68 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
69 },
70 [1] = {
71 .hwport = 1,
72 .flags = 0,
73 .ucon = AQUILA_UCON_DEFAULT,
74 .ulcon = AQUILA_ULCON_DEFAULT,
75 .ufcon = AQUILA_UFCON_DEFAULT |
76 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
77 },
78 [2] = {
79 .hwport = 2,
80 .flags = 0,
81 .ucon = AQUILA_UCON_DEFAULT,
82 .ulcon = AQUILA_ULCON_DEFAULT,
83 .ufcon = AQUILA_UFCON_DEFAULT |
84 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
85 },
86 [3] = {
87 .hwport = 3,
88 .flags = 0,
89 .ucon = AQUILA_UCON_DEFAULT,
90 .ulcon = AQUILA_ULCON_DEFAULT,
91 .ufcon = AQUILA_UFCON_DEFAULT |
92 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
93 },
94};
95
96/* Frame Buffer */
97static struct s3c_fb_pd_win aquila_fb_win0 = {
98 .max_bpp = 32,
99 .default_bpp = 16,
100 .xres = 480,
101 .yres = 800,
102};
103
104static struct s3c_fb_pd_win aquila_fb_win1 = {
105 .max_bpp = 32,
106 .default_bpp = 16,
107 .xres = 480,
108 .yres = 800,
109};
110
111static struct fb_videomode aquila_lcd_timing = {
112 .left_margin = 16,
113 .right_margin = 16,
114 .upper_margin = 3,
115 .lower_margin = 28,
116 .hsync_len = 2,
117 .vsync_len = 2,
118 .xres = 480,
119 .yres = 800,
120};
121
122static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
123 .win[0] = &aquila_fb_win0,
124 .win[1] = &aquila_fb_win1,
125 .vtiming = &aquila_lcd_timing,
126 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
127 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
128 VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
129 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
130};
131
132/* MAX8998 regulators */
133#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
134
135static struct regulator_init_data aquila_ldo2_data = {
136 .constraints = {
137 .name = "VALIVE_1.1V",
138 .min_uV = 1100000,
139 .max_uV = 1100000,
140 .apply_uV = 1,
141 .always_on = 1,
142 .state_mem = {
143 .enabled = 1,
144 },
145 },
146};
147
148static struct regulator_init_data aquila_ldo3_data = {
149 .constraints = {
150 .name = "VUSB+MIPI_1.1V",
151 .min_uV = 1100000,
152 .max_uV = 1100000,
153 .apply_uV = 1,
154 .always_on = 1,
155 },
156};
157
158static struct regulator_init_data aquila_ldo4_data = {
159 .constraints = {
160 .name = "VDAC_3.3V",
161 .min_uV = 3300000,
162 .max_uV = 3300000,
163 .apply_uV = 1,
164 },
165};
166
167static struct regulator_init_data aquila_ldo5_data = {
168 .constraints = {
169 .name = "VTF_2.8V",
170 .min_uV = 2800000,
171 .max_uV = 2800000,
172 .apply_uV = 1,
173 },
174};
175
176static struct regulator_init_data aquila_ldo6_data = {
177 .constraints = {
178 .name = "VCC_3.3V",
179 .min_uV = 3300000,
180 .max_uV = 3300000,
181 .apply_uV = 1,
182 },
183};
184
185static struct regulator_init_data aquila_ldo7_data = {
186 .constraints = {
187 .name = "VCC_3.0V",
188 .min_uV = 3000000,
189 .max_uV = 3000000,
190 .apply_uV = 1,
191 .boot_on = 1,
192 .always_on = 1,
193 },
194};
195
196static struct regulator_init_data aquila_ldo8_data = {
197 .constraints = {
198 .name = "VUSB+VADC_3.3V",
199 .min_uV = 3300000,
200 .max_uV = 3300000,
201 .apply_uV = 1,
202 .always_on = 1,
203 },
204};
205
206static struct regulator_init_data aquila_ldo9_data = {
207 .constraints = {
208 .name = "VCC+VCAM_2.8V",
209 .min_uV = 2800000,
210 .max_uV = 2800000,
211 .apply_uV = 1,
212 .always_on = 1,
213 },
214};
215
216static struct regulator_init_data aquila_ldo10_data = {
217 .constraints = {
218 .name = "VPLL_1.1V",
219 .min_uV = 1100000,
220 .max_uV = 1100000,
221 .apply_uV = 1,
222 .boot_on = 1,
223 },
224};
225
226static struct regulator_init_data aquila_ldo11_data = {
227 .constraints = {
228 .name = "CAM_IO_2.8V",
229 .min_uV = 2800000,
230 .max_uV = 2800000,
231 .apply_uV = 1,
232 .always_on = 1,
233 },
234};
235
236static struct regulator_init_data aquila_ldo12_data = {
237 .constraints = {
238 .name = "CAM_ISP_1.2V",
239 .min_uV = 1200000,
240 .max_uV = 1200000,
241 .apply_uV = 1,
242 .always_on = 1,
243 },
244};
245
246static struct regulator_init_data aquila_ldo13_data = {
247 .constraints = {
248 .name = "CAM_A_2.8V",
249 .min_uV = 2800000,
250 .max_uV = 2800000,
251 .apply_uV = 1,
252 .always_on = 1,
253 },
254};
255
256static struct regulator_init_data aquila_ldo14_data = {
257 .constraints = {
258 .name = "CAM_CIF_1.8V",
259 .min_uV = 1800000,
260 .max_uV = 1800000,
261 .apply_uV = 1,
262 .always_on = 1,
263 },
264};
265
266static struct regulator_init_data aquila_ldo15_data = {
267 .constraints = {
268 .name = "CAM_AF_3.3V",
269 .min_uV = 3300000,
270 .max_uV = 3300000,
271 .apply_uV = 1,
272 .always_on = 1,
273 },
274};
275
276static struct regulator_init_data aquila_ldo16_data = {
277 .constraints = {
278 .name = "VMIPI_1.8V",
279 .min_uV = 1800000,
280 .max_uV = 1800000,
281 .apply_uV = 1,
282 .always_on = 1,
283 },
284};
285
286static struct regulator_init_data aquila_ldo17_data = {
287 .constraints = {
288 .name = "CAM_8M_1.8V",
289 .min_uV = 1800000,
290 .max_uV = 1800000,
291 .apply_uV = 1,
292 .always_on = 1,
293 },
294};
295
296/* BUCK */
297static struct regulator_consumer_supply buck1_consumer =
298 REGULATOR_SUPPLY("vddarm", NULL);
299
300static struct regulator_consumer_supply buck2_consumer =
301 REGULATOR_SUPPLY("vddint", NULL);
302
303static struct regulator_init_data aquila_buck1_data = {
304 .constraints = {
305 .name = "VARM_1.2V",
306 .min_uV = 1200000,
307 .max_uV = 1200000,
308 .apply_uV = 1,
309 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
310 REGULATOR_CHANGE_STATUS,
311 },
312 .num_consumer_supplies = 1,
313 .consumer_supplies = &buck1_consumer,
314};
315
316static struct regulator_init_data aquila_buck2_data = {
317 .constraints = {
318 .name = "VINT_1.2V",
319 .min_uV = 1200000,
320 .max_uV = 1200000,
321 .apply_uV = 1,
322 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
323 REGULATOR_CHANGE_STATUS,
324 },
325 .num_consumer_supplies = 1,
326 .consumer_supplies = &buck2_consumer,
327};
328
329static struct regulator_init_data aquila_buck3_data = {
330 .constraints = {
331 .name = "VCC_1.8V",
332 .min_uV = 1800000,
333 .max_uV = 1800000,
334 .apply_uV = 1,
335 .state_mem = {
336 .enabled = 1,
337 },
338 },
339};
340
341static struct regulator_init_data aquila_buck4_data = {
342 .constraints = {
343 .name = "CAM_CORE_1.2V",
344 .min_uV = 1200000,
345 .max_uV = 1200000,
346 .apply_uV = 1,
347 .always_on = 1,
348 },
349};
350
351static struct max8998_regulator_data aquila_regulators[] = {
352 { MAX8998_LDO2, &aquila_ldo2_data },
353 { MAX8998_LDO3, &aquila_ldo3_data },
354 { MAX8998_LDO4, &aquila_ldo4_data },
355 { MAX8998_LDO5, &aquila_ldo5_data },
356 { MAX8998_LDO6, &aquila_ldo6_data },
357 { MAX8998_LDO7, &aquila_ldo7_data },
358 { MAX8998_LDO8, &aquila_ldo8_data },
359 { MAX8998_LDO9, &aquila_ldo9_data },
360 { MAX8998_LDO10, &aquila_ldo10_data },
361 { MAX8998_LDO11, &aquila_ldo11_data },
362 { MAX8998_LDO12, &aquila_ldo12_data },
363 { MAX8998_LDO13, &aquila_ldo13_data },
364 { MAX8998_LDO14, &aquila_ldo14_data },
365 { MAX8998_LDO15, &aquila_ldo15_data },
366 { MAX8998_LDO16, &aquila_ldo16_data },
367 { MAX8998_LDO17, &aquila_ldo17_data },
368 { MAX8998_BUCK1, &aquila_buck1_data },
369 { MAX8998_BUCK2, &aquila_buck2_data },
370 { MAX8998_BUCK3, &aquila_buck3_data },
371 { MAX8998_BUCK4, &aquila_buck4_data },
372};
373
374static struct max8998_platform_data aquila_max8998_pdata = {
375 .num_regulators = ARRAY_SIZE(aquila_regulators),
376 .regulators = aquila_regulators,
377 .buck1_set1 = S5PV210_GPH0(3),
378 .buck1_set2 = S5PV210_GPH0(4),
379 .buck2_set3 = S5PV210_GPH0(5),
380 .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
381 .buck2_voltage = { 1200000, 1200000 },
382};
383#endif
384
385static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
386 REGULATOR_SUPPLY("DBVDD", "5-001a"),
387 REGULATOR_SUPPLY("AVDD2", "5-001a"),
388 REGULATOR_SUPPLY("CPVDD", "5-001a"),
389};
390
391static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
392 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
393 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
394};
395
396static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
397 .constraints = {
398 .always_on = 1,
399 },
400 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
401 .consumer_supplies = wm8994_fixed_voltage0_supplies,
402};
403
404static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
405 .constraints = {
406 .always_on = 1,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
409 .consumer_supplies = wm8994_fixed_voltage1_supplies,
410};
411
412static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
413 .supply_name = "VCC_1.8V_PDA",
414 .microvolts = 1800000,
415 .gpio = -EINVAL,
416 .init_data = &wm8994_fixed_voltage0_init_data,
417};
418
419static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
420 .supply_name = "V_BAT",
421 .microvolts = 3700000,
422 .gpio = -EINVAL,
423 .init_data = &wm8994_fixed_voltage1_init_data,
424};
425
426static struct platform_device wm8994_fixed_voltage0 = {
427 .name = "reg-fixed-voltage",
428 .id = 0,
429 .dev = {
430 .platform_data = &wm8994_fixed_voltage0_config,
431 },
432};
433
434static struct platform_device wm8994_fixed_voltage1 = {
435 .name = "reg-fixed-voltage",
436 .id = 1,
437 .dev = {
438 .platform_data = &wm8994_fixed_voltage1_config,
439 },
440};
441
442static struct regulator_consumer_supply wm8994_avdd1_supply =
443 REGULATOR_SUPPLY("AVDD1", "5-001a");
444
445static struct regulator_consumer_supply wm8994_dcvdd_supply =
446 REGULATOR_SUPPLY("DCVDD", "5-001a");
447
448static struct regulator_init_data wm8994_ldo1_data = {
449 .constraints = {
450 .name = "AVDD1_3.0V",
451 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
452 },
453 .num_consumer_supplies = 1,
454 .consumer_supplies = &wm8994_avdd1_supply,
455};
456
457static struct regulator_init_data wm8994_ldo2_data = {
458 .constraints = {
459 .name = "DCVDD_1.0V",
460 },
461 .num_consumer_supplies = 1,
462 .consumer_supplies = &wm8994_dcvdd_supply,
463};
464
465static struct wm8994_pdata wm8994_platform_data = {
466 /* configure gpio1 function: 0x0001(Logic level input/output) */
467 .gpio_defaults[0] = 0x0001,
468 /* configure gpio3/4/5/7 function for AIF2 voice */
469 .gpio_defaults[2] = 0x8100,
470 .gpio_defaults[3] = 0x8100,
471 .gpio_defaults[4] = 0x8100,
472 .gpio_defaults[6] = 0x0100,
473 /* configure gpio8/9/10/11 function for AIF3 BT */
474 .gpio_defaults[7] = 0x8100,
475 .gpio_defaults[8] = 0x0100,
476 .gpio_defaults[9] = 0x0100,
477 .gpio_defaults[10] = 0x0100,
478 .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
479 .ldo[1] = { 0, &wm8994_ldo2_data },
480};
481
482/* GPIO I2C PMIC */
483#define AP_I2C_GPIO_PMIC_BUS_4 4
484static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
485 .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
486 .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
487};
488
489static struct platform_device aquila_i2c_gpio_pmic = {
490 .name = "i2c-gpio",
491 .id = AP_I2C_GPIO_PMIC_BUS_4,
492 .dev = {
493 .platform_data = &aquila_i2c_gpio_pmic_data,
494 },
495};
496
497static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
498#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
499 {
500 /* 0xCC when SRAD = 0 */
501 I2C_BOARD_INFO("max8998", 0xCC >> 1),
502 .platform_data = &aquila_max8998_pdata,
503 },
504#endif
505};
506
507/* GPIO I2C AP 1.8V */
508#define AP_I2C_GPIO_BUS_5 5
509static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
510 .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
511 .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
512};
513
514static struct platform_device aquila_i2c_gpio5 = {
515 .name = "i2c-gpio",
516 .id = AP_I2C_GPIO_BUS_5,
517 .dev = {
518 .platform_data = &aquila_i2c_gpio5_data,
519 },
520};
521
522static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
523 {
524 /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
525 I2C_BOARD_INFO("wm8994", 0x1a),
526 .platform_data = &wm8994_platform_data,
527 },
528};
529
530/* PMIC Power button */
531static struct gpio_keys_button aquila_gpio_keys_table[] = {
532 {
533 .code = KEY_POWER,
534 .gpio = S5PV210_GPH2(6),
535 .desc = "gpio-keys: KEY_POWER",
536 .type = EV_KEY,
537 .active_low = 1,
538 .wakeup = 1,
539 .debounce_interval = 1,
540 },
541};
542
543static struct gpio_keys_platform_data aquila_gpio_keys_data = {
544 .buttons = aquila_gpio_keys_table,
545 .nbuttons = ARRAY_SIZE(aquila_gpio_keys_table),
546};
547
548static struct platform_device aquila_device_gpiokeys = {
549 .name = "gpio-keys",
550 .dev = {
551 .platform_data = &aquila_gpio_keys_data,
552 },
553};
554
555static void __init aquila_pmic_init(void)
556{
557 /* AP_PMIC_IRQ: EINT7 */
558 s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
559 s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
560
561 /* nPower: EINT22 */
562 s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
563 s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
564}
565
566/* MoviNAND */
567static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
568 .max_width = 4,
569 .cd_type = S3C_SDHCI_CD_PERMANENT,
570};
571
572/* Wireless LAN */
573static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
574 .max_width = 4,
575 .cd_type = S3C_SDHCI_CD_EXTERNAL,
576 /* ext_cd_{init,cleanup} callbacks will be added later */
577};
578
579/* External Flash */
580#define AQUILA_EXT_FLASH_EN S5PV210_MP05(4)
581#define AQUILA_EXT_FLASH_CD S5PV210_GPH3(4)
582static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
583 .max_width = 4,
584 .cd_type = S3C_SDHCI_CD_GPIO,
585 .ext_cd_gpio = AQUILA_EXT_FLASH_CD,
586 .ext_cd_gpio_invert = 1,
587};
588
589static void aquila_setup_sdhci(void)
590{
591 gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
592
593 s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
594 s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
595 s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
596};
597
598/* Audio device */
599static struct platform_device aquila_device_audio = {
600 .name = "smdk-audio",
601 .id = -1,
602};
603
604static struct platform_device *aquila_devices[] __initdata = {
605 &aquila_i2c_gpio_pmic,
606 &aquila_i2c_gpio5,
607 &aquila_device_gpiokeys,
608 &aquila_device_audio,
609 &s3c_device_fb,
610 &s5p_device_onenand,
611 &s3c_device_hsmmc0,
612 &s3c_device_hsmmc1,
613 &s3c_device_hsmmc2,
614 &s5p_device_fimc0,
615 &s5p_device_fimc1,
616 &s5p_device_fimc2,
617 &s5p_device_fimc_md,
618 &s5pv210_device_iis0,
619 &wm8994_fixed_voltage0,
620 &wm8994_fixed_voltage1,
621};
622
623static void __init aquila_sound_init(void)
624{
625 unsigned int gpio;
626
627 /* CODEC_XTAL_EN
628 *
629 * The Aquila board have a oscillator which provide main clock
630 * to WM8994 codec. The oscillator provide 24MHz clock to WM8994
631 * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
632 * */
633 gpio = S5PV210_GPH3(2); /* XEINT_26 */
634 gpio_request(gpio, "CODEC_XTAL_EN");
635 s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
636 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
637
638 /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
639 * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
640 * because it needs 24MHz clock to operate WM8994 codec.
641 */
642 __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
643}
644
645static void __init aquila_map_io(void)
646{
647 s5pv210_init_io(NULL, 0);
648 s3c24xx_init_clocks(24000000);
649 s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
650 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
651}
652
653static void __init aquila_machine_init(void)
654{
655 /* PMIC */
656 aquila_pmic_init();
657 i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
658 ARRAY_SIZE(i2c_gpio_pmic_devs));
659 /* SDHCI */
660 aquila_setup_sdhci();
661
662 s3c_fimc_setname(0, "s5p-fimc");
663 s3c_fimc_setname(1, "s5p-fimc");
664 s3c_fimc_setname(2, "s5p-fimc");
665
666 /* SOUND */
667 aquila_sound_init();
668 i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
669 ARRAY_SIZE(i2c_gpio5_devs));
670
671 /* FB */
672 s3c_fb_set_platdata(&aquila_lcd_pdata);
673
674 platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
675}
676
677MACHINE_START(AQUILA, "Aquila")
678 /* Maintainers:
679 Marek Szyprowski <m.szyprowski@samsung.com>
680 Kyungmin Park <kyungmin.park@samsung.com> */
681 .atag_offset = 0x100,
682 .init_irq = s5pv210_init_irq,
683 .map_io = aquila_map_io,
684 .init_machine = aquila_machine_init,
685 .init_time = samsung_timer_init,
686 .restart = s5pv210_restart,
687MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
deleted file mode 100644
index c1ce921c4088..000000000000
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ /dev/null
@@ -1,916 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-goni.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/fb.h>
17#include <linux/i2c.h>
18#include <linux/i2c-gpio.h>
19#include <linux/i2c/atmel_mxt_ts.h>
20#include <linux/mfd/max8998.h>
21#include <linux/mfd/wm8994/pdata.h>
22#include <linux/regulator/fixed.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_gpio.h>
25#include <linux/lcd.h>
26#include <linux/gpio_keys.h>
27#include <linux/input.h>
28#include <linux/gpio.h>
29#include <linux/mmc/host.h>
30#include <linux/interrupt.h>
31#include <linux/platform_data/s3c-hsotg.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/setup.h>
36#include <asm/mach-types.h>
37
38#include <video/samsung_fimd.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41
42#include <plat/gpio-cfg.h>
43#include <plat/devs.h>
44#include <plat/cpu.h>
45#include <plat/fb.h>
46#include <linux/platform_data/i2c-s3c2410.h>
47#include <plat/keypad.h>
48#include <plat/sdhci.h>
49#include <plat/clock.h>
50#include <plat/samsung-time.h>
51#include <plat/mfc.h>
52
53#include "common.h"
54
55/* Following are default values for UCON, ULCON and UFCON UART registers */
56#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
57 S3C2410_UCON_RXILEVEL | \
58 S3C2410_UCON_TXIRQMODE | \
59 S3C2410_UCON_RXIRQMODE | \
60 S3C2410_UCON_RXFIFO_TOI | \
61 S3C2443_UCON_RXERR_IRQEN)
62
63#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
64
65#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
66
67static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
68 [0] = {
69 .hwport = 0,
70 .flags = 0,
71 .ucon = GONI_UCON_DEFAULT,
72 .ulcon = GONI_ULCON_DEFAULT,
73 .ufcon = GONI_UFCON_DEFAULT |
74 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
75 },
76 [1] = {
77 .hwport = 1,
78 .flags = 0,
79 .ucon = GONI_UCON_DEFAULT,
80 .ulcon = GONI_ULCON_DEFAULT,
81 .ufcon = GONI_UFCON_DEFAULT |
82 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
83 },
84 [2] = {
85 .hwport = 2,
86 .flags = 0,
87 .ucon = GONI_UCON_DEFAULT,
88 .ulcon = GONI_ULCON_DEFAULT,
89 .ufcon = GONI_UFCON_DEFAULT |
90 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
91 },
92 [3] = {
93 .hwport = 3,
94 .flags = 0,
95 .ucon = GONI_UCON_DEFAULT,
96 .ulcon = GONI_ULCON_DEFAULT,
97 .ufcon = GONI_UFCON_DEFAULT |
98 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
99 },
100};
101
102/* Frame Buffer */
103static struct s3c_fb_pd_win goni_fb_win0 = {
104 .max_bpp = 32,
105 .default_bpp = 16,
106 .xres = 480,
107 .yres = 800,
108 .virtual_x = 480,
109 .virtual_y = 2 * 800,
110};
111
112static struct fb_videomode goni_lcd_timing = {
113 .left_margin = 16,
114 .right_margin = 16,
115 .upper_margin = 2,
116 .lower_margin = 28,
117 .hsync_len = 2,
118 .vsync_len = 1,
119 .xres = 480,
120 .yres = 800,
121 .refresh = 55,
122};
123
124static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
125 .win[0] = &goni_fb_win0,
126 .vtiming = &goni_lcd_timing,
127 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
128 VIDCON0_CLKSEL_LCD,
129 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
130 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
131 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
132};
133
134static int lcd_power_on(struct lcd_device *ld, int enable)
135{
136 return 1;
137}
138
139static int reset_lcd(struct lcd_device *ld)
140{
141 static unsigned int first = 1;
142 int reset_gpio = -1;
143
144 reset_gpio = S5PV210_MP05(5);
145
146 if (first) {
147 gpio_request(reset_gpio, "MLCD_RST");
148 first = 0;
149 }
150
151 gpio_direction_output(reset_gpio, 1);
152 return 1;
153}
154
155static struct lcd_platform_data goni_lcd_platform_data = {
156 .reset = reset_lcd,
157 .power_on = lcd_power_on,
158 .lcd_enabled = 0,
159 .reset_delay = 120, /* 120ms */
160 .power_on_delay = 25, /* 25ms */
161 .power_off_delay = 200, /* 200ms */
162};
163
164#define LCD_BUS_NUM 3
165static struct spi_board_info spi_board_info[] __initdata = {
166 {
167 .modalias = "s6e63m0",
168 .platform_data = &goni_lcd_platform_data,
169 .max_speed_hz = 1200000,
170 .bus_num = LCD_BUS_NUM,
171 .chip_select = 0,
172 .mode = SPI_MODE_3,
173 .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
174 },
175};
176
177static struct spi_gpio_platform_data lcd_spi_gpio_data = {
178 .sck = S5PV210_MP04(1), /* DISPLAY_CLK */
179 .mosi = S5PV210_MP04(3), /* DISPLAY_SI */
180 .miso = SPI_GPIO_NO_MISO,
181 .num_chipselect = 1,
182};
183
184static struct platform_device goni_spi_gpio = {
185 .name = "spi_gpio",
186 .id = LCD_BUS_NUM,
187 .dev = {
188 .parent = &s3c_device_fb.dev,
189 .platform_data = &lcd_spi_gpio_data,
190 },
191};
192
193/* KEYPAD */
194static uint32_t keymap[] __initdata = {
195 /* KEY(row, col, keycode) */
196 KEY(0, 1, KEY_MENU), /* Send */
197 KEY(0, 2, KEY_BACK), /* End */
198 KEY(1, 1, KEY_CONFIG), /* Half shot */
199 KEY(1, 2, KEY_VOLUMEUP),
200 KEY(2, 1, KEY_CAMERA), /* Full shot */
201 KEY(2, 2, KEY_VOLUMEDOWN),
202};
203
204static struct matrix_keymap_data keymap_data __initdata = {
205 .keymap = keymap,
206 .keymap_size = ARRAY_SIZE(keymap),
207};
208
209static struct samsung_keypad_platdata keypad_data __initdata = {
210 .keymap_data = &keymap_data,
211 .rows = 3,
212 .cols = 3,
213};
214
215/* Radio */
216static struct i2c_board_info i2c1_devs[] __initdata = {
217 {
218 I2C_BOARD_INFO("si470x", 0x10),
219 },
220};
221
222static void __init goni_radio_init(void)
223{
224 int gpio;
225
226 gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */
227 gpio_request(gpio, "FM_INT");
228 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
229 i2c1_devs[0].irq = gpio_to_irq(gpio);
230
231 gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
232 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
233}
234
235/* TSP */
236static struct mxt_platform_data qt602240_platform_data = {
237 .irqflags = IRQF_TRIGGER_FALLING,
238};
239
240static struct s3c2410_platform_i2c i2c2_data __initdata = {
241 .flags = 0,
242 .bus_num = 2,
243 .slave_addr = 0x10,
244 .frequency = 400 * 1000,
245 .sda_delay = 100,
246};
247
248static struct i2c_board_info i2c2_devs[] __initdata = {
249 {
250 I2C_BOARD_INFO("qt602240_ts", 0x4a),
251 .platform_data = &qt602240_platform_data,
252 },
253};
254
255static void __init goni_tsp_init(void)
256{
257 int gpio;
258
259 gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
260 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
261 gpio_export(gpio, 0);
262
263 gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
264 gpio_request(gpio, "TSP_INT");
265
266 s5p_register_gpio_interrupt(gpio);
267 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
268 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
269 i2c2_devs[0].irq = gpio_to_irq(gpio);
270}
271
272/* USB OTG */
273static struct s3c_hsotg_plat goni_hsotg_pdata;
274
275/* MAX8998 regulators */
276#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
277
278static struct regulator_consumer_supply goni_ldo3_consumers[] = {
279 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
280};
281
282static struct regulator_consumer_supply goni_ldo5_consumers[] = {
283 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
284};
285
286static struct regulator_consumer_supply goni_ldo8_consumers[] = {
287 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
288 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
289};
290
291static struct regulator_consumer_supply goni_ldo11_consumers[] = {
292 REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
293};
294
295static struct regulator_consumer_supply goni_ldo13_consumers[] = {
296 REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
297};
298
299static struct regulator_consumer_supply goni_ldo14_consumers[] = {
300 REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
301};
302
303static struct regulator_init_data goni_ldo2_data = {
304 .constraints = {
305 .name = "VALIVE_1.1V",
306 .min_uV = 1100000,
307 .max_uV = 1100000,
308 .apply_uV = 1,
309 .always_on = 1,
310 .state_mem = {
311 .enabled = 1,
312 },
313 },
314};
315
316static struct regulator_init_data goni_ldo3_data = {
317 .constraints = {
318 .name = "VUSB+MIPI_1.1V",
319 .min_uV = 1100000,
320 .max_uV = 1100000,
321 .apply_uV = 1,
322 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
323 },
324 .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
325 .consumer_supplies = goni_ldo3_consumers,
326};
327
328static struct regulator_init_data goni_ldo4_data = {
329 .constraints = {
330 .name = "VDAC_3.3V",
331 .min_uV = 3300000,
332 .max_uV = 3300000,
333 .apply_uV = 1,
334 },
335};
336
337static struct regulator_init_data goni_ldo5_data = {
338 .constraints = {
339 .name = "VTF_2.8V",
340 .min_uV = 2800000,
341 .max_uV = 2800000,
342 .apply_uV = 1,
343 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
344 },
345 .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
346 .consumer_supplies = goni_ldo5_consumers,
347};
348
349static struct regulator_init_data goni_ldo6_data = {
350 .constraints = {
351 .name = "VCC_3.3V",
352 .min_uV = 3300000,
353 .max_uV = 3300000,
354 .apply_uV = 1,
355 },
356};
357
358static struct regulator_init_data goni_ldo7_data = {
359 .constraints = {
360 .name = "VLCD_1.8V",
361 .min_uV = 1800000,
362 .max_uV = 1800000,
363 .apply_uV = 1,
364 .always_on = 1,
365 },
366};
367
368static struct regulator_init_data goni_ldo8_data = {
369 .constraints = {
370 .name = "VUSB+VADC_3.3V",
371 .min_uV = 3300000,
372 .max_uV = 3300000,
373 .apply_uV = 1,
374 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
375 },
376 .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
377 .consumer_supplies = goni_ldo8_consumers,
378};
379
380static struct regulator_init_data goni_ldo9_data = {
381 .constraints = {
382 .name = "VCC+VCAM_2.8V",
383 .min_uV = 2800000,
384 .max_uV = 2800000,
385 .apply_uV = 1,
386 },
387};
388
389static struct regulator_init_data goni_ldo10_data = {
390 .constraints = {
391 .name = "VPLL_1.1V",
392 .min_uV = 1100000,
393 .max_uV = 1100000,
394 .apply_uV = 1,
395 .boot_on = 1,
396 },
397};
398
399static struct regulator_init_data goni_ldo11_data = {
400 .constraints = {
401 .name = "CAM_IO_2.8V",
402 .min_uV = 2800000,
403 .max_uV = 2800000,
404 .apply_uV = 1,
405 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
406 },
407 .num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers),
408 .consumer_supplies = goni_ldo11_consumers,
409};
410
411static struct regulator_init_data goni_ldo12_data = {
412 .constraints = {
413 .name = "CAM_ISP_1.2V",
414 .min_uV = 1200000,
415 .max_uV = 1200000,
416 .apply_uV = 1,
417 },
418};
419
420static struct regulator_init_data goni_ldo13_data = {
421 .constraints = {
422 .name = "CAM_A_2.8V",
423 .min_uV = 2800000,
424 .max_uV = 2800000,
425 .apply_uV = 1,
426 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
427 },
428 .num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers),
429 .consumer_supplies = goni_ldo13_consumers,
430};
431
432static struct regulator_init_data goni_ldo14_data = {
433 .constraints = {
434 .name = "CAM_CIF_1.8V",
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
439 },
440 .num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers),
441 .consumer_supplies = goni_ldo14_consumers,
442};
443
444static struct regulator_init_data goni_ldo15_data = {
445 .constraints = {
446 .name = "CAM_AF_3.3V",
447 .min_uV = 3300000,
448 .max_uV = 3300000,
449 .apply_uV = 1,
450 },
451};
452
453static struct regulator_init_data goni_ldo16_data = {
454 .constraints = {
455 .name = "VMIPI_1.8V",
456 .min_uV = 1800000,
457 .max_uV = 1800000,
458 .apply_uV = 1,
459 },
460};
461
462static struct regulator_init_data goni_ldo17_data = {
463 .constraints = {
464 .name = "VCC_3.0V_LCD",
465 .min_uV = 3000000,
466 .max_uV = 3000000,
467 .apply_uV = 1,
468 .always_on = 1,
469 },
470};
471
472/* BUCK */
473static struct regulator_consumer_supply buck1_consumer =
474 REGULATOR_SUPPLY("vddarm", NULL);
475
476static struct regulator_consumer_supply buck2_consumer =
477 REGULATOR_SUPPLY("vddint", NULL);
478
479static struct regulator_consumer_supply buck3_consumer =
480 REGULATOR_SUPPLY("vdet", "s5p-sdo");
481
482
483static struct regulator_init_data goni_buck1_data = {
484 .constraints = {
485 .name = "VARM_1.2V",
486 .min_uV = 1200000,
487 .max_uV = 1200000,
488 .apply_uV = 1,
489 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
490 REGULATOR_CHANGE_STATUS,
491 },
492 .num_consumer_supplies = 1,
493 .consumer_supplies = &buck1_consumer,
494};
495
496static struct regulator_init_data goni_buck2_data = {
497 .constraints = {
498 .name = "VINT_1.2V",
499 .min_uV = 1200000,
500 .max_uV = 1200000,
501 .apply_uV = 1,
502 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
503 REGULATOR_CHANGE_STATUS,
504 },
505 .num_consumer_supplies = 1,
506 .consumer_supplies = &buck2_consumer,
507};
508
509static struct regulator_init_data goni_buck3_data = {
510 .constraints = {
511 .name = "VCC_1.8V",
512 .min_uV = 1800000,
513 .max_uV = 1800000,
514 .apply_uV = 1,
515 .state_mem = {
516 .enabled = 1,
517 },
518 },
519 .num_consumer_supplies = 1,
520 .consumer_supplies = &buck3_consumer,
521};
522
523static struct regulator_init_data goni_buck4_data = {
524 .constraints = {
525 .name = "CAM_CORE_1.2V",
526 .min_uV = 1200000,
527 .max_uV = 1200000,
528 .apply_uV = 1,
529 .always_on = 1,
530 },
531};
532
533static struct max8998_regulator_data goni_regulators[] = {
534 { MAX8998_LDO2, &goni_ldo2_data },
535 { MAX8998_LDO3, &goni_ldo3_data },
536 { MAX8998_LDO4, &goni_ldo4_data },
537 { MAX8998_LDO5, &goni_ldo5_data },
538 { MAX8998_LDO6, &goni_ldo6_data },
539 { MAX8998_LDO7, &goni_ldo7_data },
540 { MAX8998_LDO8, &goni_ldo8_data },
541 { MAX8998_LDO9, &goni_ldo9_data },
542 { MAX8998_LDO10, &goni_ldo10_data },
543 { MAX8998_LDO11, &goni_ldo11_data },
544 { MAX8998_LDO12, &goni_ldo12_data },
545 { MAX8998_LDO13, &goni_ldo13_data },
546 { MAX8998_LDO14, &goni_ldo14_data },
547 { MAX8998_LDO15, &goni_ldo15_data },
548 { MAX8998_LDO16, &goni_ldo16_data },
549 { MAX8998_LDO17, &goni_ldo17_data },
550 { MAX8998_BUCK1, &goni_buck1_data },
551 { MAX8998_BUCK2, &goni_buck2_data },
552 { MAX8998_BUCK3, &goni_buck3_data },
553 { MAX8998_BUCK4, &goni_buck4_data },
554};
555
556static struct max8998_platform_data goni_max8998_pdata = {
557 .num_regulators = ARRAY_SIZE(goni_regulators),
558 .regulators = goni_regulators,
559 .buck1_set1 = S5PV210_GPH0(3),
560 .buck1_set2 = S5PV210_GPH0(4),
561 .buck2_set3 = S5PV210_GPH0(5),
562 .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
563 .buck2_voltage = { 1200000, 1200000 },
564};
565#endif
566
567static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
568 REGULATOR_SUPPLY("DBVDD", "5-001a"),
569 REGULATOR_SUPPLY("AVDD2", "5-001a"),
570 REGULATOR_SUPPLY("CPVDD", "5-001a"),
571};
572
573static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
574 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
575 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
576};
577
578static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
579 .constraints = {
580 .always_on = 1,
581 },
582 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
583 .consumer_supplies = wm8994_fixed_voltage0_supplies,
584};
585
586static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
587 .constraints = {
588 .always_on = 1,
589 },
590 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
591 .consumer_supplies = wm8994_fixed_voltage1_supplies,
592};
593
594static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
595 .supply_name = "VCC_1.8V_PDA",
596 .microvolts = 1800000,
597 .gpio = -EINVAL,
598 .init_data = &wm8994_fixed_voltage0_init_data,
599};
600
601static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
602 .supply_name = "V_BAT",
603 .microvolts = 3700000,
604 .gpio = -EINVAL,
605 .init_data = &wm8994_fixed_voltage1_init_data,
606};
607
608static struct platform_device wm8994_fixed_voltage0 = {
609 .name = "reg-fixed-voltage",
610 .id = 0,
611 .dev = {
612 .platform_data = &wm8994_fixed_voltage0_config,
613 },
614};
615
616static struct platform_device wm8994_fixed_voltage1 = {
617 .name = "reg-fixed-voltage",
618 .id = 1,
619 .dev = {
620 .platform_data = &wm8994_fixed_voltage1_config,
621 },
622};
623
624static struct regulator_consumer_supply wm8994_avdd1_supply =
625 REGULATOR_SUPPLY("AVDD1", "5-001a");
626
627static struct regulator_consumer_supply wm8994_dcvdd_supply =
628 REGULATOR_SUPPLY("DCVDD", "5-001a");
629
630static struct regulator_init_data wm8994_ldo1_data = {
631 .constraints = {
632 .name = "AVDD1_3.0V",
633 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
634 },
635 .num_consumer_supplies = 1,
636 .consumer_supplies = &wm8994_avdd1_supply,
637};
638
639static struct regulator_init_data wm8994_ldo2_data = {
640 .constraints = {
641 .name = "DCVDD_1.0V",
642 },
643 .num_consumer_supplies = 1,
644 .consumer_supplies = &wm8994_dcvdd_supply,
645};
646
647static struct wm8994_pdata wm8994_platform_data = {
648 /* configure gpio1 function: 0x0001(Logic level input/output) */
649 .gpio_defaults[0] = 0x0001,
650 /* configure gpio3/4/5/7 function for AIF2 voice */
651 .gpio_defaults[2] = 0x8100,
652 .gpio_defaults[3] = 0x8100,
653 .gpio_defaults[4] = 0x8100,
654 .gpio_defaults[6] = 0x0100,
655 /* configure gpio8/9/10/11 function for AIF3 BT */
656 .gpio_defaults[7] = 0x8100,
657 .gpio_defaults[8] = 0x0100,
658 .gpio_defaults[9] = 0x0100,
659 .gpio_defaults[10] = 0x0100,
660 .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
661 .ldo[1] = { 0, &wm8994_ldo2_data },
662};
663
664/* GPIO I2C PMIC */
665#define AP_I2C_GPIO_PMIC_BUS_4 4
666static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
667 .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
668 .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
669};
670
671static struct platform_device goni_i2c_gpio_pmic = {
672 .name = "i2c-gpio",
673 .id = AP_I2C_GPIO_PMIC_BUS_4,
674 .dev = {
675 .platform_data = &goni_i2c_gpio_pmic_data,
676 },
677};
678
679static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
680#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
681 {
682 /* 0xCC when SRAD = 0 */
683 I2C_BOARD_INFO("max8998", 0xCC >> 1),
684 .platform_data = &goni_max8998_pdata,
685 },
686#endif
687};
688
689/* GPIO I2C AP 1.8V */
690#define AP_I2C_GPIO_BUS_5 5
691static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
692 .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
693 .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
694};
695
696static struct platform_device goni_i2c_gpio5 = {
697 .name = "i2c-gpio",
698 .id = AP_I2C_GPIO_BUS_5,
699 .dev = {
700 .platform_data = &goni_i2c_gpio5_data,
701 },
702};
703
704static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
705 {
706 /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
707 I2C_BOARD_INFO("wm8994", 0x1a),
708 .platform_data = &wm8994_platform_data,
709 },
710};
711
712/* PMIC Power button */
713static struct gpio_keys_button goni_gpio_keys_table[] = {
714 {
715 .code = KEY_POWER,
716 .gpio = S5PV210_GPH2(6),
717 .desc = "gpio-keys: KEY_POWER",
718 .type = EV_KEY,
719 .active_low = 1,
720 .wakeup = 1,
721 .debounce_interval = 1,
722 },
723};
724
725static struct gpio_keys_platform_data goni_gpio_keys_data = {
726 .buttons = goni_gpio_keys_table,
727 .nbuttons = ARRAY_SIZE(goni_gpio_keys_table),
728};
729
730static struct platform_device goni_device_gpiokeys = {
731 .name = "gpio-keys",
732 .dev = {
733 .platform_data = &goni_gpio_keys_data,
734 },
735};
736
737static void __init goni_pmic_init(void)
738{
739 /* AP_PMIC_IRQ: EINT7 */
740 s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
741 s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
742
743 /* nPower: EINT22 */
744 s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
745 s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
746}
747
748/* MoviNAND */
749static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
750 .max_width = 4,
751 .cd_type = S3C_SDHCI_CD_PERMANENT,
752};
753
754/* Wireless LAN */
755static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = {
756 .max_width = 4,
757 .cd_type = S3C_SDHCI_CD_EXTERNAL,
758 /* ext_cd_{init,cleanup} callbacks will be added later */
759};
760
761/* External Flash */
762#define GONI_EXT_FLASH_EN S5PV210_MP05(4)
763#define GONI_EXT_FLASH_CD S5PV210_GPH3(4)
764static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
765 .max_width = 4,
766 .cd_type = S3C_SDHCI_CD_GPIO,
767 .ext_cd_gpio = GONI_EXT_FLASH_CD,
768 .ext_cd_gpio_invert = 1,
769};
770
771static struct regulator_consumer_supply mmc2_supplies[] = {
772 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
773};
774
775static struct regulator_init_data mmc2_fixed_voltage_init_data = {
776 .constraints = {
777 .name = "V_TF_2.8V",
778 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
779 },
780 .num_consumer_supplies = ARRAY_SIZE(mmc2_supplies),
781 .consumer_supplies = mmc2_supplies,
782};
783
784static struct fixed_voltage_config mmc2_fixed_voltage_config = {
785 .supply_name = "EXT_FLASH_EN",
786 .microvolts = 2800000,
787 .gpio = GONI_EXT_FLASH_EN,
788 .enable_high = true,
789 .init_data = &mmc2_fixed_voltage_init_data,
790};
791
792static struct platform_device mmc2_fixed_voltage = {
793 .name = "reg-fixed-voltage",
794 .id = 2,
795 .dev = {
796 .platform_data = &mmc2_fixed_voltage_config,
797 },
798};
799
800static void goni_setup_sdhci(void)
801{
802 s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
803 s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
804 s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
805};
806
807/* Audio device */
808static struct platform_device goni_device_audio = {
809 .name = "smdk-audio",
810 .id = -1,
811};
812
813static struct platform_device *goni_devices[] __initdata = {
814 &s3c_device_fb,
815 &s5p_device_onenand,
816 &goni_spi_gpio,
817 &goni_i2c_gpio_pmic,
818 &goni_i2c_gpio5,
819 &goni_device_audio,
820 &mmc2_fixed_voltage,
821 &goni_device_gpiokeys,
822 &s5p_device_mfc,
823 &s5p_device_mfc_l,
824 &s5p_device_mfc_r,
825 &s5p_device_mixer,
826 &s5p_device_sdo,
827 &s3c_device_i2c0,
828 &s3c_device_hsmmc0,
829 &s3c_device_hsmmc1,
830 &s3c_device_hsmmc2,
831 &s5pv210_device_iis0,
832 &s3c_device_usb_hsotg,
833 &samsung_device_keypad,
834 &s3c_device_i2c1,
835 &s3c_device_i2c2,
836 &wm8994_fixed_voltage0,
837 &wm8994_fixed_voltage1,
838};
839
840static void __init goni_sound_init(void)
841{
842 /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
843 * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
844 * because it needs 24MHz clock to operate WM8994 codec.
845 */
846 __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
847}
848
849static void __init goni_map_io(void)
850{
851 s5pv210_init_io(NULL, 0);
852 s3c24xx_init_clocks(clk_xusbxti.rate);
853 s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
854 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
855}
856
857static void __init goni_reserve(void)
858{
859 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
860}
861
862static void __init goni_machine_init(void)
863{
864 /* Radio: call before I2C 1 registeration */
865 goni_radio_init();
866
867 /* I2C0 */
868 s3c_i2c0_set_platdata(NULL);
869
870 /* I2C1 */
871 s3c_i2c1_set_platdata(NULL);
872 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
873
874 /* TSP: call before I2C 2 registeration */
875 goni_tsp_init();
876
877 /* I2C2 */
878 s3c_i2c2_set_platdata(&i2c2_data);
879 i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
880
881 /* PMIC */
882 goni_pmic_init();
883 i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
884 ARRAY_SIZE(i2c_gpio_pmic_devs));
885 /* SDHCI */
886 goni_setup_sdhci();
887
888 /* SOUND */
889 goni_sound_init();
890 i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
891 ARRAY_SIZE(i2c_gpio5_devs));
892
893 /* FB */
894 s3c_fb_set_platdata(&goni_lcd_pdata);
895
896 s3c_hsotg_set_platdata(&goni_hsotg_pdata);
897
898 /* SPI */
899 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
900
901 /* KEYPAD */
902 samsung_keypad_set_platdata(&keypad_data);
903
904 platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
905}
906
907MACHINE_START(GONI, "GONI")
908 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
909 .atag_offset = 0x100,
910 .init_irq = s5pv210_init_irq,
911 .map_io = goni_map_io,
912 .init_machine = goni_machine_init,
913 .init_time = samsung_timer_init,
914 .reserve = &goni_reserve,
915 .restart = s5pv210_restart,
916MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
deleted file mode 100644
index 448e1d2eeed6..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-smdkc110.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/i2c.h>
17#include <linux/device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/setup.h>
22#include <asm/mach-types.h>
23
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/devs.h>
28#include <plat/cpu.h>
29#include <linux/platform_data/ata-samsung_cf.h>
30#include <linux/platform_data/i2c-s3c2410.h>
31#include <plat/pm.h>
32#include <plat/samsung-time.h>
33#include <plat/mfc.h>
34
35#include "common.h"
36
37/* Following are default values for UCON, ULCON and UFCON UART registers */
38#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
39 S3C2410_UCON_RXILEVEL | \
40 S3C2410_UCON_TXIRQMODE | \
41 S3C2410_UCON_RXIRQMODE | \
42 S3C2410_UCON_RXFIFO_TOI | \
43 S3C2443_UCON_RXERR_IRQEN)
44
45#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
46
47#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
48 S5PV210_UFCON_TXTRIG4 | \
49 S5PV210_UFCON_RXTRIG4)
50
51static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
52 [0] = {
53 .hwport = 0,
54 .flags = 0,
55 .ucon = SMDKC110_UCON_DEFAULT,
56 .ulcon = SMDKC110_ULCON_DEFAULT,
57 .ufcon = SMDKC110_UFCON_DEFAULT,
58 },
59 [1] = {
60 .hwport = 1,
61 .flags = 0,
62 .ucon = SMDKC110_UCON_DEFAULT,
63 .ulcon = SMDKC110_ULCON_DEFAULT,
64 .ufcon = SMDKC110_UFCON_DEFAULT,
65 },
66 [2] = {
67 .hwport = 2,
68 .flags = 0,
69 .ucon = SMDKC110_UCON_DEFAULT,
70 .ulcon = SMDKC110_ULCON_DEFAULT,
71 .ufcon = SMDKC110_UFCON_DEFAULT,
72 },
73 [3] = {
74 .hwport = 3,
75 .flags = 0,
76 .ucon = SMDKC110_UCON_DEFAULT,
77 .ulcon = SMDKC110_ULCON_DEFAULT,
78 .ufcon = SMDKC110_UFCON_DEFAULT,
79 },
80};
81
82static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
83 .setup_gpio = s5pv210_ide_setup_gpio,
84};
85
86static struct platform_device *smdkc110_devices[] __initdata = {
87 &s5pv210_device_iis0,
88 &s5pv210_device_ac97,
89 &s5pv210_device_spdif,
90 &s3c_device_cfcon,
91 &s3c_device_i2c0,
92 &s3c_device_i2c1,
93 &s3c_device_i2c2,
94 &s3c_device_rtc,
95 &s3c_device_wdt,
96 &s5p_device_fimc0,
97 &s5p_device_fimc1,
98 &s5p_device_fimc2,
99 &s5p_device_fimc_md,
100 &s5p_device_mfc,
101 &s5p_device_mfc_l,
102 &s5p_device_mfc_r,
103};
104
105static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
106 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
107 { I2C_BOARD_INFO("wm8580", 0x1b), },
108};
109
110static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
111 /* To Be Updated */
112};
113
114static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = {
115 /* To Be Updated */
116};
117
118static void __init smdkc110_map_io(void)
119{
120 s5pv210_init_io(NULL, 0);
121 s3c24xx_init_clocks(24000000);
122 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
123 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
124}
125
126static void __init smdkc110_reserve(void)
127{
128 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
129}
130
131static void __init smdkc110_machine_init(void)
132{
133 s3c_pm_init();
134
135 s3c_i2c0_set_platdata(NULL);
136 s3c_i2c1_set_platdata(NULL);
137 s3c_i2c2_set_platdata(NULL);
138 i2c_register_board_info(0, smdkc110_i2c_devs0,
139 ARRAY_SIZE(smdkc110_i2c_devs0));
140 i2c_register_board_info(1, smdkc110_i2c_devs1,
141 ARRAY_SIZE(smdkc110_i2c_devs1));
142 i2c_register_board_info(2, smdkc110_i2c_devs2,
143 ARRAY_SIZE(smdkc110_i2c_devs2));
144
145 s3c_ide_set_platdata(&smdkc110_ide_pdata);
146
147 platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
148}
149
150MACHINE_START(SMDKC110, "SMDKC110")
151 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
152 .atag_offset = 0x100,
153 .init_irq = s5pv210_init_irq,
154 .map_io = smdkc110_map_io,
155 .init_machine = smdkc110_machine_init,
156 .init_time = samsung_timer_init,
157 .restart = s5pv210_restart,
158 .reserve = &smdkc110_reserve,
159MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
deleted file mode 100644
index 2a6655fb63e7..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ /dev/null
@@ -1,337 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-smdkv210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/serial_core.h>
16#include <linux/serial_s3c.h>
17#include <linux/device.h>
18#include <linux/dm9000.h>
19#include <linux/fb.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/pwm_backlight.h>
23#include <linux/platform_data/s3c-hsotg.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <mach/map.h>
34#include <mach/regs-clock.h>
35
36#include <plat/regs-srom.h>
37#include <plat/gpio-cfg.h>
38#include <plat/devs.h>
39#include <plat/cpu.h>
40#include <plat/adc.h>
41#include <linux/platform_data/touchscreen-s3c2410.h>
42#include <linux/platform_data/ata-samsung_cf.h>
43#include <linux/platform_data/i2c-s3c2410.h>
44#include <plat/keypad.h>
45#include <plat/pm.h>
46#include <plat/fb.h>
47#include <plat/samsung-time.h>
48#include <plat/backlight.h>
49#include <plat/mfc.h>
50#include <plat/clock.h>
51
52#include "common.h"
53
54/* Following are default values for UCON, ULCON and UFCON UART registers */
55#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
56 S3C2410_UCON_RXILEVEL | \
57 S3C2410_UCON_TXIRQMODE | \
58 S3C2410_UCON_RXIRQMODE | \
59 S3C2410_UCON_RXFIFO_TOI | \
60 S3C2443_UCON_RXERR_IRQEN)
61
62#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
63
64#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
65 S5PV210_UFCON_TXTRIG4 | \
66 S5PV210_UFCON_RXTRIG4)
67
68static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
69 [0] = {
70 .hwport = 0,
71 .flags = 0,
72 .ucon = SMDKV210_UCON_DEFAULT,
73 .ulcon = SMDKV210_ULCON_DEFAULT,
74 .ufcon = SMDKV210_UFCON_DEFAULT,
75 },
76 [1] = {
77 .hwport = 1,
78 .flags = 0,
79 .ucon = SMDKV210_UCON_DEFAULT,
80 .ulcon = SMDKV210_ULCON_DEFAULT,
81 .ufcon = SMDKV210_UFCON_DEFAULT,
82 },
83 [2] = {
84 .hwport = 2,
85 .flags = 0,
86 .ucon = SMDKV210_UCON_DEFAULT,
87 .ulcon = SMDKV210_ULCON_DEFAULT,
88 .ufcon = SMDKV210_UFCON_DEFAULT,
89 },
90 [3] = {
91 .hwport = 3,
92 .flags = 0,
93 .ucon = SMDKV210_UCON_DEFAULT,
94 .ulcon = SMDKV210_ULCON_DEFAULT,
95 .ufcon = SMDKV210_UFCON_DEFAULT,
96 },
97};
98
99static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
100 .setup_gpio = s5pv210_ide_setup_gpio,
101};
102
103static uint32_t smdkv210_keymap[] __initdata = {
104 /* KEY(row, col, keycode) */
105 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
106 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
107 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
108 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
109};
110
111static struct matrix_keymap_data smdkv210_keymap_data __initdata = {
112 .keymap = smdkv210_keymap,
113 .keymap_size = ARRAY_SIZE(smdkv210_keymap),
114};
115
116static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
117 .keymap_data = &smdkv210_keymap_data,
118 .rows = 8,
119 .cols = 8,
120};
121
122static struct resource smdkv210_dm9000_resources[] = {
123 [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1),
124 [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1),
125 [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \
126 | IORESOURCE_IRQ_HIGHLEVEL),
127};
128
129static struct dm9000_plat_data smdkv210_dm9000_platdata = {
130 .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
131 .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
132};
133
134static struct platform_device smdkv210_dm9000 = {
135 .name = "dm9000",
136 .id = -1,
137 .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
138 .resource = smdkv210_dm9000_resources,
139 .dev = {
140 .platform_data = &smdkv210_dm9000_platdata,
141 },
142};
143
144static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
145 unsigned int power)
146{
147 if (power) {
148#if !defined(CONFIG_BACKLIGHT_PWM)
149 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
150 gpio_free(S5PV210_GPD0(3));
151#endif
152
153 /* fire nRESET on power up */
154 gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
155
156 gpio_set_value(S5PV210_GPH0(6), 0);
157 mdelay(10);
158
159 gpio_set_value(S5PV210_GPH0(6), 1);
160 mdelay(10);
161
162 gpio_free(S5PV210_GPH0(6));
163 } else {
164#if !defined(CONFIG_BACKLIGHT_PWM)
165 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
166 gpio_free(S5PV210_GPD0(3));
167#endif
168 }
169}
170
171static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
172 .set_power = smdkv210_lte480wv_set_power,
173};
174
175static struct platform_device smdkv210_lcd_lte480wv = {
176 .name = "platform-lcd",
177 .dev.parent = &s3c_device_fb.dev,
178 .dev.platform_data = &smdkv210_lcd_lte480wv_data,
179};
180
181static struct s3c_fb_pd_win smdkv210_fb_win0 = {
182 .max_bpp = 32,
183 .default_bpp = 24,
184 .xres = 800,
185 .yres = 480,
186};
187
188static struct fb_videomode smdkv210_lcd_timing = {
189 .left_margin = 13,
190 .right_margin = 8,
191 .upper_margin = 7,
192 .lower_margin = 5,
193 .hsync_len = 3,
194 .vsync_len = 1,
195 .xres = 800,
196 .yres = 480,
197};
198
199static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
200 .win[0] = &smdkv210_fb_win0,
201 .vtiming = &smdkv210_lcd_timing,
202 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
203 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
204 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
205};
206
207/* USB OTG */
208static struct s3c_hsotg_plat smdkv210_hsotg_pdata;
209
210static struct platform_device *smdkv210_devices[] __initdata = {
211 &s3c_device_adc,
212 &s3c_device_cfcon,
213 &s3c_device_fb,
214 &s3c_device_hsmmc0,
215 &s3c_device_hsmmc1,
216 &s3c_device_hsmmc2,
217 &s3c_device_hsmmc3,
218 &s3c_device_i2c0,
219 &s3c_device_i2c1,
220 &s3c_device_i2c2,
221 &samsung_device_pwm,
222 &s3c_device_rtc,
223 &s3c_device_ts,
224 &s3c_device_usb_hsotg,
225 &s3c_device_wdt,
226 &s5p_device_fimc0,
227 &s5p_device_fimc1,
228 &s5p_device_fimc2,
229 &s5p_device_fimc_md,
230 &s5p_device_jpeg,
231 &s5p_device_mfc,
232 &s5p_device_mfc_l,
233 &s5p_device_mfc_r,
234 &s5pv210_device_ac97,
235 &s5pv210_device_iis0,
236 &s5pv210_device_spdif,
237 &samsung_asoc_idma,
238 &samsung_device_keypad,
239 &smdkv210_dm9000,
240 &smdkv210_lcd_lte480wv,
241};
242
243static void __init smdkv210_dm9000_init(void)
244{
245 unsigned int tmp;
246
247 gpio_request(S5PV210_MP01(5), "nCS5");
248 s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
249 gpio_free(S5PV210_MP01(5));
250
251 tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
252 __raw_writel(tmp, S5P_SROM_BC5);
253
254 tmp = __raw_readl(S5P_SROM_BW);
255 tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
256 tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
257 __raw_writel(tmp, S5P_SROM_BW);
258}
259
260static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
261 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
262 { I2C_BOARD_INFO("wm8580", 0x1b), },
263};
264
265static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
266 /* To Be Updated */
267};
268
269static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
270 /* To Be Updated */
271};
272
273/* LCD Backlight data */
274static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
275 .no = S5PV210_GPD0(3),
276 .func = S3C_GPIO_SFN(2),
277};
278
279static struct platform_pwm_backlight_data smdkv210_bl_data = {
280 .pwm_id = 3,
281 .pwm_period_ns = 1000,
282 .enable_gpio = -1,
283};
284
285static void __init smdkv210_map_io(void)
286{
287 s5pv210_init_io(NULL, 0);
288 s3c24xx_init_clocks(clk_xusbxti.rate);
289 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
290 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
291}
292
293static void __init smdkv210_reserve(void)
294{
295 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
296}
297
298static void __init smdkv210_machine_init(void)
299{
300 s3c_pm_init();
301
302 smdkv210_dm9000_init();
303
304 samsung_keypad_set_platdata(&smdkv210_keypad_data);
305 s3c24xx_ts_set_platdata(NULL);
306
307 s3c_i2c0_set_platdata(NULL);
308 s3c_i2c1_set_platdata(NULL);
309 s3c_i2c2_set_platdata(NULL);
310 i2c_register_board_info(0, smdkv210_i2c_devs0,
311 ARRAY_SIZE(smdkv210_i2c_devs0));
312 i2c_register_board_info(1, smdkv210_i2c_devs1,
313 ARRAY_SIZE(smdkv210_i2c_devs1));
314 i2c_register_board_info(2, smdkv210_i2c_devs2,
315 ARRAY_SIZE(smdkv210_i2c_devs2));
316
317 s3c_ide_set_platdata(&smdkv210_ide_pdata);
318
319 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
320
321 s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
322
323 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
324
325 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
326}
327
328MACHINE_START(SMDKV210, "SMDKV210")
329 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
330 .atag_offset = 0x100,
331 .init_irq = s5pv210_init_irq,
332 .map_io = smdkv210_map_io,
333 .init_machine = smdkv210_machine_init,
334 .init_time = samsung_timer_init,
335 .restart = s5pv210_restart,
336 .reserve = &smdkv210_reserve,
337MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
deleted file mode 100644
index 157805529f26..000000000000
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
2 *
3 * Copyright (c) 2010 aESOP Community
4 * http://www.aesop.or.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/serial_core.h>
16#include <linux/serial_s3c.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/setup.h>
21#include <asm/mach-types.h>
22
23#include <mach/map.h>
24#include <mach/regs-clock.h>
25
26#include <plat/devs.h>
27#include <plat/cpu.h>
28#include <linux/platform_data/i2c-s3c2410.h>
29#include <plat/samsung-time.h>
30
31#include "common.h"
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = TORBRECK_UCON_DEFAULT,
52 .ulcon = TORBRECK_ULCON_DEFAULT,
53 .ufcon = TORBRECK_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = TORBRECK_UCON_DEFAULT,
59 .ulcon = TORBRECK_ULCON_DEFAULT,
60 .ufcon = TORBRECK_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = TORBRECK_UCON_DEFAULT,
66 .ulcon = TORBRECK_ULCON_DEFAULT,
67 .ufcon = TORBRECK_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = TORBRECK_UCON_DEFAULT,
73 .ulcon = TORBRECK_ULCON_DEFAULT,
74 .ufcon = TORBRECK_UFCON_DEFAULT,
75 },
76};
77
78static struct platform_device *torbreck_devices[] __initdata = {
79 &s5pv210_device_iis0,
80 &s3c_device_cfcon,
81 &s3c_device_hsmmc0,
82 &s3c_device_hsmmc1,
83 &s3c_device_hsmmc2,
84 &s3c_device_hsmmc3,
85 &s3c_device_i2c0,
86 &s3c_device_i2c1,
87 &s3c_device_i2c2,
88 &s3c_device_rtc,
89 &s3c_device_wdt,
90};
91
92static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
93 /* To Be Updated */
94};
95
96static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
97 /* To Be Updated */
98};
99
100static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
101 /* To Be Updated */
102};
103
104static void __init torbreck_map_io(void)
105{
106 s5pv210_init_io(NULL, 0);
107 s3c24xx_init_clocks(24000000);
108 s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
109 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
110}
111
112static void __init torbreck_machine_init(void)
113{
114 s3c_i2c0_set_platdata(NULL);
115 s3c_i2c1_set_platdata(NULL);
116 s3c_i2c2_set_platdata(NULL);
117 i2c_register_board_info(0, torbreck_i2c_devs0,
118 ARRAY_SIZE(torbreck_i2c_devs0));
119 i2c_register_board_info(1, torbreck_i2c_devs1,
120 ARRAY_SIZE(torbreck_i2c_devs1));
121 i2c_register_board_info(2, torbreck_i2c_devs2,
122 ARRAY_SIZE(torbreck_i2c_devs2));
123
124 platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
125}
126
127MACHINE_START(TORBRECK, "TORBRECK")
128 /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
129 .atag_offset = 0x100,
130 .init_irq = s5pv210_init_irq,
131 .map_io = torbreck_map_io,
132 .init_machine = torbreck_machine_init,
133 .init_time = samsung_timer_init,
134 .restart = s5pv210_restart,
135MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 3cf3f9c8ddd1..123163dd2ab0 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/pm.c 1/* linux/arch/arm/mach-s5pv210/pm.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV210 - Power Management support 6 * S5PV210 - Power Management support
@@ -19,65 +19,28 @@
19#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <plat/cpu.h> 22#include <asm/cacheflush.h>
23#include <plat/pm.h> 23#include <asm/suspend.h>
24
25#include <plat/pm-common.h>
24 26
25#include <mach/regs-irq.h>
26#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
27 28
28static struct sleep_save s5pv210_core_save[] = { 29#include "common.h"
29 /* Clock source */
30 SAVE_ITEM(S5P_CLK_SRC0),
31 SAVE_ITEM(S5P_CLK_SRC1),
32 SAVE_ITEM(S5P_CLK_SRC2),
33 SAVE_ITEM(S5P_CLK_SRC3),
34 SAVE_ITEM(S5P_CLK_SRC4),
35 SAVE_ITEM(S5P_CLK_SRC5),
36 SAVE_ITEM(S5P_CLK_SRC6),
37
38 /* Clock source Mask */
39 SAVE_ITEM(S5P_CLK_SRC_MASK0),
40 SAVE_ITEM(S5P_CLK_SRC_MASK1),
41
42 /* Clock Divider */
43 SAVE_ITEM(S5P_CLK_DIV0),
44 SAVE_ITEM(S5P_CLK_DIV1),
45 SAVE_ITEM(S5P_CLK_DIV2),
46 SAVE_ITEM(S5P_CLK_DIV3),
47 SAVE_ITEM(S5P_CLK_DIV4),
48 SAVE_ITEM(S5P_CLK_DIV5),
49 SAVE_ITEM(S5P_CLK_DIV6),
50 SAVE_ITEM(S5P_CLK_DIV7),
51
52 /* Clock Main Gate */
53 SAVE_ITEM(S5P_CLKGATE_MAIN0),
54 SAVE_ITEM(S5P_CLKGATE_MAIN1),
55 SAVE_ITEM(S5P_CLKGATE_MAIN2),
56
57 /* Clock source Peri Gate */
58 SAVE_ITEM(S5P_CLKGATE_PERI0),
59 SAVE_ITEM(S5P_CLKGATE_PERI1),
60
61 /* Clock source SCLK Gate */
62 SAVE_ITEM(S5P_CLKGATE_SCLK0),
63 SAVE_ITEM(S5P_CLKGATE_SCLK1),
64
65 /* Clock IP Clock gate */
66 SAVE_ITEM(S5P_CLKGATE_IP0),
67 SAVE_ITEM(S5P_CLKGATE_IP1),
68 SAVE_ITEM(S5P_CLKGATE_IP2),
69 SAVE_ITEM(S5P_CLKGATE_IP3),
70 SAVE_ITEM(S5P_CLKGATE_IP4),
71
72 /* Clock Blcok and Bus gate */
73 SAVE_ITEM(S5P_CLKGATE_BLOCK),
74 SAVE_ITEM(S5P_CLKGATE_BUS0),
75 30
31static struct sleep_save s5pv210_core_save[] = {
76 /* Clock ETC */ 32 /* Clock ETC */
77 SAVE_ITEM(S5P_CLK_OUT),
78 SAVE_ITEM(S5P_MDNIE_SEL), 33 SAVE_ITEM(S5P_MDNIE_SEL),
79}; 34};
80 35
36/*
37 * VIC wake-up support (TODO)
38 */
39static u32 s5pv210_irqwake_intmask = 0xffffffff;
40
41/*
42 * Suspend helpers.
43 */
81static int s5pv210_cpu_suspend(unsigned long arg) 44static int s5pv210_cpu_suspend(unsigned long arg)
82{ 45{
83 unsigned long tmp; 46 unsigned long tmp;
@@ -102,8 +65,12 @@ static void s5pv210_pm_prepare(void)
102{ 65{
103 unsigned int tmp; 66 unsigned int tmp;
104 67
68 /* Set wake-up mask registers */
69 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
70 __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
71
105 /* ensure at least INFORM0 has the resume address */ 72 /* ensure at least INFORM0 has the resume address */
106 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); 73 __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
107 74
108 tmp = __raw_readl(S5P_SLEEP_CFG); 75 tmp = __raw_readl(S5P_SLEEP_CFG);
109 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); 76 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
@@ -123,26 +90,70 @@ static void s5pv210_pm_prepare(void)
123 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 90 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
124} 91}
125 92
126static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) 93/*
94 * Suspend operations.
95 */
96static int s5pv210_suspend_enter(suspend_state_t state)
127{ 97{
128 pm_cpu_prep = s5pv210_pm_prepare; 98 int ret;
129 pm_cpu_sleep = s5pv210_cpu_suspend; 99
100 s3c_pm_debug_init();
101
102 S3C_PMDBG("%s: suspending the system...\n", __func__);
103
104 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
105 s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
106
107 if (s5pv210_irqwake_intmask == -1U
108 && exynos_get_eint_wake_mask() == -1U) {
109 pr_err("%s: No wake-up sources!\n", __func__);
110 pr_err("%s: Aborting sleep\n", __func__);
111 return -EINVAL;
112 }
113
114 s3c_pm_save_uarts();
115 s5pv210_pm_prepare();
116 flush_cache_all();
117 s3c_pm_check_store();
118
119 ret = cpu_suspend(0, s5pv210_cpu_suspend);
120 if (ret)
121 return ret;
122
123 s3c_pm_restore_uarts();
124
125 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
126 __raw_readl(S5P_WAKEUP_STAT));
127
128 s3c_pm_check_restore();
129
130 S3C_PMDBG("%s: resuming the system...\n", __func__);
130 131
131 return 0; 132 return 0;
132} 133}
133 134
134static struct subsys_interface s5pv210_pm_interface = { 135static int s5pv210_suspend_prepare(void)
135 .name = "s5pv210_pm", 136{
136 .subsys = &s5pv210_subsys, 137 s3c_pm_check_prepare();
137 .add_dev = s5pv210_pm_add,
138};
139 138
140static __init int s5pv210_pm_drvinit(void) 139 return 0;
140}
141
142static void s5pv210_suspend_finish(void)
141{ 143{
142 return subsys_interface_register(&s5pv210_pm_interface); 144 s3c_pm_check_cleanup();
143} 145}
144arch_initcall(s5pv210_pm_drvinit);
145 146
147static const struct platform_suspend_ops s5pv210_suspend_ops = {
148 .enter = s5pv210_suspend_enter,
149 .prepare = s5pv210_suspend_prepare,
150 .finish = s5pv210_suspend_finish,
151 .valid = suspend_valid_only_mem,
152};
153
154/*
155 * Syscore operations used to delay restore of certain registers.
156 */
146static void s5pv210_pm_resume(void) 157static void s5pv210_pm_resume(void)
147{ 158{
148 u32 tmp; 159 u32 tmp;
@@ -159,9 +170,11 @@ static struct syscore_ops s5pv210_pm_syscore_ops = {
159 .resume = s5pv210_pm_resume, 170 .resume = s5pv210_pm_resume,
160}; 171};
161 172
162static __init int s5pv210_pm_syscore_init(void) 173/*
174 * Initialization entry point.
175 */
176void __init s5pv210_pm_init(void)
163{ 177{
164 register_syscore_ops(&s5pv210_pm_syscore_ops); 178 register_syscore_ops(&s5pv210_pm_syscore_ops);
165 return 0; 179 suspend_set_ops(&s5pv210_suspend_ops);
166} 180}
167arch_initcall(s5pv210_pm_syscore_init);
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
new file mode 100644
index 000000000000..53feff33d129
--- /dev/null
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -0,0 +1,77 @@
1/*
2 * Samsung's S5PC110/S5PV210 flattened device tree enabled machine.
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
5 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
6 * Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/of_fdt.h>
14#include <linux/of_platform.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18#include <asm/system_misc.h>
19
20#include <plat/map-base.h>
21#include <mach/regs-clock.h>
22
23#include "common.h"
24
25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
26 int depth, void *data)
27{
28 struct map_desc iodesc;
29 const __be32 *reg;
30 int len;
31
32 if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock"))
33 return 0;
34
35 reg = of_get_flat_dt_prop(node, "reg", &len);
36 if (reg == NULL || len != (sizeof(unsigned long) * 2))
37 return 0;
38
39 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
40 iodesc.length = be32_to_cpu(reg[1]) - 1;
41 iodesc.virtual = (unsigned long)S3C_VA_SYS;
42 iodesc.type = MT_DEVICE;
43 iotable_init(&iodesc, 1);
44
45 return 1;
46}
47
48static void __init s5pv210_dt_map_io(void)
49{
50 debug_ll_io_init();
51
52 of_scan_flat_dt(s5pv210_fdt_map_sys, NULL);
53}
54
55static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd)
56{
57 __raw_writel(0x1, S5P_SWRESET);
58}
59
60static void __init s5pv210_dt_init_late(void)
61{
62 platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0);
63 s5pv210_pm_init();
64}
65
66static char const *s5pv210_dt_compat[] __initconst = {
67 "samsung,s5pc110",
68 "samsung,s5pv210",
69 NULL
70};
71
72DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board")
73 .dt_compat = s5pv210_dt_compat,
74 .map_io = s5pv210_dt_map_io,
75 .restart = s5pv210_dt_restart,
76 .init_late = s5pv210_dt_init_late,
77MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
deleted file mode 100644
index 55103c8220b3..000000000000
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Base s5pv210 setup information for 24bpp LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fb.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <plat/fb.h>
20#include <mach/regs-clock.h>
21#include <plat/gpio-cfg.h>
22
23static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
24{
25 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
26
27 for (; nr > 0; nr--, base++)
28 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
29}
30
31
32void s5pv210_fb_gpio_setup_24bpp(void)
33{
34 s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
35 s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
36 s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
37 s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
38
39 /* Set DISPLAY_CONTROL register for Display path selection.
40 *
41 * ouput | RGB | I80 | ITU
42 * -----------------------------------
43 * 00 | MIE | FIMD | FIMD
44 * 01 | MDNIE | MDNIE | FIMD
45 * 10 | FIMD | FIMD | FIMD
46 * 11 | FIMD | FIMD | FIMD
47 */
48 writel(0x2, S5P_MDNIE_SEL);
49}
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
deleted file mode 100644
index 54cc5b11be0b..000000000000
--- a/arch/arm/mach-s5pv210/setup-fimc.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5PV210 camera interface GPIO configuration.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13#include <plat/camport.h>
14
15int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
16{
17 u32 gpio8, gpio5;
18 int ret;
19
20 switch (id) {
21 case S5P_CAMPORT_A:
22 gpio8 = S5PV210_GPE0(0);
23 gpio5 = S5PV210_GPE1(0);
24 break;
25
26 case S5P_CAMPORT_B:
27 gpio8 = S5PV210_GPJ0(0);
28 gpio5 = S5PV210_GPJ1(0);
29 break;
30
31 default:
32 WARN(1, "Wrong camport id: %d\n", id);
33 return -EINVAL;
34 }
35
36 ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
37 S3C_GPIO_PULL_UP);
38 if (ret)
39 return ret;
40
41 return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
42 S3C_GPIO_PULL_UP);
43}
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
deleted file mode 100644
index 4a15849766c0..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
deleted file mode 100644
index 4777f6b97a92..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c1.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C1 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c1.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
deleted file mode 100644
index bbce6c74b915..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c2.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C2 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c2_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
deleted file mode 100644
index ea123d546bd2..000000000000
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV210 setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15
16#include <plat/gpio-cfg.h>
17
18static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
19{
20 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
21
22 for (; nr > 0; nr--, base++)
23 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
24}
25
26void s5pv210_ide_setup_gpio(void)
27{
28 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
29 s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
30
31 /* CF_Data[0 - 7] */
32 s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
33
34 /* CF_Data[8 - 15] */
35 s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
36
37 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
38 s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
39}
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
deleted file mode 100644
index c56420a52f48..000000000000
--- a/arch/arm/mach-s5pv210/setup-keypad.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv210/setup-keypad.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/gpio.h>
15#include <plat/gpio-cfg.h>
16
17void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
18{
19 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
20 s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
21
22 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
23 s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
24}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
deleted file mode 100644
index 0512ada00522..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,103 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/sdhci.h>
24
25void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
26{
27 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
28
29 /* Set all the necessary GPG0/GPG1 pins to special-function 2 */
30 s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
31
32 switch (width) {
33 case 8:
34 /* GPG1[3:6] special-function 3 */
35 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
36 case 4:
37 /* GPG0[3:6] special-function 2 */
38 s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
39 default:
40 break;
41 }
42
43 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
44 s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
45 s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
46 }
47}
48
49void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
50{
51 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
52
53 /* Set all the necessary GPG1[0:1] pins to special-function 2 */
54 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
55
56 /* Data pin GPG1[3:6] to special-function 2 */
57 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
58
59 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
60 s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
61 s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
62 }
63}
64
65void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
66{
67 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
68
69 /* Set all the necessary GPG2[0:1] pins to special-function 2 */
70 s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
71
72 switch (width) {
73 case 8:
74 /* Data pin GPG3[3:6] to special-function 3 */
75 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
76 case 4:
77 /* Data pin GPG2[3:6] to special-function 2 */
78 s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
79 default:
80 break;
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
85 s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
86 }
87}
88
89void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
90{
91 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
92
93 /* Set all the necessary GPG3[0:1] pins to special-function 2 */
94 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
95
96 /* Data pin GPG3[3:6] to special-function 2 */
97 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
98
99 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
100 s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
101 s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
102 }
103}
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
deleted file mode 100644
index 81aecc162f82..000000000000
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
18 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
19 s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
20 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
21 return 0;
22}
23#endif
24
25#ifdef CONFIG_S3C64XX_DEV_SPI1
26int s3c64xx_spi1_cfg_gpio(void)
27{
28 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
30 s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
31 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
32 return 0;
33}
34#endif
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
deleted file mode 100644
index b2ee5333f89c..000000000000
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundationr
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15
16#include <mach/map.h>
17
18#include <plat/cpu.h>
19#include <plat/regs-usb-hsotg-phy.h>
20#include <plat/usb-phy.h>
21
22#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
23#define S5PV210_USB_PHY0_EN (1 << 0)
24#define S5PV210_USB_PHY1_EN (1 << 1)
25
26static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
27{
28 struct clk *xusbxti;
29 u32 phyclk;
30
31 writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
32 S5PV210_USB_PHY_CON);
33
34 /* set clock frequency for PLL */
35 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
36
37 xusbxti = clk_get(&pdev->dev, "xusbxti");
38 if (xusbxti && !IS_ERR(xusbxti)) {
39 switch (clk_get_rate(xusbxti)) {
40 case 12 * MHZ:
41 phyclk |= S3C_PHYCLK_CLKSEL_12M;
42 break;
43 case 24 * MHZ:
44 phyclk |= S3C_PHYCLK_CLKSEL_24M;
45 break;
46 default:
47 case 48 * MHZ:
48 /* default reference clock */
49 break;
50 }
51 clk_put(xusbxti);
52 }
53
54 /* TODO: select external clock/oscillator */
55 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
56
57 /* set to normal OTG PHY */
58 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
59 mdelay(1);
60
61 /* reset OTG PHY and Link */
62 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
63 S3C_RSTCON);
64 udelay(20); /* at-least 10uS */
65 writel(0, S3C_RSTCON);
66
67 return 0;
68}
69
70static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
71{
72 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
73 S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
74
75 writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
76 S5PV210_USB_PHY_CON);
77
78 return 0;
79}
80
81int s5p_usb_phy_init(struct platform_device *pdev, int type)
82{
83 if (type == USB_PHY_TYPE_DEVICE)
84 return s5pv210_usb_otgphy_init(pdev);
85
86 return -EINVAL;
87}
88
89int s5p_usb_phy_exit(struct platform_device *pdev, int type)
90{
91 if (type == USB_PHY_TYPE_DEVICE)
92 return s5pv210_usb_otgphy_exit(pdev);
93
94 return -EINVAL;
95}
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
new file mode 100644
index 000000000000..7c43ddd33ba8
--- /dev/null
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -0,0 +1,36 @@
1/*
2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5PV210 Sleep Code
6 * Based on S3C64XX sleep code by:
7 * Ben Dooks, (c) 2008 Simtec Electronics
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/linkage.h>
16
17 .data
18 .align
19
20 /*
21 * sleep magic, to allow the bootloader to check for an valid
22 * image to resume to. Must be the first word before the
23 * s3c_cpu_resume entry.
24 */
25
26 .word 0x2bedf00d
27
28 /*
29 * s3c_cpu_resume
30 *
31 * resume code entry for bootloader to call
32 */
33
34ENTRY(s5pv210_cpu_resume)
35 b cpu_resume
36ENDPROC(s5pv210_cpu_resume)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 12:12:36 -0500