aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pv210
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/clock.c130
-rw-r--r--arch/arm/mach-s5pv210/include/mach/clkdev.h7
2 files changed, 47 insertions, 90 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..b5c95e663c53 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
36static struct clksrc_clk clk_mout_apll = { 36static struct clksrc_clk clk_mout_apll = {
37 .clk = { 37 .clk = {
38 .name = "mout_apll", 38 .name = "mout_apll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_apll, 40 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
45static struct clksrc_clk clk_mout_epll = { 44static struct clksrc_clk clk_mout_epll = {
46 .clk = { 45 .clk = {
47 .name = "mout_epll", 46 .name = "mout_epll",
48 .id = -1,
49 }, 47 },
50 .sources = &clk_src_epll, 48 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
54static struct clksrc_clk clk_mout_mpll = { 52static struct clksrc_clk clk_mout_mpll = {
55 .clk = { 53 .clk = {
56 .name = "mout_mpll", 54 .name = "mout_mpll",
57 .id = -1,
58 }, 55 },
59 .sources = &clk_src_mpll, 56 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
73static struct clksrc_clk clk_armclk = { 70static struct clksrc_clk clk_armclk = {
74 .clk = { 71 .clk = {
75 .name = "armclk", 72 .name = "armclk",
76 .id = -1,
77 }, 73 },
78 .sources = &clkset_armclk, 74 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
83static struct clksrc_clk clk_hclk_msys = { 79static struct clksrc_clk clk_hclk_msys = {
84 .clk = { 80 .clk = {
85 .name = "hclk_msys", 81 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk, 82 .parent = &clk_armclk.clk,
88 }, 83 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
92static struct clksrc_clk clk_pclk_msys = { 87static struct clksrc_clk clk_pclk_msys = {
93 .clk = { 88 .clk = {
94 .name = "pclk_msys", 89 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk, 90 .parent = &clk_hclk_msys.clk,
97 }, 91 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
101static struct clksrc_clk clk_sclk_a2m = { 95static struct clksrc_clk clk_sclk_a2m = {
102 .clk = { 96 .clk = {
103 .name = "sclk_a2m", 97 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk, 98 .parent = &clk_mout_apll.clk,
106 }, 99 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
120static struct clksrc_clk clk_hclk_dsys = { 113static struct clksrc_clk clk_hclk_dsys = {
121 .clk = { 114 .clk = {
122 .name = "hclk_dsys", 115 .name = "hclk_dsys",
123 .id = -1,
124 }, 116 },
125 .sources = &clkset_hclk_sys, 117 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
130static struct clksrc_clk clk_pclk_dsys = { 122static struct clksrc_clk clk_pclk_dsys = {
131 .clk = { 123 .clk = {
132 .name = "pclk_dsys", 124 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk, 125 .parent = &clk_hclk_dsys.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
139static struct clksrc_clk clk_hclk_psys = { 130static struct clksrc_clk clk_hclk_psys = {
140 .clk = { 131 .clk = {
141 .name = "hclk_psys", 132 .name = "hclk_psys",
142 .id = -1,
143 }, 133 },
144 .sources = &clkset_hclk_sys, 134 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
149static struct clksrc_clk clk_pclk_psys = { 139static struct clksrc_clk clk_pclk_psys = {
150 .clk = { 140 .clk = {
151 .name = "pclk_psys", 141 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk, 142 .parent = &clk_hclk_psys.clk,
154 }, 143 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 176
188static struct clk clk_sclk_hdmi27m = { 177static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m", 178 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000, 179 .rate = 27000000,
192}; 180};
193 181
194static struct clk clk_sclk_hdmiphy = { 182static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy", 183 .name = "sclk_hdmiphy",
196 .id = -1,
197}; 184};
198 185
199static struct clk clk_sclk_usbphy0 = { 186static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0", 187 .name = "sclk_usbphy0",
201 .id = -1,
202}; 188};
203 189
204static struct clk clk_sclk_usbphy1 = { 190static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1", 191 .name = "sclk_usbphy1",
206 .id = -1,
207}; 192};
208 193
209static struct clk clk_pcmcdclk0 = { 194static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk", 195 .name = "pcmcdclk",
211 .id = -1,
212}; 196};
213 197
214static struct clk clk_pcmcdclk1 = { 198static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk", 199 .name = "pcmcdclk",
216 .id = -1,
217}; 200};
218 201
219static struct clk clk_pcmcdclk2 = { 202static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk", 203 .name = "pcmcdclk",
221 .id = -1,
222}; 204};
223 205
224static struct clk *clkset_vpllsrc_list[] = { 206static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
234static struct clksrc_clk clk_vpllsrc = { 216static struct clksrc_clk clk_vpllsrc = {
235 .clk = { 217 .clk = {
236 .name = "vpll_src", 218 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl, 219 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7), 220 .ctrlbit = (1 << 7),
240 }, 221 },
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
255static struct clksrc_clk clk_sclk_vpll = { 236static struct clksrc_clk clk_sclk_vpll = {
256 .clk = { 237 .clk = {
257 .name = "sclk_vpll", 238 .name = "sclk_vpll",
258 .id = -1,
259 }, 239 },
260 .sources = &clkset_sclk_vpll, 240 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
276static struct clksrc_clk clk_mout_dmc0 = { 256static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = { 257 .clk = {
278 .name = "mout_dmc0", 258 .name = "mout_dmc0",
279 .id = -1,
280 }, 259 },
281 .sources = &clkset_moutdmc0src, 260 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
285static struct clksrc_clk clk_sclk_dmc0 = { 264static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = { 265 .clk = {
287 .name = "sclk_dmc0", 266 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk, 267 .parent = &clk_mout_dmc0.clk,
290 }, 268 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, 269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
312static struct clk init_clocks_off[] = { 290static struct clk init_clocks_off[] = {
313 { 291 {
314 .name = "pdma", 292 .name = "pdma",
315 .id = 0, 293 .devname = "s3c-pl330.0",
316 .parent = &clk_hclk_psys.clk, 294 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl, 295 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3), 296 .ctrlbit = (1 << 3),
319 }, { 297 }, {
320 .name = "pdma", 298 .name = "pdma",
321 .id = 1, 299 .devname = "s3c-pl330.1",
322 .parent = &clk_hclk_psys.clk, 300 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl, 301 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4), 302 .ctrlbit = (1 << 4),
325 }, { 303 }, {
326 .name = "rot", 304 .name = "rot",
327 .id = -1,
328 .parent = &clk_hclk_dsys.clk, 305 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl, 306 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29), 307 .ctrlbit = (1<<29),
331 }, { 308 }, {
332 .name = "fimc", 309 .name = "fimc",
333 .id = 0, 310 .devname = "s5pv210-fimc.0",
334 .parent = &clk_hclk_dsys.clk, 311 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl, 312 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24), 313 .ctrlbit = (1 << 24),
337 }, { 314 }, {
338 .name = "fimc", 315 .name = "fimc",
339 .id = 1, 316 .devname = "s5pv210-fimc.1",
340 .parent = &clk_hclk_dsys.clk, 317 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl, 318 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25), 319 .ctrlbit = (1 << 25),
343 }, { 320 }, {
344 .name = "fimc", 321 .name = "fimc",
345 .id = 2, 322 .devname = "s5pv210-fimc.2",
346 .parent = &clk_hclk_dsys.clk, 323 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl, 324 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26), 325 .ctrlbit = (1 << 26),
349 }, { 326 }, {
350 .name = "otg", 327 .name = "otg",
351 .id = -1,
352 .parent = &clk_hclk_psys.clk, 328 .parent = &clk_hclk_psys.clk,
353 .enable = s5pv210_clk_ip1_ctrl, 329 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16), 330 .ctrlbit = (1<<16),
355 }, { 331 }, {
356 .name = "usb-host", 332 .name = "usb-host",
357 .id = -1,
358 .parent = &clk_hclk_psys.clk, 333 .parent = &clk_hclk_psys.clk,
359 .enable = s5pv210_clk_ip1_ctrl, 334 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17), 335 .ctrlbit = (1<<17),
361 }, { 336 }, {
362 .name = "lcd", 337 .name = "lcd",
363 .id = -1,
364 .parent = &clk_hclk_dsys.clk, 338 .parent = &clk_hclk_dsys.clk,
365 .enable = s5pv210_clk_ip1_ctrl, 339 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0), 340 .ctrlbit = (1<<0),
367 }, { 341 }, {
368 .name = "cfcon", 342 .name = "cfcon",
369 .id = 0,
370 .parent = &clk_hclk_psys.clk, 343 .parent = &clk_hclk_psys.clk,
371 .enable = s5pv210_clk_ip1_ctrl, 344 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25), 345 .ctrlbit = (1<<25),
373 }, { 346 }, {
374 .name = "hsmmc", 347 .name = "hsmmc",
375 .id = 0, 348 .devname = "s3c-sdhci.0",
376 .parent = &clk_hclk_psys.clk, 349 .parent = &clk_hclk_psys.clk,
377 .enable = s5pv210_clk_ip2_ctrl, 350 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16), 351 .ctrlbit = (1<<16),
379 }, { 352 }, {
380 .name = "hsmmc", 353 .name = "hsmmc",
381 .id = 1, 354 .devname = "s3c-sdhci.1",
382 .parent = &clk_hclk_psys.clk, 355 .parent = &clk_hclk_psys.clk,
383 .enable = s5pv210_clk_ip2_ctrl, 356 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17), 357 .ctrlbit = (1<<17),
385 }, { 358 }, {
386 .name = "hsmmc", 359 .name = "hsmmc",
387 .id = 2, 360 .devname = "s3c-sdhci.2",
388 .parent = &clk_hclk_psys.clk, 361 .parent = &clk_hclk_psys.clk,
389 .enable = s5pv210_clk_ip2_ctrl, 362 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18), 363 .ctrlbit = (1<<18),
391 }, { 364 }, {
392 .name = "hsmmc", 365 .name = "hsmmc",
393 .id = 3, 366 .devname = "s3c-sdhci.3",
394 .parent = &clk_hclk_psys.clk, 367 .parent = &clk_hclk_psys.clk,
395 .enable = s5pv210_clk_ip2_ctrl, 368 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19), 369 .ctrlbit = (1<<19),
397 }, { 370 }, {
398 .name = "systimer", 371 .name = "systimer",
399 .id = -1,
400 .parent = &clk_pclk_psys.clk, 372 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl, 373 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16), 374 .ctrlbit = (1<<16),
403 }, { 375 }, {
404 .name = "watchdog", 376 .name = "watchdog",
405 .id = -1,
406 .parent = &clk_pclk_psys.clk, 377 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl, 378 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22), 379 .ctrlbit = (1<<22),
409 }, { 380 }, {
410 .name = "rtc", 381 .name = "rtc",
411 .id = -1,
412 .parent = &clk_pclk_psys.clk, 382 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl, 383 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15), 384 .ctrlbit = (1<<15),
415 }, { 385 }, {
416 .name = "i2c", 386 .name = "i2c",
417 .id = 0, 387 .devname = "s3c2440-i2c.0",
418 .parent = &clk_pclk_psys.clk, 388 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl, 389 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7), 390 .ctrlbit = (1<<7),
421 }, { 391 }, {
422 .name = "i2c", 392 .name = "i2c",
423 .id = 1, 393 .devname = "s3c2440-i2c.1",
424 .parent = &clk_pclk_psys.clk, 394 .parent = &clk_pclk_psys.clk,
425 .enable = s5pv210_clk_ip3_ctrl, 395 .enable = s5pv210_clk_ip3_ctrl,
426 .ctrlbit = (1 << 10), 396 .ctrlbit = (1 << 10),
427 }, { 397 }, {
428 .name = "i2c", 398 .name = "i2c",
429 .id = 2, 399 .devname = "s3c2440-i2c.2",
430 .parent = &clk_pclk_psys.clk, 400 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 401 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9), 402 .ctrlbit = (1<<9),
433 }, { 403 }, {
434 .name = "spi", 404 .name = "spi",
435 .id = 0, 405 .devname = "s3c64xx-spi.0",
436 .parent = &clk_pclk_psys.clk, 406 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 407 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12), 408 .ctrlbit = (1<<12),
439 }, { 409 }, {
440 .name = "spi", 410 .name = "spi",
441 .id = 1, 411 .devname = "s3c64xx-spi.1",
442 .parent = &clk_pclk_psys.clk, 412 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13), 414 .ctrlbit = (1<<13),
445 }, { 415 }, {
446 .name = "spi", 416 .name = "spi",
447 .id = 2, 417 .devname = "s3c64xx-spi.2",
448 .parent = &clk_pclk_psys.clk, 418 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14), 420 .ctrlbit = (1<<14),
451 }, { 421 }, {
452 .name = "timers", 422 .name = "timers",
453 .id = -1,
454 .parent = &clk_pclk_psys.clk, 423 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl, 424 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23), 425 .ctrlbit = (1<<23),
457 }, { 426 }, {
458 .name = "adc", 427 .name = "adc",
459 .id = -1,
460 .parent = &clk_pclk_psys.clk, 428 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl, 429 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24), 430 .ctrlbit = (1<<24),
463 }, { 431 }, {
464 .name = "keypad", 432 .name = "keypad",
465 .id = -1,
466 .parent = &clk_pclk_psys.clk, 433 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl, 434 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 435 .ctrlbit = (1<<21),
469 }, { 436 }, {
470 .name = "iis", 437 .name = "iis",
471 .id = 0, 438 .devname = "samsung-i2s.0",
472 .parent = &clk_p, 439 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 440 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 441 .ctrlbit = (1<<4),
475 }, { 442 }, {
476 .name = "iis", 443 .name = "iis",
477 .id = 1, 444 .devname = "samsung-i2s.1",
478 .parent = &clk_p, 445 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 446 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 447 .ctrlbit = (1 << 5),
481 }, { 448 }, {
482 .name = "iis", 449 .name = "iis",
483 .id = 2, 450 .devname = "samsung-i2s.2",
484 .parent = &clk_p, 451 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 452 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 453 .ctrlbit = (1 << 6),
487 }, { 454 }, {
488 .name = "spdif", 455 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p, 456 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl, 457 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0), 458 .ctrlbit = (1 << 0),
@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
496static struct clk init_clocks[] = { 462static struct clk init_clocks[] = {
497 { 463 {
498 .name = "hclk_imem", 464 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk, 465 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5), 466 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl, 467 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops, 468 .ops = &clk_hclk_imem_ops,
504 }, { 469 }, {
505 .name = "uart", 470 .name = "uart",
506 .id = 0, 471 .devname = "s5pv210-uart.0",
507 .parent = &clk_pclk_psys.clk, 472 .parent = &clk_pclk_psys.clk,
508 .enable = s5pv210_clk_ip3_ctrl, 473 .enable = s5pv210_clk_ip3_ctrl,
509 .ctrlbit = (1 << 17), 474 .ctrlbit = (1 << 17),
510 }, { 475 }, {
511 .name = "uart", 476 .name = "uart",
512 .id = 1, 477 .devname = "s5pv210-uart.1",
513 .parent = &clk_pclk_psys.clk, 478 .parent = &clk_pclk_psys.clk,
514 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
515 .ctrlbit = (1 << 18), 480 .ctrlbit = (1 << 18),
516 }, { 481 }, {
517 .name = "uart", 482 .name = "uart",
518 .id = 2, 483 .devname = "s5pv210-uart.2",
519 .parent = &clk_pclk_psys.clk, 484 .parent = &clk_pclk_psys.clk,
520 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
521 .ctrlbit = (1 << 19), 486 .ctrlbit = (1 << 19),
522 }, { 487 }, {
523 .name = "uart", 488 .name = "uart",
524 .id = 3, 489 .devname = "s5pv210-uart.3",
525 .parent = &clk_pclk_psys.clk, 490 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 491 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 492 .ctrlbit = (1 << 20),
528 }, { 493 }, {
529 .name = "sromc", 494 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk, 495 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl, 496 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26), 497 .ctrlbit = (1 << 26),
@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
579static struct clksrc_clk clk_sclk_dac = { 543static struct clksrc_clk clk_sclk_dac = {
580 .clk = { 544 .clk = {
581 .name = "sclk_dac", 545 .name = "sclk_dac",
582 .id = -1,
583 .enable = s5pv210_clk_mask0_ctrl, 546 .enable = s5pv210_clk_mask0_ctrl,
584 .ctrlbit = (1 << 2), 547 .ctrlbit = (1 << 2),
585 }, 548 },
@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
590static struct clksrc_clk clk_sclk_pixel = { 553static struct clksrc_clk clk_sclk_pixel = {
591 .clk = { 554 .clk = {
592 .name = "sclk_pixel", 555 .name = "sclk_pixel",
593 .id = -1,
594 .parent = &clk_sclk_vpll.clk, 556 .parent = &clk_sclk_vpll.clk,
595 }, 557 },
596 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, 558 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
609static struct clksrc_clk clk_sclk_hdmi = { 571static struct clksrc_clk clk_sclk_hdmi = {
610 .clk = { 572 .clk = {
611 .name = "sclk_hdmi", 573 .name = "sclk_hdmi",
612 .id = -1,
613 .enable = s5pv210_clk_mask0_ctrl, 574 .enable = s5pv210_clk_mask0_ctrl,
614 .ctrlbit = (1 << 0), 575 .ctrlbit = (1 << 0),
615 }, 576 },
@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
647static struct clksrc_clk clk_sclk_audio0 = { 608static struct clksrc_clk clk_sclk_audio0 = {
648 .clk = { 609 .clk = {
649 .name = "sclk_audio", 610 .name = "sclk_audio",
650 .id = 0, 611 .devname = "soc-audio.0",
651 .enable = s5pv210_clk_mask0_ctrl, 612 .enable = s5pv210_clk_mask0_ctrl,
652 .ctrlbit = (1 << 24), 613 .ctrlbit = (1 << 24),
653 }, 614 },
@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
676static struct clksrc_clk clk_sclk_audio1 = { 637static struct clksrc_clk clk_sclk_audio1 = {
677 .clk = { 638 .clk = {
678 .name = "sclk_audio", 639 .name = "sclk_audio",
679 .id = 1, 640 .devname = "soc-audio.1",
680 .enable = s5pv210_clk_mask0_ctrl, 641 .enable = s5pv210_clk_mask0_ctrl,
681 .ctrlbit = (1 << 25), 642 .ctrlbit = (1 << 25),
682 }, 643 },
@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
705static struct clksrc_clk clk_sclk_audio2 = { 666static struct clksrc_clk clk_sclk_audio2 = {
706 .clk = { 667 .clk = {
707 .name = "sclk_audio", 668 .name = "sclk_audio",
708 .id = 2, 669 .devname = "soc-audio.2",
709 .enable = s5pv210_clk_mask0_ctrl, 670 .enable = s5pv210_clk_mask0_ctrl,
710 .ctrlbit = (1 << 26), 671 .ctrlbit = (1 << 26),
711 }, 672 },
@@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
763static struct clksrc_clk clk_sclk_spdif = { 724static struct clksrc_clk clk_sclk_spdif = {
764 .clk = { 725 .clk = {
765 .name = "sclk_spdif", 726 .name = "sclk_spdif",
766 .id = -1,
767 .enable = s5pv210_clk_mask0_ctrl, 727 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 27), 728 .ctrlbit = (1 << 27),
769 .ops = &s5pv210_sclk_spdif_ops, 729 .ops = &s5pv210_sclk_spdif_ops,
@@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = {
793 { 753 {
794 .clk = { 754 .clk = {
795 .name = "sclk_dmc", 755 .name = "sclk_dmc",
796 .id = -1,
797 }, 756 },
798 .sources = &clkset_group1, 757 .sources = &clkset_group1,
799 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 758 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = {
801 }, { 760 }, {
802 .clk = { 761 .clk = {
803 .name = "sclk_onenand", 762 .name = "sclk_onenand",
804 .id = -1,
805 }, 763 },
806 .sources = &clkset_sclk_onenand, 764 .sources = &clkset_sclk_onenand,
807 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, 765 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
809 }, { 767 }, {
810 .clk = { 768 .clk = {
811 .name = "uclk1", 769 .name = "uclk1",
812 .id = 0, 770 .devname = "s5pv210-uart.0",
813 .enable = s5pv210_clk_mask0_ctrl, 771 .enable = s5pv210_clk_mask0_ctrl,
814 .ctrlbit = (1 << 12), 772 .ctrlbit = (1 << 12),
815 }, 773 },
@@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
819 }, { 777 }, {
820 .clk = { 778 .clk = {
821 .name = "uclk1", 779 .name = "uclk1",
822 .id = 1, 780 .devname = "s5pv210-uart.1",
823 .enable = s5pv210_clk_mask0_ctrl, 781 .enable = s5pv210_clk_mask0_ctrl,
824 .ctrlbit = (1 << 13), 782 .ctrlbit = (1 << 13),
825 }, 783 },
@@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
829 }, { 787 }, {
830 .clk = { 788 .clk = {
831 .name = "uclk1", 789 .name = "uclk1",
832 .id = 2, 790 .devname = "s5pv210-uart.2",
833 .enable = s5pv210_clk_mask0_ctrl, 791 .enable = s5pv210_clk_mask0_ctrl,
834 .ctrlbit = (1 << 14), 792 .ctrlbit = (1 << 14),
835 }, 793 },
@@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
839 }, { 797 }, {
840 .clk = { 798 .clk = {
841 .name = "uclk1", 799 .name = "uclk1",
842 .id = 3, 800 .devname = "s5pv210-uart.3",
843 .enable = s5pv210_clk_mask0_ctrl, 801 .enable = s5pv210_clk_mask0_ctrl,
844 .ctrlbit = (1 << 15), 802 .ctrlbit = (1 << 15),
845 }, 803 },
@@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 807 }, {
850 .clk = { 808 .clk = {
851 .name = "sclk_mixer", 809 .name = "sclk_mixer",
852 .id = -1,
853 .enable = s5pv210_clk_mask0_ctrl, 810 .enable = s5pv210_clk_mask0_ctrl,
854 .ctrlbit = (1 << 1), 811 .ctrlbit = (1 << 1),
855 }, 812 },
@@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = {
858 }, { 815 }, {
859 .clk = { 816 .clk = {
860 .name = "sclk_fimc", 817 .name = "sclk_fimc",
861 .id = 0, 818 .devname = "s5pv210-fimc.0",
862 .enable = s5pv210_clk_mask1_ctrl, 819 .enable = s5pv210_clk_mask1_ctrl,
863 .ctrlbit = (1 << 2), 820 .ctrlbit = (1 << 2),
864 }, 821 },
@@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = {
868 }, { 825 }, {
869 .clk = { 826 .clk = {
870 .name = "sclk_fimc", 827 .name = "sclk_fimc",
871 .id = 1, 828 .devname = "s5pv210-fimc.1",
872 .enable = s5pv210_clk_mask1_ctrl, 829 .enable = s5pv210_clk_mask1_ctrl,
873 .ctrlbit = (1 << 3), 830 .ctrlbit = (1 << 3),
874 }, 831 },
@@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = {
878 }, { 835 }, {
879 .clk = { 836 .clk = {
880 .name = "sclk_fimc", 837 .name = "sclk_fimc",
881 .id = 2, 838 .devname = "s5pv210-fimc.2",
882 .enable = s5pv210_clk_mask1_ctrl, 839 .enable = s5pv210_clk_mask1_ctrl,
883 .ctrlbit = (1 << 4), 840 .ctrlbit = (1 << 4),
884 }, 841 },
@@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
888 }, { 845 }, {
889 .clk = { 846 .clk = {
890 .name = "sclk_cam", 847 .name = "sclk_cam",
891 .id = 0, 848 .devname = "s5pv210-fimc.0",
892 .enable = s5pv210_clk_mask0_ctrl, 849 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 3), 850 .ctrlbit = (1 << 3),
894 }, 851 },
@@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
898 }, { 855 }, {
899 .clk = { 856 .clk = {
900 .name = "sclk_cam", 857 .name = "sclk_cam",
901 .id = 1, 858 .devname = "s5pv210-fimc.1",
902 .enable = s5pv210_clk_mask0_ctrl, 859 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 4), 860 .ctrlbit = (1 << 4),
904 }, 861 },
@@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = {
908 }, { 865 }, {
909 .clk = { 866 .clk = {
910 .name = "sclk_fimd", 867 .name = "sclk_fimd",
911 .id = -1,
912 .enable = s5pv210_clk_mask0_ctrl, 868 .enable = s5pv210_clk_mask0_ctrl,
913 .ctrlbit = (1 << 5), 869 .ctrlbit = (1 << 5),
914 }, 870 },
@@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = {
918 }, { 874 }, {
919 .clk = { 875 .clk = {
920 .name = "sclk_mmc", 876 .name = "sclk_mmc",
921 .id = 0, 877 .devname = "s3c-sdhci.0",
922 .enable = s5pv210_clk_mask0_ctrl, 878 .enable = s5pv210_clk_mask0_ctrl,
923 .ctrlbit = (1 << 8), 879 .ctrlbit = (1 << 8),
924 }, 880 },
@@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = {
928 }, { 884 }, {
929 .clk = { 885 .clk = {
930 .name = "sclk_mmc", 886 .name = "sclk_mmc",
931 .id = 1, 887 .devname = "s3c-sdhci.1",
932 .enable = s5pv210_clk_mask0_ctrl, 888 .enable = s5pv210_clk_mask0_ctrl,
933 .ctrlbit = (1 << 9), 889 .ctrlbit = (1 << 9),
934 }, 890 },
@@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = {
938 }, { 894 }, {
939 .clk = { 895 .clk = {
940 .name = "sclk_mmc", 896 .name = "sclk_mmc",
941 .id = 2, 897 .devname = "s3c-sdhci.2",
942 .enable = s5pv210_clk_mask0_ctrl, 898 .enable = s5pv210_clk_mask0_ctrl,
943 .ctrlbit = (1 << 10), 899 .ctrlbit = (1 << 10),
944 }, 900 },
@@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = {
948 }, { 904 }, {
949 .clk = { 905 .clk = {
950 .name = "sclk_mmc", 906 .name = "sclk_mmc",
951 .id = 3, 907 .devname = "s3c-sdhci.3",
952 .enable = s5pv210_clk_mask0_ctrl, 908 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 11), 909 .ctrlbit = (1 << 11),
954 }, 910 },
@@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = {
958 }, { 914 }, {
959 .clk = { 915 .clk = {
960 .name = "sclk_mfc", 916 .name = "sclk_mfc",
961 .id = -1,
962 .enable = s5pv210_clk_ip0_ctrl, 917 .enable = s5pv210_clk_ip0_ctrl,
963 .ctrlbit = (1 << 16), 918 .ctrlbit = (1 << 16),
964 }, 919 },
@@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = {
968 }, { 923 }, {
969 .clk = { 924 .clk = {
970 .name = "sclk_g2d", 925 .name = "sclk_g2d",
971 .id = -1,
972 .enable = s5pv210_clk_ip0_ctrl, 926 .enable = s5pv210_clk_ip0_ctrl,
973 .ctrlbit = (1 << 12), 927 .ctrlbit = (1 << 12),
974 }, 928 },
@@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = {
978 }, { 932 }, {
979 .clk = { 933 .clk = {
980 .name = "sclk_g3d", 934 .name = "sclk_g3d",
981 .id = -1,
982 .enable = s5pv210_clk_ip0_ctrl, 935 .enable = s5pv210_clk_ip0_ctrl,
983 .ctrlbit = (1 << 8), 936 .ctrlbit = (1 << 8),
984 }, 937 },
@@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = {
988 }, { 941 }, {
989 .clk = { 942 .clk = {
990 .name = "sclk_csis", 943 .name = "sclk_csis",
991 .id = -1,
992 .enable = s5pv210_clk_mask0_ctrl, 944 .enable = s5pv210_clk_mask0_ctrl,
993 .ctrlbit = (1 << 6), 945 .ctrlbit = (1 << 6),
994 }, 946 },
@@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
998 }, { 950 }, {
999 .clk = { 951 .clk = {
1000 .name = "sclk_spi", 952 .name = "sclk_spi",
1001 .id = 0, 953 .devname = "s3c64xx-spi.0",
1002 .enable = s5pv210_clk_mask0_ctrl, 954 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 16), 955 .ctrlbit = (1 << 16),
1004 }, 956 },
@@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
1008 }, { 960 }, {
1009 .clk = { 961 .clk = {
1010 .name = "sclk_spi", 962 .name = "sclk_spi",
1011 .id = 1, 963 .devname = "s3c64xx-spi.1",
1012 .enable = s5pv210_clk_mask0_ctrl, 964 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 17), 965 .ctrlbit = (1 << 17),
1014 }, 966 },
@@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = {
1018 }, { 970 }, {
1019 .clk = { 971 .clk = {
1020 .name = "sclk_pwi", 972 .name = "sclk_pwi",
1021 .id = -1,
1022 .enable = s5pv210_clk_mask0_ctrl, 973 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 29), 974 .ctrlbit = (1 << 29),
1024 }, 975 },
@@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = {
1028 }, { 979 }, {
1029 .clk = { 980 .clk = {
1030 .name = "sclk_pwm", 981 .name = "sclk_pwm",
1031 .id = -1,
1032 .enable = s5pv210_clk_mask0_ctrl, 982 .enable = s5pv210_clk_mask0_ctrl,
1033 .ctrlbit = (1 << 19), 983 .ctrlbit = (1 << 19),
1034 }, 984 },
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 21:20:55 -0500