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-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h168
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c15
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c15
-rw-r--r--arch/arm/mach-s5pv210/sleep.S105
4 files changed, 105 insertions, 198 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 3611492ad681..1dd58836fd4f 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/map.h 1/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV210 - Memory map definitions 6 * S5PV210 - Memory map definitions
@@ -16,122 +16,120 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PV210_PA_SROM_BANK5 (0xA8000000) 19#define S5PV210_PA_SDRAM 0x20000000
20 20
21#define S5PC110_PA_ONENAND (0xB0000000) 21#define S5PV210_PA_SROM_BANK5 0xA8000000
22#define S5P_PA_ONENAND S5PC110_PA_ONENAND
23 22
24#define S5PC110_PA_ONENAND_DMA (0xB0600000) 23#define S5PC110_PA_ONENAND 0xB0000000
25#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 24#define S5PC110_PA_ONENAND_DMA 0xB0600000
26 25
27#define S5PV210_PA_CHIPID (0xE0000000) 26#define S5PV210_PA_CHIPID 0xE0000000
28#define S5P_PA_CHIPID S5PV210_PA_CHIPID
29 27
30#define S5PV210_PA_SYSCON (0xE0100000) 28#define S5PV210_PA_SYSCON 0xE0100000
31#define S5P_PA_SYSCON S5PV210_PA_SYSCON
32 29
33#define S5PV210_PA_GPIO (0xE0200000) 30#define S5PV210_PA_GPIO 0xE0200000
34 31
35/* SPI */ 32#define S5PV210_PA_SPDIF 0xE1100000
36#define S5PV210_PA_SPI0 0xE1300000
37#define S5PV210_PA_SPI1 0xE1400000
38 33
39#define S5PV210_PA_KEYPAD (0xE1600000) 34#define S5PV210_PA_SPI0 0xE1300000
35#define S5PV210_PA_SPI1 0xE1400000
40 36
41#define S5PV210_PA_IIC0 (0xE1800000) 37#define S5PV210_PA_KEYPAD 0xE1600000
42#define S5PV210_PA_IIC1 (0xFAB00000)
43#define S5PV210_PA_IIC2 (0xE1A00000)
44 38
45#define S5PV210_PA_TIMER (0xE2500000) 39#define S5PV210_PA_ADC 0xE1700000
46#define S5P_PA_TIMER S5PV210_PA_TIMER
47 40
48#define S5PV210_PA_SYSTIMER (0xE2600000) 41#define S5PV210_PA_IIC0 0xE1800000
42#define S5PV210_PA_IIC1 0xFAB00000
43#define S5PV210_PA_IIC2 0xE1A00000
49 44
50#define S5PV210_PA_WATCHDOG (0xE2700000) 45#define S5PV210_PA_AC97 0xE2200000
51 46
52#define S5PV210_PA_RTC (0xE2800000) 47#define S5PV210_PA_PCM0 0xE2300000
53#define S5PV210_PA_UART (0xE2900000) 48#define S5PV210_PA_PCM1 0xE1200000
49#define S5PV210_PA_PCM2 0xE2B00000
54 50
55#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) 51#define S5PV210_PA_TIMER 0xE2500000
56#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400) 52#define S5PV210_PA_SYSTIMER 0xE2600000
57#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800) 53#define S5PV210_PA_WATCHDOG 0xE2700000
58#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00) 54#define S5PV210_PA_RTC 0xE2800000
59 55
60#define S5P_SZ_UART SZ_256 56#define S5PV210_PA_UART 0xE2900000
61 57
62#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 58#define S5PV210_PA_SROMC 0xE8000000
63 59
64#define S5PV210_PA_SROMC (0xE8000000) 60#define S5PV210_PA_CFCON 0xE8200000
65#define S5P_PA_SROMC S5PV210_PA_SROMC
66 61
67#define S5PV210_PA_CFCON (0xE8200000) 62#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
68 63
69#define S5PV210_PA_MDMA 0xFA200000 64#define S5PV210_PA_HSOTG 0xEC000000
70#define S5PV210_PA_PDMA0 0xE0900000 65#define S5PV210_PA_HSPHY 0xEC100000
71#define S5PV210_PA_PDMA1 0xE0A00000
72 66
73#define S5PV210_PA_FB (0xF8000000) 67#define S5PV210_PA_IIS0 0xEEE30000
68#define S5PV210_PA_IIS1 0xE2100000
69#define S5PV210_PA_IIS2 0xE2A00000
74 70
75#define S5PV210_PA_FIMC0 (0xFB200000) 71#define S5PV210_PA_DMC0 0xF0000000
76#define S5PV210_PA_FIMC1 (0xFB300000) 72#define S5PV210_PA_DMC1 0xF1400000
77#define S5PV210_PA_FIMC2 (0xFB400000)
78 73
79#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74#define S5PV210_PA_VIC0 0xF2000000
75#define S5PV210_PA_VIC1 0xF2100000
76#define S5PV210_PA_VIC2 0xF2200000
77#define S5PV210_PA_VIC3 0xF2300000
80 78
81#define S5PV210_PA_HSOTG (0xEC000000) 79#define S5PV210_PA_FB 0xF8000000
82#define S5PV210_PA_HSPHY (0xEC100000)
83 80
84#define S5PV210_PA_VIC0 (0xF2000000) 81#define S5PV210_PA_MDMA 0xFA200000
85#define S5PV210_PA_VIC1 (0xF2100000) 82#define S5PV210_PA_PDMA0 0xE0900000
86#define S5PV210_PA_VIC2 (0xF2200000) 83#define S5PV210_PA_PDMA1 0xE0A00000
87#define S5PV210_PA_VIC3 (0xF2300000)
88 84
89#define S5PV210_PA_SDRAM (0x20000000) 85#define S5PV210_PA_MIPI_CSIS 0xFA600000
90#define S5P_PA_SDRAM S5PV210_PA_SDRAM
91 86
92/* S/PDIF */ 87#define S5PV210_PA_FIMC0 0xFB200000
93#define S5PV210_PA_SPDIF 0xE1100000 88#define S5PV210_PA_FIMC1 0xFB300000
89#define S5PV210_PA_FIMC2 0xFB400000
94 90
95/* I2S */ 91/* Compatibiltiy Defines */
96#define S5PV210_PA_IIS0 0xEEE30000
97#define S5PV210_PA_IIS1 0xE2100000
98#define S5PV210_PA_IIS2 0xE2A00000
99 92
100/* PCM */ 93#define S3C_PA_FB S5PV210_PA_FB
101#define S5PV210_PA_PCM0 0xE2300000 94#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
102#define S5PV210_PA_PCM1 0xE1200000 95#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
103#define S5PV210_PA_PCM2 0xE2B00000 96#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
97#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
98#define S3C_PA_IIC S5PV210_PA_IIC0
99#define S3C_PA_IIC1 S5PV210_PA_IIC1
100#define S3C_PA_IIC2 S5PV210_PA_IIC2
101#define S3C_PA_RTC S5PV210_PA_RTC
102#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
103#define S3C_PA_WDT S5PV210_PA_WATCHDOG
104 104
105/* AC97 */ 105#define S5P_PA_CHIPID S5PV210_PA_CHIPID
106#define S5PV210_PA_AC97 0xE2200000 106#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
107#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
110#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112#define S5P_PA_SDRAM S5PV210_PA_SDRAM
113#define S5P_PA_SROMC S5PV210_PA_SROMC
114#define S5P_PA_SYSCON S5PV210_PA_SYSCON
115#define S5P_PA_TIMER S5PV210_PA_TIMER
107 116
108#define S5PV210_PA_ADC (0xE1700000) 117#define SAMSUNG_PA_ADC S5PV210_PA_ADC
118#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
119#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
109 120
110#define S5PV210_PA_DMC0 (0xF0000000) 121/* UART */
111#define S5PV210_PA_DMC1 (0xF1400000)
112 122
113#define S5PV210_PA_MIPI_CSIS 0xFA600000 123#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
114 124
115/* compatibiltiy defines. */ 125#define S3C_PA_UART S5PV210_PA_UART
116#define S3C_PA_UART S5PV210_PA_UART
117#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
118#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
119#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
120#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
121#define S3C_PA_IIC S5PV210_PA_IIC0
122#define S3C_PA_IIC1 S5PV210_PA_IIC1
123#define S3C_PA_IIC2 S5PV210_PA_IIC2
124#define S3C_PA_FB S5PV210_PA_FB
125#define S3C_PA_RTC S5PV210_PA_RTC
126#define S3C_PA_WDT S5PV210_PA_WATCHDOG
127#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
128#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
129#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
130#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
131#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
132 126
133#define SAMSUNG_PA_ADC S5PV210_PA_ADC 127#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
134#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 128#define S5P_PA_UART0 S5P_PA_UART(0)
135#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 129#define S5P_PA_UART1 S5P_PA_UART(1)
130#define S5P_PA_UART2 S5P_PA_UART(2)
131#define S5P_PA_UART3 S5P_PA_UART(3)
132
133#define S5P_SZ_UART SZ_256
136 134
137#endif /* __ASM_ARCH_MAP_H */ 135#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 461aa035afc0..557add4fc56c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
149 149
150static struct regulator_init_data aquila_ldo3_data = { 150static struct regulator_init_data aquila_ldo3_data = {
151 .constraints = { 151 .constraints = {
152 .name = "VUSB/MIPI_1.1V", 152 .name = "VUSB+MIPI_1.1V",
153 .min_uV = 1100000, 153 .min_uV = 1100000,
154 .max_uV = 1100000, 154 .max_uV = 1100000,
155 .apply_uV = 1, 155 .apply_uV = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
197 197
198static struct regulator_init_data aquila_ldo8_data = { 198static struct regulator_init_data aquila_ldo8_data = {
199 .constraints = { 199 .constraints = {
200 .name = "VUSB/VADC_3.3V", 200 .name = "VUSB+VADC_3.3V",
201 .min_uV = 3300000, 201 .min_uV = 3300000,
202 .max_uV = 3300000, 202 .max_uV = 3300000,
203 .apply_uV = 1, 203 .apply_uV = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
207 207
208static struct regulator_init_data aquila_ldo9_data = { 208static struct regulator_init_data aquila_ldo9_data = {
209 .constraints = { 209 .constraints = {
210 .name = "VCC/VCAM_2.8V", 210 .name = "VCC+VCAM_2.8V",
211 .min_uV = 2800000, 211 .min_uV = 2800000,
212 .max_uV = 2800000, 212 .max_uV = 2800000,
213 .apply_uV = 1, 213 .apply_uV = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
381 .buck1_set1 = S5PV210_GPH0(3), 381 .buck1_set1 = S5PV210_GPH0(3),
382 .buck1_set2 = S5PV210_GPH0(4), 382 .buck1_set2 = S5PV210_GPH0(4),
383 .buck2_set3 = S5PV210_GPH0(5), 383 .buck2_set3 = S5PV210_GPH0(5),
384 .buck1_max_voltage1 = 1200000, 384 .buck1_voltage1 = 1200000,
385 .buck1_max_voltage2 = 1200000, 385 .buck1_voltage2 = 1200000,
386 .buck2_max_voltage = 1200000, 386 .buck1_voltage3 = 1200000,
387 .buck1_voltage4 = 1200000,
388 .buck2_voltage1 = 1200000,
389 .buck2_voltage2 = 1200000,
387}; 390};
388#endif 391#endif
389 392
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e22d5112fd44..056f5c769b0a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
288 288
289static struct regulator_init_data goni_ldo3_data = { 289static struct regulator_init_data goni_ldo3_data = {
290 .constraints = { 290 .constraints = {
291 .name = "VUSB/MIPI_1.1V", 291 .name = "VUSB+MIPI_1.1V",
292 .min_uV = 1100000, 292 .min_uV = 1100000,
293 .max_uV = 1100000, 293 .max_uV = 1100000,
294 .apply_uV = 1, 294 .apply_uV = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
337 337
338static struct regulator_init_data goni_ldo8_data = { 338static struct regulator_init_data goni_ldo8_data = {
339 .constraints = { 339 .constraints = {
340 .name = "VUSB/VADC_3.3V", 340 .name = "VUSB+VADC_3.3V",
341 .min_uV = 3300000, 341 .min_uV = 3300000,
342 .max_uV = 3300000, 342 .max_uV = 3300000,
343 .apply_uV = 1, 343 .apply_uV = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
347 347
348static struct regulator_init_data goni_ldo9_data = { 348static struct regulator_init_data goni_ldo9_data = {
349 .constraints = { 349 .constraints = {
350 .name = "VCC/VCAM_2.8V", 350 .name = "VCC+VCAM_2.8V",
351 .min_uV = 2800000, 351 .min_uV = 2800000,
352 .max_uV = 2800000, 352 .max_uV = 2800000,
353 .apply_uV = 1, 353 .apply_uV = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
521 .buck1_set1 = S5PV210_GPH0(3), 521 .buck1_set1 = S5PV210_GPH0(3),
522 .buck1_set2 = S5PV210_GPH0(4), 522 .buck1_set2 = S5PV210_GPH0(4),
523 .buck2_set3 = S5PV210_GPH0(5), 523 .buck2_set3 = S5PV210_GPH0(5),
524 .buck1_max_voltage1 = 1200000, 524 .buck1_voltage1 = 1200000,
525 .buck1_max_voltage2 = 1200000, 525 .buck1_voltage2 = 1200000,
526 .buck2_max_voltage = 1200000, 526 .buck1_voltage3 = 1200000,
527 .buck1_voltage4 = 1200000,
528 .buck2_voltage1 = 1200000,
529 .buck2_voltage2 = 1200000,
527}; 530};
528#endif 531#endif
529 532
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index d4d222b716b4..a3d649466fb1 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -35,50 +35,24 @@
35 /* s3c_cpu_save 35 /* s3c_cpu_save
36 * 36 *
37 * entry: 37 * entry:
38 * r0 = save address (virtual addr of s3c_sleep_save_phys) 38 * r1 = v:p offset
39 */ 39 */
40 40
41ENTRY(s3c_cpu_save) 41ENTRY(s3c_cpu_save)
42 42
43 stmfd sp!, { r3 - r12, lr } 43 stmfd sp!, { r3 - r12, lr }
44 44 ldr r3, =resume_with_mmu
45 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 45 bl cpu_suspend
46 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
47 mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
48 mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
49 mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
50 mrc p15, 0, r9, c1, c0, 0 @ Control register
51 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
52 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
53 mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
54 mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
55
56 stmia r0, { r3 - r13 }
57
58 bl s3c_pm_cb_flushcache
59 46
60 ldr r0, =pm_cpu_sleep 47 ldr r0, =pm_cpu_sleep
61 ldr r0, [ r0 ] 48 ldr r0, [ r0 ]
62 mov pc, r0 49 mov pc, r0
63 50
64resume_with_mmu: 51resume_with_mmu:
65 /*
66 * After MMU is turned on, restore the previous MMU table.
67 */
68 ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
69 add r4, r4, r9
70 str r12, [r4]
71
72 ldmfd sp!, { r3 - r12, pc } 52 ldmfd sp!, { r3 - r12, pc }
73 53
74 .ltorg 54 .ltorg
75 55
76 .data
77
78 .global s3c_sleep_save_phys
79s3c_sleep_save_phys:
80 .word 0
81
82 /* sleep magic, to allow the bootloader to check for an valid 56 /* sleep magic, to allow the bootloader to check for an valid
83 * image to resume to. Must be the first word before the 57 * image to resume to. Must be the first word before the
84 * s3c_cpu_resume entry. 58 * s3c_cpu_resume entry.
@@ -96,75 +70,4 @@ s3c_sleep_save_phys:
96 */ 70 */
97 71
98ENTRY(s3c_cpu_resume) 72ENTRY(s3c_cpu_resume)
99 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 73 b cpu_resume
100 msr cpsr_c, r0
101
102 mov r1, #0
103 mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
104 mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
105
106 ldr r0, s3c_sleep_save_phys @ address of restore block
107 ldmia r0, { r3 - r13 }
108
109 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
110 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
111
112 mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
113 mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
114 mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
115
116 mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
117
118 mov r0, #0
119 mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
120
121 mov r0, #0 @ restore copro access
122 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
123 mcr p15, 0, r0, c7, c5, 4
124
125 mcr p15, 0, r12, c10, c2, 0 @ write PRRR
126 mcr p15, 0, r3, c10, c2, 1 @ write NMRR
127
128 /*
129 * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
130 * And there are no valid entries in the MMU table at this point.
131 * So before turning on the MMU, the MMU entry for the DRAM address
132 * range is added. After the MMU is turned on, the other entries
133 * in the MMU table will be restored.
134 */
135
136 /* r6 = Translation Table BASE0 */
137 mov r4, r6
138 mov r4, r4, LSR #14
139 mov r4, r4, LSL #14
140
141 /* Load address for adding to MMU table list */
142 ldr r11, =0xE010F000 @ INFORM0 reg.
143 ldr r10, [r11, #0]
144 mov r10, r10, LSR #18
145 bic r10, r10, #0x3
146 orr r4, r4, r10
147
148 /* Calculate MMU table entry */
149 mov r10, r10, LSL #18
150 ldr r5, =0x40E
151 orr r10, r10, r5
152
153 /* Back up originally data */
154 ldr r12, [r4]
155
156 /* Add calculated MMU table entry into MMU table list */
157 str r10, [r4]
158
159 ldr r2, =resume_with_mmu
160 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
161
162 nop
163 nop
164 nop
165 nop
166 nop @ second-to-last before mmu
167
168 mov pc, r2 @ go back to virtual address
169
170 .ltorg
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 09:36:46 -0500