diff options
Diffstat (limited to 'arch/arm/mach-s5pv210/mach-goni.c')
| -rw-r--r-- | arch/arm/mach-s5pv210/mach-goni.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 4863b13824e4..1521ea11e8c7 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
| @@ -27,16 +27,16 @@ | |||
| 27 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
| 28 | 28 | ||
| 29 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 29 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 30 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 30 | #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 31 | S3C2410_UCON_RXILEVEL | \ | 31 | S3C2410_UCON_RXILEVEL | \ |
| 32 | S3C2410_UCON_TXIRQMODE | \ | 32 | S3C2410_UCON_TXIRQMODE | \ |
| 33 | S3C2410_UCON_RXIRQMODE | \ | 33 | S3C2410_UCON_RXIRQMODE | \ |
| 34 | S3C2410_UCON_RXFIFO_TOI | \ | 34 | S3C2410_UCON_RXFIFO_TOI | \ |
| 35 | S3C2443_UCON_RXERR_IRQEN) | 35 | S3C2443_UCON_RXERR_IRQEN) |
| 36 | 36 | ||
| 37 | #define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 | 37 | #define GONI_ULCON_DEFAULT S3C2410_LCON_CS8 |
| 38 | 38 | ||
| 39 | #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | 39 | #define GONI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
| 40 | S5PV210_UFCON_TXTRIG4 | \ | 40 | S5PV210_UFCON_TXTRIG4 | \ |
| 41 | S5PV210_UFCON_RXTRIG4) | 41 | S5PV210_UFCON_RXTRIG4) |
| 42 | 42 | ||
| @@ -44,30 +44,30 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { | |||
| 44 | [0] = { | 44 | [0] = { |
| 45 | .hwport = 0, | 45 | .hwport = 0, |
| 46 | .flags = 0, | 46 | .flags = 0, |
| 47 | .ucon = S5PV210_UCON_DEFAULT, | 47 | .ucon = GONI_UCON_DEFAULT, |
| 48 | .ulcon = S5PV210_ULCON_DEFAULT, | 48 | .ulcon = GONI_ULCON_DEFAULT, |
| 49 | .ufcon = S5PV210_UFCON_DEFAULT, | 49 | .ufcon = GONI_UFCON_DEFAULT, |
| 50 | }, | 50 | }, |
| 51 | [1] = { | 51 | [1] = { |
| 52 | .hwport = 1, | 52 | .hwport = 1, |
| 53 | .flags = 0, | 53 | .flags = 0, |
| 54 | .ucon = S5PV210_UCON_DEFAULT, | 54 | .ucon = GONI_UCON_DEFAULT, |
| 55 | .ulcon = S5PV210_ULCON_DEFAULT, | 55 | .ulcon = GONI_ULCON_DEFAULT, |
| 56 | .ufcon = S5PV210_UFCON_DEFAULT, | 56 | .ufcon = GONI_UFCON_DEFAULT, |
| 57 | }, | 57 | }, |
| 58 | [2] = { | 58 | [2] = { |
| 59 | .hwport = 2, | 59 | .hwport = 2, |
| 60 | .flags = 0, | 60 | .flags = 0, |
| 61 | .ucon = S5PV210_UCON_DEFAULT, | 61 | .ucon = GONI_UCON_DEFAULT, |
| 62 | .ulcon = S5PV210_ULCON_DEFAULT, | 62 | .ulcon = GONI_ULCON_DEFAULT, |
| 63 | .ufcon = S5PV210_UFCON_DEFAULT, | 63 | .ufcon = GONI_UFCON_DEFAULT, |
| 64 | }, | 64 | }, |
| 65 | [3] = { | 65 | [3] = { |
| 66 | .hwport = 3, | 66 | .hwport = 3, |
| 67 | .flags = 0, | 67 | .flags = 0, |
| 68 | .ucon = S5PV210_UCON_DEFAULT, | 68 | .ucon = GONI_UCON_DEFAULT, |
| 69 | .ulcon = S5PV210_ULCON_DEFAULT, | 69 | .ulcon = GONI_ULCON_DEFAULT, |
| 70 | .ufcon = S5PV210_UFCON_DEFAULT, | 70 | .ufcon = GONI_UFCON_DEFAULT, |
| 71 | }, | 71 | }, |
| 72 | }; | 72 | }; |
| 73 | 73 | ||