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-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h1
3 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 62c5175ef291..ee6e07b5ae8a 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -143,4 +143,9 @@
143 143
144#define NR_IRQS (IRQ_EINT(31) + 1) 144#define NR_IRQS (IRQ_EINT(31) + 1)
145 145
146/* Compatibility */
147#define IRQ_LCD_FIFO IRQ_LCD0
148#define IRQ_LCD_VSYNC IRQ_LCD1
149#define IRQ_LCD_SYSTEM IRQ_LCD2
150
146#endif /* ASM_ARCH_IRQS_H */ 151#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 5adcb9f26e44..e6bb12c17901 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -47,6 +47,8 @@
47#define S5PV210_PA_PDMA0 0xE0900000 47#define S5PV210_PA_PDMA0 0xE0900000
48#define S5PV210_PA_PDMA1 0xE0A00000 48#define S5PV210_PA_PDMA1 0xE0A00000
49 49
50#define S5PV210_PA_FB (0xF8000000)
51
50#define S5PV210_PA_VIC0 (0xF2000000) 52#define S5PV210_PA_VIC0 (0xF2000000)
51#define S5P_PA_VIC0 S5PV210_PA_VIC0 53#define S5P_PA_VIC0 S5PV210_PA_VIC0
52 54
@@ -78,5 +80,6 @@
78/* compatibiltiy defines. */ 80/* compatibiltiy defines. */
79#define S3C_PA_UART S5PV210_PA_UART 81#define S3C_PA_UART S5PV210_PA_UART
80#define S3C_PA_IIC S5PV210_PA_IIC0 82#define S3C_PA_IIC S5PV210_PA_IIC0
83#define S3C_PA_FB S5PV210_PA_FB
81 84
82#endif /* __ASM_ARCH_MAP_H */ 85#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index e56e0e4673ed..2a25ab40c863 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -126,6 +126,7 @@
126 126
127#define S5P_RST_STAT S5P_CLKREG(0xA000) 127#define S5P_RST_STAT S5P_CLKREG(0xA000)
128#define S5P_OSC_CON S5P_CLKREG(0x8000) 128#define S5P_OSC_CON S5P_CLKREG(0x8000)
129#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
129#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) 130#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
130#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) 131#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
131#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) 132#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814)