diff options
Diffstat (limited to 'arch/arm/mach-s5pv210/clock.c')
-rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ecffafea7f83..7ed1d4e8ae0e 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -116,6 +116,16 @@ static struct clksrc_clk clk_hclk_dsys = { | |||
116 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | 116 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, |
117 | }; | 117 | }; |
118 | 118 | ||
119 | static struct clksrc_clk clk_hclk_psys = { | ||
120 | .clk = { | ||
121 | .name = "hclk_psys", | ||
122 | .id = -1, | ||
123 | }, | ||
124 | .sources = &clkset_hclk_sys, | ||
125 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | ||
126 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | ||
127 | }; | ||
128 | |||
119 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) | 129 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) |
120 | { | 130 | { |
121 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); | 131 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); |
@@ -141,11 +151,6 @@ static struct clk clk_h100 = { | |||
141 | .id = -1, | 151 | .id = -1, |
142 | }; | 152 | }; |
143 | 153 | ||
144 | static struct clk clk_h133 = { | ||
145 | .name = "hclk133", | ||
146 | .id = -1, | ||
147 | }; | ||
148 | |||
149 | static struct clk clk_p100 = { | 154 | static struct clk clk_p100 = { |
150 | .name = "pclk100", | 155 | .name = "pclk100", |
151 | .id = -1, | 156 | .id = -1, |
@@ -163,7 +168,6 @@ static struct clk clk_p66 = { | |||
163 | 168 | ||
164 | static struct clk *sys_clks[] = { | 169 | static struct clk *sys_clks[] = { |
165 | &clk_h100, | 170 | &clk_h100, |
166 | &clk_h133, | ||
167 | &clk_p100, | 171 | &clk_p100, |
168 | &clk_p83, | 172 | &clk_p83, |
169 | &clk_p66 | 173 | &clk_p66 |
@@ -179,13 +183,13 @@ static struct clk init_clocks_disable[] = { | |||
179 | }, { | 183 | }, { |
180 | .name = "otg", | 184 | .name = "otg", |
181 | .id = -1, | 185 | .id = -1, |
182 | .parent = &clk_h133, | 186 | .parent = &clk_hclk_psys.clk, |
183 | .enable = s5pv210_clk_ip1_ctrl, | 187 | .enable = s5pv210_clk_ip1_ctrl, |
184 | .ctrlbit = (1<<16), | 188 | .ctrlbit = (1<<16), |
185 | }, { | 189 | }, { |
186 | .name = "usb-host", | 190 | .name = "usb-host", |
187 | .id = -1, | 191 | .id = -1, |
188 | .parent = &clk_h133, | 192 | .parent = &clk_hclk_psys.clk, |
189 | .enable = s5pv210_clk_ip1_ctrl, | 193 | .enable = s5pv210_clk_ip1_ctrl, |
190 | .ctrlbit = (1<<17), | 194 | .ctrlbit = (1<<17), |
191 | }, { | 195 | }, { |
@@ -197,31 +201,31 @@ static struct clk init_clocks_disable[] = { | |||
197 | }, { | 201 | }, { |
198 | .name = "cfcon", | 202 | .name = "cfcon", |
199 | .id = 0, | 203 | .id = 0, |
200 | .parent = &clk_h133, | 204 | .parent = &clk_hclk_psys.clk, |
201 | .enable = s5pv210_clk_ip1_ctrl, | 205 | .enable = s5pv210_clk_ip1_ctrl, |
202 | .ctrlbit = (1<<25), | 206 | .ctrlbit = (1<<25), |
203 | }, { | 207 | }, { |
204 | .name = "hsmmc", | 208 | .name = "hsmmc", |
205 | .id = 0, | 209 | .id = 0, |
206 | .parent = &clk_h133, | 210 | .parent = &clk_hclk_psys.clk, |
207 | .enable = s5pv210_clk_ip2_ctrl, | 211 | .enable = s5pv210_clk_ip2_ctrl, |
208 | .ctrlbit = (1<<16), | 212 | .ctrlbit = (1<<16), |
209 | }, { | 213 | }, { |
210 | .name = "hsmmc", | 214 | .name = "hsmmc", |
211 | .id = 1, | 215 | .id = 1, |
212 | .parent = &clk_h133, | 216 | .parent = &clk_hclk_psys.clk, |
213 | .enable = s5pv210_clk_ip2_ctrl, | 217 | .enable = s5pv210_clk_ip2_ctrl, |
214 | .ctrlbit = (1<<17), | 218 | .ctrlbit = (1<<17), |
215 | }, { | 219 | }, { |
216 | .name = "hsmmc", | 220 | .name = "hsmmc", |
217 | .id = 2, | 221 | .id = 2, |
218 | .parent = &clk_h133, | 222 | .parent = &clk_hclk_psys.clk, |
219 | .enable = s5pv210_clk_ip2_ctrl, | 223 | .enable = s5pv210_clk_ip2_ctrl, |
220 | .ctrlbit = (1<<18), | 224 | .ctrlbit = (1<<18), |
221 | }, { | 225 | }, { |
222 | .name = "hsmmc", | 226 | .name = "hsmmc", |
223 | .id = 3, | 227 | .id = 3, |
224 | .parent = &clk_h133, | 228 | .parent = &clk_hclk_psys.clk, |
225 | .enable = s5pv210_clk_ip2_ctrl, | 229 | .enable = s5pv210_clk_ip2_ctrl, |
226 | .ctrlbit = (1<<19), | 230 | .ctrlbit = (1<<19), |
227 | }, { | 231 | }, { |
@@ -378,6 +382,7 @@ static struct clksrc_clk *sysclks[] = { | |||
378 | &clk_hclk_msys, | 382 | &clk_hclk_msys, |
379 | &clk_sclk_a2m, | 383 | &clk_sclk_a2m, |
380 | &clk_hclk_dsys, | 384 | &clk_hclk_dsys, |
385 | &clk_hclk_psys, | ||
381 | }; | 386 | }; |
382 | 387 | ||
383 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | 388 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
@@ -389,7 +394,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
389 | unsigned long armclk; | 394 | unsigned long armclk; |
390 | unsigned long hclk_msys; | 395 | unsigned long hclk_msys; |
391 | unsigned long hclk_dsys; | 396 | unsigned long hclk_dsys; |
392 | unsigned long hclk133; | 397 | unsigned long hclk_psys; |
393 | unsigned long pclk100; | 398 | unsigned long pclk100; |
394 | unsigned long pclk83; | 399 | unsigned long pclk83; |
395 | unsigned long pclk66; | 400 | unsigned long pclk66; |
@@ -429,27 +434,22 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
429 | armclk = clk_get_rate(&clk_armclk.clk); | 434 | armclk = clk_get_rate(&clk_armclk.clk); |
430 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); | 435 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
431 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); | 436 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); |
432 | 437 | hclk_psys = clk_get_rate(&clk_hclk_psys.clk); | |
433 | if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) { | ||
434 | hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); | ||
435 | hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); | ||
436 | } else | ||
437 | hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); | ||
438 | 438 | ||
439 | pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); | 439 | pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); |
440 | pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); | 440 | pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); |
441 | pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); | 441 | pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); |
442 | 442 | ||
443 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \ | 443 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" |
444 | HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | 444 | "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", |
445 | armclk, hclk_msys, hclk_dsys, hclk133, pclk100, pclk83, pclk66); | 445 | armclk, hclk_msys, hclk_dsys, hclk_psys, |
446 | pclk100, pclk83, pclk66); | ||
446 | 447 | ||
447 | clk_f.rate = armclk; | 448 | clk_f.rate = armclk; |
448 | clk_h.rate = hclk133; | 449 | clk_h.rate = hclk_psys; |
449 | clk_p.rate = pclk66; | 450 | clk_p.rate = pclk66; |
450 | clk_p66.rate = pclk66; | 451 | clk_p66.rate = pclk66; |
451 | clk_p83.rate = pclk83; | 452 | clk_p83.rate = pclk83; |
452 | clk_h133.rate = hclk133; | ||
453 | 453 | ||
454 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | 454 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
455 | s3c_set_clksrc(&clksrcs[ptr], true); | 455 | s3c_set_clksrc(&clksrcs[ptr], true); |