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-rw-r--r--arch/arm/mach-s5pv210/clock.c217
1 files changed, 133 insertions, 84 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index d8df66887060..c78dfddd77fd 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -400,30 +400,6 @@ static struct clk init_clocks_off[] = {
400 .enable = s5pv210_clk_ip1_ctrl, 400 .enable = s5pv210_clk_ip1_ctrl,
401 .ctrlbit = (1<<25), 401 .ctrlbit = (1<<25),
402 }, { 402 }, {
403 .name = "hsmmc",
404 .devname = "s3c-sdhci.0",
405 .parent = &clk_hclk_psys.clk,
406 .enable = s5pv210_clk_ip2_ctrl,
407 .ctrlbit = (1<<16),
408 }, {
409 .name = "hsmmc",
410 .devname = "s3c-sdhci.1",
411 .parent = &clk_hclk_psys.clk,
412 .enable = s5pv210_clk_ip2_ctrl,
413 .ctrlbit = (1<<17),
414 }, {
415 .name = "hsmmc",
416 .devname = "s3c-sdhci.2",
417 .parent = &clk_hclk_psys.clk,
418 .enable = s5pv210_clk_ip2_ctrl,
419 .ctrlbit = (1<<18),
420 }, {
421 .name = "hsmmc",
422 .devname = "s3c-sdhci.3",
423 .parent = &clk_hclk_psys.clk,
424 .enable = s5pv210_clk_ip2_ctrl,
425 .ctrlbit = (1<<19),
426 }, {
427 .name = "systimer", 403 .name = "systimer",
428 .parent = &clk_pclk_psys.clk, 404 .parent = &clk_pclk_psys.clk,
429 .enable = s5pv210_clk_ip3_ctrl, 405 .enable = s5pv210_clk_ip3_ctrl,
@@ -560,6 +536,38 @@ static struct clk init_clocks[] = {
560 }, 536 },
561}; 537};
562 538
539static struct clk clk_hsmmc0 = {
540 .name = "hsmmc",
541 .devname = "s3c-sdhci.0",
542 .parent = &clk_hclk_psys.clk,
543 .enable = s5pv210_clk_ip2_ctrl,
544 .ctrlbit = (1<<16),
545};
546
547static struct clk clk_hsmmc1 = {
548 .name = "hsmmc",
549 .devname = "s3c-sdhci.1",
550 .parent = &clk_hclk_psys.clk,
551 .enable = s5pv210_clk_ip2_ctrl,
552 .ctrlbit = (1<<17),
553};
554
555static struct clk clk_hsmmc2 = {
556 .name = "hsmmc",
557 .devname = "s3c-sdhci.2",
558 .parent = &clk_hclk_psys.clk,
559 .enable = s5pv210_clk_ip2_ctrl,
560 .ctrlbit = (1<<18),
561};
562
563static struct clk clk_hsmmc3 = {
564 .name = "hsmmc",
565 .devname = "s3c-sdhci.3",
566 .parent = &clk_hclk_psys.clk,
567 .enable = s5pv210_clk_ip2_ctrl,
568 .ctrlbit = (1<<19),
569};
570
563static struct clk *clkset_uart_list[] = { 571static struct clk *clkset_uart_list[] = {
564 [6] = &clk_mout_mpll.clk, 572 [6] = &clk_mout_mpll.clk,
565 [7] = &clk_mout_epll.clk, 573 [7] = &clk_mout_epll.clk,
@@ -867,46 +875,6 @@ static struct clksrc_clk clksrcs[] = {
867 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 875 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
868 }, { 876 }, {
869 .clk = { 877 .clk = {
870 .name = "sclk_mmc",
871 .devname = "s3c-sdhci.0",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 8),
874 },
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
878 }, {
879 .clk = {
880 .name = "sclk_mmc",
881 .devname = "s3c-sdhci.1",
882 .enable = s5pv210_clk_mask0_ctrl,
883 .ctrlbit = (1 << 9),
884 },
885 .sources = &clkset_group2,
886 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
887 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
888 }, {
889 .clk = {
890 .name = "sclk_mmc",
891 .devname = "s3c-sdhci.2",
892 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 10),
894 },
895 .sources = &clkset_group2,
896 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
897 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
898 }, {
899 .clk = {
900 .name = "sclk_mmc",
901 .devname = "s3c-sdhci.3",
902 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 11),
904 },
905 .sources = &clkset_group2,
906 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
907 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
908 }, {
909 .clk = {
910 .name = "sclk_mfc", 878 .name = "sclk_mfc",
911 .devname = "s5p-mfc", 879 .devname = "s5p-mfc",
912 .enable = s5pv210_clk_ip0_ctrl, 880 .enable = s5pv210_clk_ip0_ctrl,
@@ -944,26 +912,6 @@ static struct clksrc_clk clksrcs[] = {
944 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 912 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
945 }, { 913 }, {
946 .clk = { 914 .clk = {
947 .name = "sclk_spi",
948 .devname = "s3c64xx-spi.0",
949 .enable = s5pv210_clk_mask0_ctrl,
950 .ctrlbit = (1 << 16),
951 },
952 .sources = &clkset_group2,
953 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
954 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
955 }, {
956 .clk = {
957 .name = "sclk_spi",
958 .devname = "s3c64xx-spi.1",
959 .enable = s5pv210_clk_mask0_ctrl,
960 .ctrlbit = (1 << 17),
961 },
962 .sources = &clkset_group2,
963 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
964 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
965 }, {
966 .clk = {
967 .name = "sclk_pwi", 915 .name = "sclk_pwi",
968 .enable = s5pv210_clk_mask0_ctrl, 916 .enable = s5pv210_clk_mask0_ctrl,
969 .ctrlbit = (1 << 29), 917 .ctrlbit = (1 << 29),
@@ -1031,11 +979,97 @@ static struct clksrc_clk clk_sclk_uart3 = {
1031 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, 979 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1032}; 980};
1033 981
982static struct clksrc_clk clk_sclk_mmc0 = {
983 .clk = {
984 .name = "sclk_mmc",
985 .devname = "s3c-sdhci.0",
986 .enable = s5pv210_clk_mask0_ctrl,
987 .ctrlbit = (1 << 8),
988 },
989 .sources = &clkset_group2,
990 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
991 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
992};
993
994static struct clksrc_clk clk_sclk_mmc1 = {
995 .clk = {
996 .name = "sclk_mmc",
997 .devname = "s3c-sdhci.1",
998 .enable = s5pv210_clk_mask0_ctrl,
999 .ctrlbit = (1 << 9),
1000 },
1001 .sources = &clkset_group2,
1002 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1003 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1004};
1005
1006static struct clksrc_clk clk_sclk_mmc2 = {
1007 .clk = {
1008 .name = "sclk_mmc",
1009 .devname = "s3c-sdhci.2",
1010 .enable = s5pv210_clk_mask0_ctrl,
1011 .ctrlbit = (1 << 10),
1012 },
1013 .sources = &clkset_group2,
1014 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1015 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1016};
1017
1018static struct clksrc_clk clk_sclk_mmc3 = {
1019 .clk = {
1020 .name = "sclk_mmc",
1021 .devname = "s3c-sdhci.3",
1022 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 11),
1024 },
1025 .sources = &clkset_group2,
1026 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1027 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1028};
1029
1030static struct clksrc_clk clk_sclk_spi0 = {
1031 .clk = {
1032 .name = "sclk_spi",
1033 .devname = "s3c64xx-spi.0",
1034 .enable = s5pv210_clk_mask0_ctrl,
1035 .ctrlbit = (1 << 16),
1036 },
1037 .sources = &clkset_group2,
1038 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1039 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1040 };
1041
1042static struct clksrc_clk clk_sclk_spi1 = {
1043 .clk = {
1044 .name = "sclk_spi",
1045 .devname = "s3c64xx-spi.1",
1046 .enable = s5pv210_clk_mask0_ctrl,
1047 .ctrlbit = (1 << 17),
1048 },
1049 .sources = &clkset_group2,
1050 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1051 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1052 };
1053
1054
1034static struct clksrc_clk *clksrc_cdev[] = { 1055static struct clksrc_clk *clksrc_cdev[] = {
1035 &clk_sclk_uart0, 1056 &clk_sclk_uart0,
1036 &clk_sclk_uart1, 1057 &clk_sclk_uart1,
1037 &clk_sclk_uart2, 1058 &clk_sclk_uart2,
1038 &clk_sclk_uart3, 1059 &clk_sclk_uart3,
1060 &clk_sclk_mmc0,
1061 &clk_sclk_mmc1,
1062 &clk_sclk_mmc2,
1063 &clk_sclk_mmc3,
1064 &clk_sclk_spi0,
1065 &clk_sclk_spi1,
1066};
1067
1068static struct clk *clk_cdev[] = {
1069 &clk_hsmmc0,
1070 &clk_hsmmc1,
1071 &clk_hsmmc2,
1072 &clk_hsmmc3,
1039}; 1073};
1040 1074
1041/* Clock initialisation code */ 1075/* Clock initialisation code */
@@ -1283,6 +1317,17 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1283 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), 1317 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1284 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), 1318 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1285 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), 1319 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1328 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1329 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1330 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1286}; 1331};
1287 1332
1288void __init s5pv210_register_clocks(void) 1333void __init s5pv210_register_clocks(void)
@@ -1307,6 +1352,10 @@ void __init s5pv210_register_clocks(void)
1307 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1352 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1308 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); 1353 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1309 1354
1355 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1356 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1357 s3c_disable_clocks(clk_cdev[ptr], 1);
1358
1310 s3c24xx_register_clock(&dummy_apb_pclk); 1359 s3c24xx_register_clock(&dummy_apb_pclk);
1311 s3c_pwmclk_init(); 1360 s3c_pwmclk_init();
1312} 1361}