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-rw-r--r--arch/arm/mach-s5pv210/clock.c833
1 files changed, 711 insertions, 122 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ccccae262351..154bca4abc09 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,128 @@
31#include <plat/clock-clksrc.h> 31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h> 32#include <plat/s5pv210.h>
33 33
34static struct clksrc_clk clk_mout_apll = {
35 .clk = {
36 .name = "mout_apll",
37 .id = -1,
38 },
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
41};
42
43static struct clksrc_clk clk_mout_epll = {
44 .clk = {
45 .name = "mout_epll",
46 .id = -1,
47 },
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
50};
51
52static struct clksrc_clk clk_mout_mpll = {
53 .clk = {
54 .name = "mout_mpll",
55 .id = -1,
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
61static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
64};
65
66static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
69};
70
71static struct clksrc_clk clk_armclk = {
72 .clk = {
73 .name = "armclk",
74 .id = -1,
75 },
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79};
80
81static struct clksrc_clk clk_hclk_msys = {
82 .clk = {
83 .name = "hclk_msys",
84 .id = -1,
85 .parent = &clk_armclk.clk,
86 },
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
88};
89
90static struct clksrc_clk clk_pclk_msys = {
91 .clk = {
92 .name = "pclk_msys",
93 .id = -1,
94 .parent = &clk_hclk_msys.clk,
95 },
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
97};
98
99static struct clksrc_clk clk_sclk_a2m = {
100 .clk = {
101 .name = "sclk_a2m",
102 .id = -1,
103 .parent = &clk_mout_apll.clk,
104 },
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
106};
107
108static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
111};
112
113static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
116};
117
118static struct clksrc_clk clk_hclk_dsys = {
119 .clk = {
120 .name = "hclk_dsys",
121 .id = -1,
122 },
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
126};
127
128static struct clksrc_clk clk_pclk_dsys = {
129 .clk = {
130 .name = "pclk_dsys",
131 .id = -1,
132 .parent = &clk_hclk_dsys.clk,
133 },
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
135};
136
137static struct clksrc_clk clk_hclk_psys = {
138 .clk = {
139 .name = "hclk_psys",
140 .id = -1,
141 },
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
145};
146
147static struct clksrc_clk clk_pclk_psys = {
148 .clk = {
149 .name = "pclk_psys",
150 .id = -1,
151 .parent = &clk_hclk_psys.clk,
152 },
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
154};
155
34static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) 156static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
35{ 157{
36 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); 158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
@@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
51 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
52} 174}
53 175
54static struct clk clk_h200 = { 176static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
55 .name = "hclk200", 177{
178 return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
179}
180
181static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
182{
183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184}
185
186static struct clk clk_sclk_hdmi27m = {
187 .name = "sclk_hdmi27m",
56 .id = -1, 188 .id = -1,
189 .rate = 27000000,
57}; 190};
58 191
59static struct clk clk_h100 = { 192static struct clk clk_sclk_hdmiphy = {
60 .name = "hclk100", 193 .name = "sclk_hdmiphy",
61 .id = -1, 194 .id = -1,
62}; 195};
63 196
64static struct clk clk_h166 = { 197static struct clk clk_sclk_usbphy0 = {
65 .name = "hclk166", 198 .name = "sclk_usbphy0",
66 .id = -1, 199 .id = -1,
67}; 200};
68 201
69static struct clk clk_h133 = { 202static struct clk clk_sclk_usbphy1 = {
70 .name = "hclk133", 203 .name = "sclk_usbphy1",
71 .id = -1, 204 .id = -1,
72}; 205};
73 206
74static struct clk clk_p100 = { 207static struct clk clk_pcmcdclk0 = {
75 .name = "pclk100", 208 .name = "pcmcdclk",
76 .id = -1, 209 .id = -1,
77}; 210};
78 211
79static struct clk clk_p83 = { 212static struct clk clk_pcmcdclk1 = {
80 .name = "pclk83", 213 .name = "pcmcdclk",
81 .id = -1, 214 .id = -1,
82}; 215};
83 216
84static struct clk clk_p66 = { 217static struct clk clk_pcmcdclk2 = {
85 .name = "pclk66", 218 .name = "pcmcdclk",
86 .id = -1, 219 .id = -1,
87}; 220};
88 221
89static struct clk *sys_clks[] = { 222static struct clk *clkset_vpllsrc_list[] = {
90 &clk_h200, 223 [0] = &clk_fin_vpll,
91 &clk_h100, 224 [1] = &clk_sclk_hdmi27m,
92 &clk_h166, 225};
93 &clk_h133, 226
94 &clk_p100, 227static struct clksrc_sources clkset_vpllsrc = {
95 &clk_p83, 228 .sources = clkset_vpllsrc_list,
96 &clk_p66 229 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
230};
231
232static struct clksrc_clk clk_vpllsrc = {
233 .clk = {
234 .name = "vpll_src",
235 .id = -1,
236 .enable = s5pv210_clk_mask0_ctrl,
237 .ctrlbit = (1 << 7),
238 },
239 .sources = &clkset_vpllsrc,
240 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
241};
242
243static struct clk *clkset_sclk_vpll_list[] = {
244 [0] = &clk_vpllsrc.clk,
245 [1] = &clk_fout_vpll,
246};
247
248static struct clksrc_sources clkset_sclk_vpll = {
249 .sources = clkset_sclk_vpll_list,
250 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
251};
252
253static struct clksrc_clk clk_sclk_vpll = {
254 .clk = {
255 .name = "sclk_vpll",
256 .id = -1,
257 },
258 .sources = &clkset_sclk_vpll,
259 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
260};
261
262static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
263{
264 return clk_get_rate(clk->parent) / 2;
265}
266
267static struct clk_ops clk_hclk_imem_ops = {
268 .get_rate = s5pv210_clk_imem_get_rate,
97}; 269};
98 270
99static struct clk init_clocks_disable[] = { 271static struct clk init_clocks_disable[] = {
100 { 272 {
101 .name = "rot", 273 .name = "rot",
102 .id = -1, 274 .id = -1,
103 .parent = &clk_h166, 275 .parent = &clk_hclk_dsys.clk,
104 .enable = s5pv210_clk_ip0_ctrl, 276 .enable = s5pv210_clk_ip0_ctrl,
105 .ctrlbit = (1<<29), 277 .ctrlbit = (1<<29),
106 }, { 278 }, {
107 .name = "otg", 279 .name = "otg",
108 .id = -1, 280 .id = -1,
109 .parent = &clk_h133, 281 .parent = &clk_hclk_psys.clk,
110 .enable = s5pv210_clk_ip1_ctrl, 282 .enable = s5pv210_clk_ip1_ctrl,
111 .ctrlbit = (1<<16), 283 .ctrlbit = (1<<16),
112 }, { 284 }, {
113 .name = "usb-host", 285 .name = "usb-host",
114 .id = -1, 286 .id = -1,
115 .parent = &clk_h133, 287 .parent = &clk_hclk_psys.clk,
116 .enable = s5pv210_clk_ip1_ctrl, 288 .enable = s5pv210_clk_ip1_ctrl,
117 .ctrlbit = (1<<17), 289 .ctrlbit = (1<<17),
118 }, { 290 }, {
119 .name = "lcd", 291 .name = "lcd",
120 .id = -1, 292 .id = -1,
121 .parent = &clk_h166, 293 .parent = &clk_hclk_dsys.clk,
122 .enable = s5pv210_clk_ip1_ctrl, 294 .enable = s5pv210_clk_ip1_ctrl,
123 .ctrlbit = (1<<0), 295 .ctrlbit = (1<<0),
124 }, { 296 }, {
125 .name = "cfcon", 297 .name = "cfcon",
126 .id = 0, 298 .id = 0,
127 .parent = &clk_h133, 299 .parent = &clk_hclk_psys.clk,
128 .enable = s5pv210_clk_ip1_ctrl, 300 .enable = s5pv210_clk_ip1_ctrl,
129 .ctrlbit = (1<<25), 301 .ctrlbit = (1<<25),
130 }, { 302 }, {
131 .name = "hsmmc", 303 .name = "hsmmc",
132 .id = 0, 304 .id = 0,
133 .parent = &clk_h133, 305 .parent = &clk_hclk_psys.clk,
134 .enable = s5pv210_clk_ip2_ctrl, 306 .enable = s5pv210_clk_ip2_ctrl,
135 .ctrlbit = (1<<16), 307 .ctrlbit = (1<<16),
136 }, { 308 }, {
137 .name = "hsmmc", 309 .name = "hsmmc",
138 .id = 1, 310 .id = 1,
139 .parent = &clk_h133, 311 .parent = &clk_hclk_psys.clk,
140 .enable = s5pv210_clk_ip2_ctrl, 312 .enable = s5pv210_clk_ip2_ctrl,
141 .ctrlbit = (1<<17), 313 .ctrlbit = (1<<17),
142 }, { 314 }, {
143 .name = "hsmmc", 315 .name = "hsmmc",
144 .id = 2, 316 .id = 2,
145 .parent = &clk_h133, 317 .parent = &clk_hclk_psys.clk,
146 .enable = s5pv210_clk_ip2_ctrl, 318 .enable = s5pv210_clk_ip2_ctrl,
147 .ctrlbit = (1<<18), 319 .ctrlbit = (1<<18),
148 }, { 320 }, {
149 .name = "hsmmc", 321 .name = "hsmmc",
150 .id = 3, 322 .id = 3,
151 .parent = &clk_h133, 323 .parent = &clk_hclk_psys.clk,
152 .enable = s5pv210_clk_ip2_ctrl, 324 .enable = s5pv210_clk_ip2_ctrl,
153 .ctrlbit = (1<<19), 325 .ctrlbit = (1<<19),
154 }, { 326 }, {
155 .name = "systimer", 327 .name = "systimer",
156 .id = -1, 328 .id = -1,
157 .parent = &clk_p66, 329 .parent = &clk_pclk_psys.clk,
158 .enable = s5pv210_clk_ip3_ctrl, 330 .enable = s5pv210_clk_ip3_ctrl,
159 .ctrlbit = (1<<16), 331 .ctrlbit = (1<<16),
160 }, { 332 }, {
161 .name = "watchdog", 333 .name = "watchdog",
162 .id = -1, 334 .id = -1,
163 .parent = &clk_p66, 335 .parent = &clk_pclk_psys.clk,
164 .enable = s5pv210_clk_ip3_ctrl, 336 .enable = s5pv210_clk_ip3_ctrl,
165 .ctrlbit = (1<<22), 337 .ctrlbit = (1<<22),
166 }, { 338 }, {
167 .name = "rtc", 339 .name = "rtc",
168 .id = -1, 340 .id = -1,
169 .parent = &clk_p66, 341 .parent = &clk_pclk_psys.clk,
170 .enable = s5pv210_clk_ip3_ctrl, 342 .enable = s5pv210_clk_ip3_ctrl,
171 .ctrlbit = (1<<15), 343 .ctrlbit = (1<<15),
172 }, { 344 }, {
173 .name = "i2c", 345 .name = "i2c",
174 .id = 0, 346 .id = 0,
175 .parent = &clk_p66, 347 .parent = &clk_pclk_psys.clk,
176 .enable = s5pv210_clk_ip3_ctrl, 348 .enable = s5pv210_clk_ip3_ctrl,
177 .ctrlbit = (1<<7), 349 .ctrlbit = (1<<7),
178 }, { 350 }, {
179 .name = "i2c", 351 .name = "i2c",
180 .id = 1, 352 .id = 1,
181 .parent = &clk_p66, 353 .parent = &clk_pclk_psys.clk,
182 .enable = s5pv210_clk_ip3_ctrl, 354 .enable = s5pv210_clk_ip3_ctrl,
183 .ctrlbit = (1<<8), 355 .ctrlbit = (1<<8),
184 }, { 356 }, {
185 .name = "i2c", 357 .name = "i2c",
186 .id = 2, 358 .id = 2,
187 .parent = &clk_p66, 359 .parent = &clk_pclk_psys.clk,
188 .enable = s5pv210_clk_ip3_ctrl, 360 .enable = s5pv210_clk_ip3_ctrl,
189 .ctrlbit = (1<<9), 361 .ctrlbit = (1<<9),
190 }, { 362 }, {
191 .name = "spi", 363 .name = "spi",
192 .id = 0, 364 .id = 0,
193 .parent = &clk_p66, 365 .parent = &clk_pclk_psys.clk,
194 .enable = s5pv210_clk_ip3_ctrl, 366 .enable = s5pv210_clk_ip3_ctrl,
195 .ctrlbit = (1<<12), 367 .ctrlbit = (1<<12),
196 }, { 368 }, {
197 .name = "spi", 369 .name = "spi",
198 .id = 1, 370 .id = 1,
199 .parent = &clk_p66, 371 .parent = &clk_pclk_psys.clk,
200 .enable = s5pv210_clk_ip3_ctrl, 372 .enable = s5pv210_clk_ip3_ctrl,
201 .ctrlbit = (1<<13), 373 .ctrlbit = (1<<13),
202 }, { 374 }, {
203 .name = "spi", 375 .name = "spi",
204 .id = 2, 376 .id = 2,
205 .parent = &clk_p66, 377 .parent = &clk_pclk_psys.clk,
206 .enable = s5pv210_clk_ip3_ctrl, 378 .enable = s5pv210_clk_ip3_ctrl,
207 .ctrlbit = (1<<14), 379 .ctrlbit = (1<<14),
208 }, { 380 }, {
209 .name = "timers", 381 .name = "timers",
210 .id = -1, 382 .id = -1,
211 .parent = &clk_p66, 383 .parent = &clk_pclk_psys.clk,
212 .enable = s5pv210_clk_ip3_ctrl, 384 .enable = s5pv210_clk_ip3_ctrl,
213 .ctrlbit = (1<<23), 385 .ctrlbit = (1<<23),
214 }, { 386 }, {
215 .name = "adc", 387 .name = "adc",
216 .id = -1, 388 .id = -1,
217 .parent = &clk_p66, 389 .parent = &clk_pclk_psys.clk,
218 .enable = s5pv210_clk_ip3_ctrl, 390 .enable = s5pv210_clk_ip3_ctrl,
219 .ctrlbit = (1<<24), 391 .ctrlbit = (1<<24),
220 }, { 392 }, {
221 .name = "keypad", 393 .name = "keypad",
222 .id = -1, 394 .id = -1,
223 .parent = &clk_p66, 395 .parent = &clk_pclk_psys.clk,
224 .enable = s5pv210_clk_ip3_ctrl, 396 .enable = s5pv210_clk_ip3_ctrl,
225 .ctrlbit = (1<<21), 397 .ctrlbit = (1<<21),
226 }, { 398 }, {
@@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = {
246 418
247static struct clk init_clocks[] = { 419static struct clk init_clocks[] = {
248 { 420 {
421 .name = "hclk_imem",
422 .id = -1,
423 .parent = &clk_hclk_msys.clk,
424 .ctrlbit = (1 << 5),
425 .enable = s5pv210_clk_ip0_ctrl,
426 .ops = &clk_hclk_imem_ops,
427 }, {
249 .name = "uart", 428 .name = "uart",
250 .id = 0, 429 .id = 0,
251 .parent = &clk_p66, 430 .parent = &clk_pclk_psys.clk,
252 .enable = s5pv210_clk_ip3_ctrl, 431 .enable = s5pv210_clk_ip3_ctrl,
253 .ctrlbit = (1<<7), 432 .ctrlbit = (1<<7),
254 }, { 433 }, {
255 .name = "uart", 434 .name = "uart",
256 .id = 1, 435 .id = 1,
257 .parent = &clk_p66, 436 .parent = &clk_pclk_psys.clk,
258 .enable = s5pv210_clk_ip3_ctrl, 437 .enable = s5pv210_clk_ip3_ctrl,
259 .ctrlbit = (1<<8), 438 .ctrlbit = (1<<8),
260 }, { 439 }, {
261 .name = "uart", 440 .name = "uart",
262 .id = 2, 441 .id = 2,
263 .parent = &clk_p66, 442 .parent = &clk_pclk_psys.clk,
264 .enable = s5pv210_clk_ip3_ctrl, 443 .enable = s5pv210_clk_ip3_ctrl,
265 .ctrlbit = (1<<9), 444 .ctrlbit = (1<<9),
266 }, { 445 }, {
267 .name = "uart", 446 .name = "uart",
268 .id = 3, 447 .id = 3,
269 .parent = &clk_p66, 448 .parent = &clk_pclk_psys.clk,
270 .enable = s5pv210_clk_ip3_ctrl, 449 .enable = s5pv210_clk_ip3_ctrl,
271 .ctrlbit = (1<<10), 450 .ctrlbit = (1<<10),
272 }, 451 },
273}; 452};
274 453
275static struct clksrc_clk clk_mout_apll = { 454static struct clk *clkset_uart_list[] = {
276 .clk = { 455 [6] = &clk_mout_mpll.clk,
277 .name = "mout_apll", 456 [7] = &clk_mout_epll.clk,
457};
458
459static struct clksrc_sources clkset_uart = {
460 .sources = clkset_uart_list,
461 .nr_sources = ARRAY_SIZE(clkset_uart_list),
462};
463
464static struct clk *clkset_group1_list[] = {
465 [0] = &clk_sclk_a2m.clk,
466 [1] = &clk_mout_mpll.clk,
467 [2] = &clk_mout_epll.clk,
468 [3] = &clk_sclk_vpll.clk,
469};
470
471static struct clksrc_sources clkset_group1 = {
472 .sources = clkset_group1_list,
473 .nr_sources = ARRAY_SIZE(clkset_group1_list),
474};
475
476static struct clk *clkset_sclk_onenand_list[] = {
477 [0] = &clk_hclk_psys.clk,
478 [1] = &clk_hclk_dsys.clk,
479};
480
481static struct clksrc_sources clkset_sclk_onenand = {
482 .sources = clkset_sclk_onenand_list,
483 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
484};
485
486static struct clk *clkset_sclk_dac_list[] = {
487 [0] = &clk_sclk_vpll.clk,
488 [1] = &clk_sclk_hdmiphy,
489};
490
491static struct clksrc_sources clkset_sclk_dac = {
492 .sources = clkset_sclk_dac_list,
493 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
494};
495
496static struct clksrc_clk clk_sclk_dac = {
497 .clk = {
498 .name = "sclk_dac",
278 .id = -1, 499 .id = -1,
500 .ctrlbit = (1 << 10),
501 .enable = s5pv210_clk_ip1_ctrl,
279 }, 502 },
280 .sources = &clk_src_apll, 503 .sources = &clkset_sclk_dac,
281 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 504 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
282}; 505};
283 506
284static struct clksrc_clk clk_mout_epll = { 507static struct clksrc_clk clk_sclk_pixel = {
285 .clk = { 508 .clk = {
286 .name = "mout_epll", 509 .name = "sclk_pixel",
287 .id = -1, 510 .id = -1,
511 .parent = &clk_sclk_vpll.clk,
288 }, 512 },
289 .sources = &clk_src_epll, 513 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
290 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
291}; 514};
292 515
293static struct clksrc_clk clk_mout_mpll = { 516static struct clk *clkset_sclk_hdmi_list[] = {
294 .clk = { 517 [0] = &clk_sclk_pixel.clk,
295 .name = "mout_mpll", 518 [1] = &clk_sclk_hdmiphy,
519};
520
521static struct clksrc_sources clkset_sclk_hdmi = {
522 .sources = clkset_sclk_hdmi_list,
523 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
524};
525
526static struct clksrc_clk clk_sclk_hdmi = {
527 .clk = {
528 .name = "sclk_hdmi",
296 .id = -1, 529 .id = -1,
530 .enable = s5pv210_clk_ip1_ctrl,
531 .ctrlbit = (1 << 11),
297 }, 532 },
298 .sources = &clk_src_mpll, 533 .sources = &clkset_sclk_hdmi,
299 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 534 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
300}; 535};
301 536
302static struct clk *clkset_uart_list[] = { 537static struct clk *clkset_sclk_mixer_list[] = {
538 [0] = &clk_sclk_dac.clk,
539 [1] = &clk_sclk_hdmi.clk,
540};
541
542static struct clksrc_sources clkset_sclk_mixer = {
543 .sources = clkset_sclk_mixer_list,
544 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
545};
546
547static struct clk *clkset_sclk_audio0_list[] = {
548 [0] = &clk_ext_xtal_mux,
549 [1] = &clk_pcmcdclk0,
550 [2] = &clk_sclk_hdmi27m,
551 [3] = &clk_sclk_usbphy0,
552 [4] = &clk_sclk_usbphy1,
553 [5] = &clk_sclk_hdmiphy,
303 [6] = &clk_mout_mpll.clk, 554 [6] = &clk_mout_mpll.clk,
304 [7] = &clk_mout_epll.clk, 555 [7] = &clk_mout_epll.clk,
556 [8] = &clk_sclk_vpll.clk,
305}; 557};
306 558
307static struct clksrc_sources clkset_uart = { 559static struct clksrc_sources clkset_sclk_audio0 = {
308 .sources = clkset_uart_list, 560 .sources = clkset_sclk_audio0_list,
309 .nr_sources = ARRAY_SIZE(clkset_uart_list), 561 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
562};
563
564static struct clksrc_clk clk_sclk_audio0 = {
565 .clk = {
566 .name = "sclk_audio",
567 .id = 0,
568 .enable = s5pv210_clk_ip3_ctrl,
569 .ctrlbit = (1 << 4),
570 },
571 .sources = &clkset_sclk_audio0,
572 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
573 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
574};
575
576static struct clk *clkset_sclk_audio1_list[] = {
577 [0] = &clk_ext_xtal_mux,
578 [1] = &clk_pcmcdclk1,
579 [2] = &clk_sclk_hdmi27m,
580 [3] = &clk_sclk_usbphy0,
581 [4] = &clk_sclk_usbphy1,
582 [5] = &clk_sclk_hdmiphy,
583 [6] = &clk_mout_mpll.clk,
584 [7] = &clk_mout_epll.clk,
585 [8] = &clk_sclk_vpll.clk,
586};
587
588static struct clksrc_sources clkset_sclk_audio1 = {
589 .sources = clkset_sclk_audio1_list,
590 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
591};
592
593static struct clksrc_clk clk_sclk_audio1 = {
594 .clk = {
595 .name = "sclk_audio",
596 .id = 1,
597 .enable = s5pv210_clk_ip3_ctrl,
598 .ctrlbit = (1 << 5),
599 },
600 .sources = &clkset_sclk_audio1,
601 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
602 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
603};
604
605static struct clk *clkset_sclk_audio2_list[] = {
606 [0] = &clk_ext_xtal_mux,
607 [1] = &clk_pcmcdclk0,
608 [2] = &clk_sclk_hdmi27m,
609 [3] = &clk_sclk_usbphy0,
610 [4] = &clk_sclk_usbphy1,
611 [5] = &clk_sclk_hdmiphy,
612 [6] = &clk_mout_mpll.clk,
613 [7] = &clk_mout_epll.clk,
614 [8] = &clk_sclk_vpll.clk,
615};
616
617static struct clksrc_sources clkset_sclk_audio2 = {
618 .sources = clkset_sclk_audio2_list,
619 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
620};
621
622static struct clksrc_clk clk_sclk_audio2 = {
623 .clk = {
624 .name = "sclk_audio",
625 .id = 2,
626 .enable = s5pv210_clk_ip3_ctrl,
627 .ctrlbit = (1 << 6),
628 },
629 .sources = &clkset_sclk_audio2,
630 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
631 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
632};
633
634static struct clk *clkset_sclk_spdif_list[] = {
635 [0] = &clk_sclk_audio0.clk,
636 [1] = &clk_sclk_audio1.clk,
637 [2] = &clk_sclk_audio2.clk,
638};
639
640static struct clksrc_sources clkset_sclk_spdif = {
641 .sources = clkset_sclk_spdif_list,
642 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
643};
644
645static struct clk *clkset_group2_list[] = {
646 [0] = &clk_ext_xtal_mux,
647 [1] = &clk_xusbxti,
648 [2] = &clk_sclk_hdmi27m,
649 [3] = &clk_sclk_usbphy0,
650 [4] = &clk_sclk_usbphy1,
651 [5] = &clk_sclk_hdmiphy,
652 [6] = &clk_mout_mpll.clk,
653 [7] = &clk_mout_epll.clk,
654 [8] = &clk_sclk_vpll.clk,
655};
656
657static struct clksrc_sources clkset_group2 = {
658 .sources = clkset_group2_list,
659 .nr_sources = ARRAY_SIZE(clkset_group2_list),
310}; 660};
311 661
312static struct clksrc_clk clksrcs[] = { 662static struct clksrc_clk clksrcs[] = {
313 { 663 {
314 .clk = { 664 .clk = {
315 .name = "uclk1", 665 .name = "sclk_dmc",
316 .id = -1, 666 .id = -1,
667 },
668 .sources = &clkset_group1,
669 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
670 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
671 }, {
672 .clk = {
673 .name = "sclk_onenand",
674 .id = -1,
675 },
676 .sources = &clkset_sclk_onenand,
677 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
678 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
679 }, {
680 .clk = {
681 .name = "uclk1",
682 .id = 0,
317 .ctrlbit = (1<<17), 683 .ctrlbit = (1<<17),
318 .enable = s5pv210_clk_ip3_ctrl, 684 .enable = s5pv210_clk_ip3_ctrl,
319 }, 685 },
320 .sources = &clkset_uart, 686 .sources = &clkset_uart,
321 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, 687 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
322 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, 688 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
323 } 689 }, {
690 .clk = {
691 .name = "uclk1",
692 .id = 1,
693 .enable = s5pv210_clk_ip3_ctrl,
694 .ctrlbit = (1 << 18),
695 },
696 .sources = &clkset_uart,
697 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
698 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
699 }, {
700 .clk = {
701 .name = "uclk1",
702 .id = 2,
703 .enable = s5pv210_clk_ip3_ctrl,
704 .ctrlbit = (1 << 19),
705 },
706 .sources = &clkset_uart,
707 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
708 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
709 }, {
710 .clk = {
711 .name = "uclk1",
712 .id = 3,
713 .enable = s5pv210_clk_ip3_ctrl,
714 .ctrlbit = (1 << 20),
715 },
716 .sources = &clkset_uart,
717 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
718 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
719 }, {
720 .clk = {
721 .name = "sclk_mixer",
722 .id = -1,
723 .enable = s5pv210_clk_ip1_ctrl,
724 .ctrlbit = (1 << 9),
725 },
726 .sources = &clkset_sclk_mixer,
727 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
728 }, {
729 .clk = {
730 .name = "sclk_spdif",
731 .id = -1,
732 .enable = s5pv210_clk_mask0_ctrl,
733 .ctrlbit = (1 << 27),
734 },
735 .sources = &clkset_sclk_spdif,
736 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
737 }, {
738 .clk = {
739 .name = "sclk_fimc",
740 .id = 0,
741 .enable = s5pv210_clk_ip0_ctrl,
742 .ctrlbit = (1 << 24),
743 },
744 .sources = &clkset_group2,
745 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
746 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
747 }, {
748 .clk = {
749 .name = "sclk_fimc",
750 .id = 1,
751 .enable = s5pv210_clk_ip0_ctrl,
752 .ctrlbit = (1 << 25),
753 },
754 .sources = &clkset_group2,
755 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
756 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
757 }, {
758 .clk = {
759 .name = "sclk_fimc",
760 .id = 2,
761 .enable = s5pv210_clk_ip0_ctrl,
762 .ctrlbit = (1 << 26),
763 },
764 .sources = &clkset_group2,
765 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
766 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
767 }, {
768 .clk = {
769 .name = "sclk_cam",
770 .id = 0,
771 },
772 .sources = &clkset_group2,
773 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_cam",
778 .id = 1,
779 },
780 .sources = &clkset_group2,
781 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
782 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
783 }, {
784 .clk = {
785 .name = "sclk_fimd",
786 .id = -1,
787 .enable = s5pv210_clk_ip1_ctrl,
788 .ctrlbit = (1 << 0),
789 },
790 .sources = &clkset_group2,
791 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
792 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
793 }, {
794 .clk = {
795 .name = "sclk_mmc",
796 .id = 0,
797 .enable = s5pv210_clk_ip2_ctrl,
798 .ctrlbit = (1 << 16),
799 },
800 .sources = &clkset_group2,
801 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
802 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
803 }, {
804 .clk = {
805 .name = "sclk_mmc",
806 .id = 1,
807 .enable = s5pv210_clk_ip2_ctrl,
808 .ctrlbit = (1 << 17),
809 },
810 .sources = &clkset_group2,
811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
812 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
813 }, {
814 .clk = {
815 .name = "sclk_mmc",
816 .id = 2,
817 .enable = s5pv210_clk_ip2_ctrl,
818 .ctrlbit = (1 << 18),
819 },
820 .sources = &clkset_group2,
821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
822 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
823 }, {
824 .clk = {
825 .name = "sclk_mmc",
826 .id = 3,
827 .enable = s5pv210_clk_ip2_ctrl,
828 .ctrlbit = (1 << 19),
829 },
830 .sources = &clkset_group2,
831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
832 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
833 }, {
834 .clk = {
835 .name = "sclk_mfc",
836 .id = -1,
837 .enable = s5pv210_clk_ip0_ctrl,
838 .ctrlbit = (1 << 16),
839 },
840 .sources = &clkset_group1,
841 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
842 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
843 }, {
844 .clk = {
845 .name = "sclk_g2d",
846 .id = -1,
847 .enable = s5pv210_clk_ip0_ctrl,
848 .ctrlbit = (1 << 12),
849 },
850 .sources = &clkset_group1,
851 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
852 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
853 }, {
854 .clk = {
855 .name = "sclk_g3d",
856 .id = -1,
857 .enable = s5pv210_clk_ip0_ctrl,
858 .ctrlbit = (1 << 8),
859 },
860 .sources = &clkset_group1,
861 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
862 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
863 }, {
864 .clk = {
865 .name = "sclk_csis",
866 .id = -1,
867 .enable = s5pv210_clk_ip0_ctrl,
868 .ctrlbit = (1 << 31),
869 },
870 .sources = &clkset_group2,
871 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
872 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
873 }, {
874 .clk = {
875 .name = "sclk_spi",
876 .id = 0,
877 .enable = s5pv210_clk_ip3_ctrl,
878 .ctrlbit = (1 << 12),
879 },
880 .sources = &clkset_group2,
881 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
882 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
883 }, {
884 .clk = {
885 .name = "sclk_spi",
886 .id = 1,
887 .enable = s5pv210_clk_ip3_ctrl,
888 .ctrlbit = (1 << 13),
889 },
890 .sources = &clkset_group2,
891 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
892 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
893 }, {
894 .clk = {
895 .name = "sclk_pwi",
896 .id = -1,
897 .enable = &s5pv210_clk_ip4_ctrl,
898 .ctrlbit = (1 << 2),
899 },
900 .sources = &clkset_group2,
901 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
902 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
903 }, {
904 .clk = {
905 .name = "sclk_pwm",
906 .id = -1,
907 .enable = s5pv210_clk_ip3_ctrl,
908 .ctrlbit = (1 << 23),
909 },
910 .sources = &clkset_group2,
911 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
912 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
913 },
324}; 914};
325 915
326/* Clock initialisation code */ 916/* Clock initialisation code */
327static struct clksrc_clk *init_parents[] = { 917static struct clksrc_clk *sysclks[] = {
328 &clk_mout_apll, 918 &clk_mout_apll,
329 &clk_mout_epll, 919 &clk_mout_epll,
330 &clk_mout_mpll, 920 &clk_mout_mpll,
921 &clk_armclk,
922 &clk_hclk_msys,
923 &clk_sclk_a2m,
924 &clk_hclk_dsys,
925 &clk_hclk_psys,
926 &clk_pclk_msys,
927 &clk_pclk_dsys,
928 &clk_pclk_psys,
929 &clk_vpllsrc,
930 &clk_sclk_vpll,
931 &clk_sclk_dac,
932 &clk_sclk_pixel,
933 &clk_sclk_hdmi,
331}; 934};
332 935
333#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
334
335void __init_or_cpufreq s5pv210_setup_clocks(void) 936void __init_or_cpufreq s5pv210_setup_clocks(void)
336{ 937{
337 struct clk *xtal_clk; 938 struct clk *xtal_clk;
338 unsigned long xtal; 939 unsigned long xtal;
940 unsigned long vpllsrc;
339 unsigned long armclk; 941 unsigned long armclk;
340 unsigned long hclk200; 942 unsigned long hclk_msys;
341 unsigned long hclk166; 943 unsigned long hclk_dsys;
342 unsigned long hclk133; 944 unsigned long hclk_psys;
343 unsigned long pclk100; 945 unsigned long pclk_msys;
344 unsigned long pclk83; 946 unsigned long pclk_dsys;
345 unsigned long pclk66; 947 unsigned long pclk_psys;
346 unsigned long apll; 948 unsigned long apll;
347 unsigned long mpll; 949 unsigned long mpll;
348 unsigned long epll; 950 unsigned long epll;
951 unsigned long vpll;
349 unsigned int ptr; 952 unsigned int ptr;
350 u32 clkdiv0, clkdiv1; 953 u32 clkdiv0, clkdiv1;
351 954
@@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
368 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); 971 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
369 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 972 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
370 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); 973 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
371 974 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
372 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", 975 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
373 apll, mpll, epll);
374
375 armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
376 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
377 hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
378 else
379 hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
380
381 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
382 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
383 hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
384 } else
385 hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
386
387 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
388 hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
389 hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
390 } else
391 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
392
393 pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
394 pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
395 pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
396
397 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
398 HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
399 armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
400 976
401 clk_fout_apll.rate = apll; 977 clk_fout_apll.rate = apll;
402 clk_fout_mpll.rate = mpll; 978 clk_fout_mpll.rate = mpll;
403 clk_fout_epll.rate = epll; 979 clk_fout_epll.rate = epll;
980 clk_fout_vpll.rate = vpll;
404 981
405 clk_f.rate = armclk; 982 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
406 clk_h.rate = hclk133; 983 apll, mpll, epll, vpll);
407 clk_p.rate = pclk66; 984
408 clk_p66.rate = pclk66; 985 armclk = clk_get_rate(&clk_armclk.clk);
409 clk_p83.rate = pclk83; 986 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
410 clk_h133.rate = hclk133; 987 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
411 clk_h166.rate = hclk166; 988 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
412 clk_h200.rate = hclk200; 989 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
990 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
991 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
992
993 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
994 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
995 armclk, hclk_msys, hclk_dsys, hclk_psys,
996 pclk_msys, pclk_dsys, pclk_psys);
413 997
414 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 998 clk_f.rate = armclk;
415 s3c_set_clksrc(init_parents[ptr], true); 999 clk_h.rate = hclk_psys;
1000 clk_p.rate = pclk_psys;
416 1001
417 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 1002 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
418 s3c_set_clksrc(&clksrcs[ptr], true); 1003 s3c_set_clksrc(&clksrcs[ptr], true);
419} 1004}
420 1005
421static struct clk *clks[] __initdata = { 1006static struct clk *clks[] __initdata = {
422 &clk_mout_epll.clk, 1007 &clk_sclk_hdmi27m,
423 &clk_mout_mpll.clk, 1008 &clk_sclk_hdmiphy,
1009 &clk_sclk_usbphy0,
1010 &clk_sclk_usbphy1,
1011 &clk_pcmcdclk0,
1012 &clk_pcmcdclk1,
1013 &clk_pcmcdclk2,
424}; 1014};
425 1015
426void __init s5pv210_register_clocks(void) 1016void __init s5pv210_register_clocks(void)
@@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void)
433 if (ret > 0) 1023 if (ret > 0)
434 printk(KERN_ERR "Failed to register %u clocks\n", ret); 1024 printk(KERN_ERR "Failed to register %u clocks\n", ret);
435 1025
1026 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1027 s3c_register_clksrc(sysclks[ptr], 1);
1028
436 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1029 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
437 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1030 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
438 1031
439 ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
440 if (ret > 0)
441 printk(KERN_ERR "Failed to register system clocks\n");
442
443 clkp = init_clocks_disable; 1032 clkp = init_clocks_disable;
444 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 1033 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
445 ret = s3c24xx_register_clock(clkp); 1034 ret = s3c24xx_register_clock(clkp);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 15:25:42 -0400