aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pc100
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r--arch/arm/mach-s5pc100/Kconfig26
-rw-r--r--arch/arm/mach-s5pc100/Makefile14
-rw-r--r--arch/arm/mach-s5pc100/cpu.c60
-rw-r--r--arch/arm/mach-s5pc100/dev-audio.c287
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c233
-rw-r--r--arch/arm/mach-s5pc100/dma.c167
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c36
-rw-r--r--arch/arm/mach-s5pc100/include/mach/debug-macro.S6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pc100/include/mach/entry-macro.S8
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h102
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h124
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h40
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-irq.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/spi-clocks.h18
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h9
-rw-r--r--arch/arm/mach-s5pc100/include/mach/tick.h4
-rw-r--r--arch/arm/mach-s5pc100/init.c24
-rw-r--r--arch/arm/mach-s5pc100/irq-gpio.c266
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c56
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci-gpio.c86
23 files changed, 1429 insertions, 183 deletions
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 8593337784e1..b2a11dfa3399 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,10 +5,13 @@
5 5
6# Configuration options for the S5PC100 CPU 6# Configuration options for the S5PC100 CPU
7 7
8if ARCH_S5PC100
9
8config CPU_S5PC100 10config CPU_S5PC100
9 bool 11 bool
10 select CPU_S5PC100_INIT 12 select PLAT_S5P
11 select CPU_S5PC100_CLOCK 13 select S5P_EXT_INT
14 select S3C_PL330_DMA
12 help 15 help
13 Enable S5PC100 CPU support 16 Enable S5PC100 CPU support
14 17
@@ -17,17 +20,22 @@ config S5PC100_SETUP_FB_24BPP
17 help 20 help
18 Common setup code for S5PC1XX with an 24bpp RGB display helper. 21 Common setup code for S5PC1XX with an 24bpp RGB display helper.
19 22
20config S5PC100_SETUP_SDHCI
21 bool
22 select S5PC1XX_SETUP_SDHCI_GPIO
23 help
24 Internal helper functions for S5PC100 based SDHCI systems
25
26config S5PC100_SETUP_I2C1 23config S5PC100_SETUP_I2C1
27 bool 24 bool
28 help 25 help
29 Common setup code for i2c bus 1. 26 Common setup code for i2c bus 1.
30 27
28config S5PC100_SETUP_SDHCI
29 bool
30 select S5PC100_SETUP_SDHCI_GPIO
31 help
32 Internal helper functions for S5PC100 based SDHCI systems
33
34config S5PC100_SETUP_SDHCI_GPIO
35 bool
36 help
37 Common setup code for SDHCI gpio.
38
31config MACH_SMDKC100 39config MACH_SMDKC100
32 bool "SMDKC100" 40 bool "SMDKC100"
33 select CPU_S5PC100 41 select CPU_S5PC100
@@ -41,3 +49,5 @@ config MACH_SMDKC100
41 select S5PC100_SETUP_SDHCI 49 select S5PC100_SETUP_SDHCI
42 help 50 help
43 Machine support for the Samsung SMDKC100 51 Machine support for the Samsung SMDKC100
52
53endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 373bc546eae8..543f3de5131e 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,14 +11,24 @@ obj- :=
11 11
12# Core support for S5PC100 system 12# Core support for S5PC100 system
13 13
14obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o 14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o
15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o 15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
16obj-$(CONFIG_CPU_S5PC100) += dma.o
16 17
17# Helper and device support 18# Helper and device support
18 19
19obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o 20obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
20obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
21obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o 22obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
23obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
24
25# device support
26obj-y += dev-audio.o
27obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
22 28
23# machine support 29# machine support
30
24obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o 31obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
32
33# device support
34obj-y += dev-audio.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e7574a852..7b5bdbc9a5df 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,47 +22,55 @@
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25#include <asm/proc-fns.h>
26
27#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 26#include <asm/mach/map.h>
29#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
30 28
29#include <asm/proc-fns.h>
30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/map.h> 32#include <mach/map.h>
33#include <asm/irq.h> 33#include <asm/irq.h>
34 34
35#include <plat/cpu-freq.h>
36#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
37#include <plat/regs-power.h> 36#include <mach/regs-clock.h>
38 37
39#include <plat/cpu.h> 38#include <plat/cpu.h>
40#include <plat/devs.h> 39#include <plat/devs.h>
41#include <plat/clock.h> 40#include <plat/clock.h>
42#include <plat/sdhci.h>
43#include <plat/iic-core.h> 41#include <plat/iic-core.h>
42#include <plat/sdhci.h>
43#include <plat/onenand-core.h>
44
44#include <plat/s5pc100.h> 45#include <plat/s5pc100.h>
45 46
46/* Initial IO mappings */ 47/* Initial IO mappings */
47 48
48static struct map_desc s5pc100_iodesc[] __initdata = { 49static struct map_desc s5pc100_iodesc[] __initdata = {
50 {
51 .virtual = (unsigned long)S5P_VA_SYSTIMER,
52 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
53 .length = SZ_16K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC2,
57 .pfn = __phys_to_pfn(S5P_PA_VIC2),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = (unsigned long)S5PC100_VA_OTHERS,
62 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
63 .length = SZ_4K,
64 .type = MT_DEVICE,
65 }
49}; 66};
50 67
51static void s5pc100_idle(void) 68static void s5pc100_idle(void)
52{ 69{
53 unsigned long tmp; 70 if (!need_resched())
54 71 cpu_do_idle();
55 tmp = __raw_readl(S5PC100_PWR_CFG);
56 tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
57 tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
58 tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
59 __raw_writel(tmp, S5PC100_PWR_CFG);
60
61 tmp = __raw_readl(S5PC100_OTHERS);
62 tmp |= S5PC100_PMU_INT_DISABLE;
63 __raw_writel(tmp, S5PC100_OTHERS);
64 72
65 cpu_do_idle(); 73 local_irq_enable();
66} 74}
67 75
68/* s5pc100_map_io 76/* s5pc100_map_io
@@ -82,26 +90,29 @@ void __init s5pc100_map_io(void)
82 /* the i2c devices are directly compatible with s3c2440 */ 90 /* the i2c devices are directly compatible with s3c2440 */
83 s3c_i2c0_setname("s3c2440-i2c"); 91 s3c_i2c0_setname("s3c2440-i2c");
84 s3c_i2c1_setname("s3c2440-i2c"); 92 s3c_i2c1_setname("s3c2440-i2c");
93
94 s3c_onenand_setname("s5pc100-onenand");
85} 95}
86 96
87void __init s5pc100_init_clocks(int xtal) 97void __init s5pc100_init_clocks(int xtal)
88{ 98{
89 printk(KERN_DEBUG "%s: initialising clocks\n", __func__); 99 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
100
90 s3c24xx_register_baseclocks(xtal); 101 s3c24xx_register_baseclocks(xtal);
91 s5pc1xx_register_clocks(); 102 s5p_register_clocks(xtal);
92 s5pc100_register_clocks(); 103 s5pc100_register_clocks();
93 s5pc100_setup_clocks(); 104 s5pc100_setup_clocks();
94} 105}
95 106
96void __init s5pc100_init_irq(void) 107void __init s5pc100_init_irq(void)
97{ 108{
98 u32 vic_valid[] = {~0, ~0, ~0}; 109 u32 vic[] = {~0, ~0, ~0};
99 110
100 /* VIC0, VIC1, and VIC2 are fully populated. */ 111 /* VIC0, VIC1, and VIC2 are fully populated. */
101 s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid)); 112 s5p_init_irq(vic, ARRAY_SIZE(vic));
102} 113}
103 114
104struct sysdev_class s5pc100_sysclass = { 115static struct sysdev_class s5pc100_sysclass = {
105 .name = "s5pc100-core", 116 .name = "s5pc100-core",
106}; 117};
107 118
@@ -118,9 +129,10 @@ core_initcall(s5pc100_core_init);
118 129
119int __init s5pc100_init(void) 130int __init s5pc100_init(void)
120{ 131{
121 printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); 132 printk(KERN_INFO "S5PC100: Initializing architecture\n");
122 133
123 s5pc1xx_idle = s5pc100_idle; 134 /* set idle function */
135 pm_idle = s5pc100_idle;
124 136
125 return sysdev_register(&s5pc100_sysdev); 137 return sysdev_register(&s5pc100_sysdev);
126} 138}
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
new file mode 100644
index 000000000000..18cfe9ae1936
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -0,0 +1,287 @@
1/* linux/arch/arm/mach-s5pc100/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/audio.h>
16
17#include <mach/gpio.h>
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5pc100_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case 1:
27 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
28 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
29 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
30 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
31 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
32 break;
33
34 case 2:
35 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
36 s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
37 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
38 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
39 s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
40 break;
41
42 case -1: /* Dedicated pins */
43 break;
44
45 default:
46 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
47 return -EINVAL;
48 }
49
50 return 0;
51}
52
53static struct s3c_audio_pdata s3c_i2s_pdata = {
54 .cfg_gpio = s5pc100_cfg_i2s,
55};
56
57static struct resource s5pc100_iis0_resource[] = {
58 [0] = {
59 .start = S5PC100_PA_I2S0,
60 .end = S5PC100_PA_I2S0 + 0x100 - 1,
61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
64 .start = DMACH_I2S0_TX,
65 .end = DMACH_I2S0_TX,
66 .flags = IORESOURCE_DMA,
67 },
68 [2] = {
69 .start = DMACH_I2S0_RX,
70 .end = DMACH_I2S0_RX,
71 .flags = IORESOURCE_DMA,
72 },
73};
74
75struct platform_device s5pc100_device_iis0 = {
76 .name = "s3c64xx-iis-v4",
77 .id = -1,
78 .num_resources = ARRAY_SIZE(s5pc100_iis0_resource),
79 .resource = s5pc100_iis0_resource,
80 .dev = {
81 .platform_data = &s3c_i2s_pdata,
82 },
83};
84
85static struct resource s5pc100_iis1_resource[] = {
86 [0] = {
87 .start = S5PC100_PA_I2S1,
88 .end = S5PC100_PA_I2S1 + 0x100 - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = DMACH_I2S1_TX,
93 .end = DMACH_I2S1_TX,
94 .flags = IORESOURCE_DMA,
95 },
96 [2] = {
97 .start = DMACH_I2S1_RX,
98 .end = DMACH_I2S1_RX,
99 .flags = IORESOURCE_DMA,
100 },
101};
102
103struct platform_device s5pc100_device_iis1 = {
104 .name = "s3c64xx-iis",
105 .id = 1,
106 .num_resources = ARRAY_SIZE(s5pc100_iis1_resource),
107 .resource = s5pc100_iis1_resource,
108 .dev = {
109 .platform_data = &s3c_i2s_pdata,
110 },
111};
112
113static struct resource s5pc100_iis2_resource[] = {
114 [0] = {
115 .start = S5PC100_PA_I2S2,
116 .end = S5PC100_PA_I2S2 + 0x100 - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 [1] = {
120 .start = DMACH_I2S2_TX,
121 .end = DMACH_I2S2_TX,
122 .flags = IORESOURCE_DMA,
123 },
124 [2] = {
125 .start = DMACH_I2S2_RX,
126 .end = DMACH_I2S2_RX,
127 .flags = IORESOURCE_DMA,
128 },
129};
130
131struct platform_device s5pc100_device_iis2 = {
132 .name = "s3c64xx-iis",
133 .id = 2,
134 .num_resources = ARRAY_SIZE(s5pc100_iis2_resource),
135 .resource = s5pc100_iis2_resource,
136 .dev = {
137 .platform_data = &s3c_i2s_pdata,
138 },
139};
140
141/* PCM Controller platform_devices */
142
143static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
144{
145 switch (pdev->id) {
146 case 0:
147 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
148 s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
149 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
150 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
151 s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
152 break;
153
154 case 1:
155 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
156 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
157 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
158 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
159 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
160 break;
161
162 default:
163 printk(KERN_DEBUG "Invalid PCM Controller number!");
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static struct s3c_audio_pdata s3c_pcm_pdata = {
171 .cfg_gpio = s5pc100_pcm_cfg_gpio,
172};
173
174static struct resource s5pc100_pcm0_resource[] = {
175 [0] = {
176 .start = S5PC100_PA_PCM0,
177 .end = S5PC100_PA_PCM0 + 0x100 - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = DMACH_PCM0_TX,
182 .end = DMACH_PCM0_TX,
183 .flags = IORESOURCE_DMA,
184 },
185 [2] = {
186 .start = DMACH_PCM0_RX,
187 .end = DMACH_PCM0_RX,
188 .flags = IORESOURCE_DMA,
189 },
190};
191
192struct platform_device s5pc100_device_pcm0 = {
193 .name = "samsung-pcm",
194 .id = 0,
195 .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource),
196 .resource = s5pc100_pcm0_resource,
197 .dev = {
198 .platform_data = &s3c_pcm_pdata,
199 },
200};
201
202static struct resource s5pc100_pcm1_resource[] = {
203 [0] = {
204 .start = S5PC100_PA_PCM1,
205 .end = S5PC100_PA_PCM1 + 0x100 - 1,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = DMACH_PCM1_TX,
210 .end = DMACH_PCM1_TX,
211 .flags = IORESOURCE_DMA,
212 },
213 [2] = {
214 .start = DMACH_PCM1_RX,
215 .end = DMACH_PCM1_RX,
216 .flags = IORESOURCE_DMA,
217 },
218};
219
220struct platform_device s5pc100_device_pcm1 = {
221 .name = "samsung-pcm",
222 .id = 1,
223 .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource),
224 .resource = s5pc100_pcm1_resource,
225 .dev = {
226 .platform_data = &s3c_pcm_pdata,
227 },
228};
229
230/* AC97 Controller platform devices */
231
232static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
233{
234 s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
235 s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
236 s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
237 s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
238 s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
239
240 return 0;
241}
242
243static struct resource s5pc100_ac97_resource[] = {
244 [0] = {
245 .start = S5PC100_PA_AC97,
246 .end = S5PC100_PA_AC97 + 0x100 - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = DMACH_AC97_PCMOUT,
251 .end = DMACH_AC97_PCMOUT,
252 .flags = IORESOURCE_DMA,
253 },
254 [2] = {
255 .start = DMACH_AC97_PCMIN,
256 .end = DMACH_AC97_PCMIN,
257 .flags = IORESOURCE_DMA,
258 },
259 [3] = {
260 .start = DMACH_AC97_MICIN,
261 .end = DMACH_AC97_MICIN,
262 .flags = IORESOURCE_DMA,
263 },
264 [4] = {
265 .start = IRQ_AC97,
266 .end = IRQ_AC97,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271static struct s3c_audio_pdata s3c_ac97_pdata = {
272 .cfg_gpio = s5pc100_ac97_cfg_gpio,
273};
274
275static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
276
277struct platform_device s5pc100_device_ac97 = {
278 .name = "s3c-ac97",
279 .id = -1,
280 .num_resources = ARRAY_SIZE(s5pc100_ac97_resource),
281 .resource = s5pc100_ac97_resource,
282 .dev = {
283 .platform_data = &s3c_ac97_pdata,
284 .dma_mask = &s5pc100_ac97_dmamask,
285 .coherent_dma_mask = DMA_BIT_MASK(32),
286 },
287};
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
new file mode 100644
index 000000000000..14618c346057
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -0,0 +1,233 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13
14#include <mach/dma.h>
15#include <mach/map.h>
16#include <mach/gpio.h>
17#include <mach/spi-clocks.h>
18
19#include <plat/s3c64xx-spi.h>
20#include <plat/gpio-cfg.h>
21#include <plat/irqs.h>
22
23static char *spi_src_clks[] = {
24 [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
25 [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
26 [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
27};
28
29/* SPI Controller platform_devices */
30
31/* Since we emulate multi-cs capability, we do not touch the CS.
32 * The emulated CS is toggled by board specific mechanism, as it can
33 * be either some immediate GPIO or some signal out of some other
34 * chip in between ... or some yet another way.
35 * We simply do not assume anything about CS.
36 */
37static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
38{
39 switch (pdev->id) {
40 case 0:
41 s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
42 s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
43 s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
44 s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
46 s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
47 break;
48
49 case 1:
50 s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
51 s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
52 s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
53 s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
54 s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
55 s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
56 break;
57
58 case 2:
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
61 s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
62 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
63 s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
64 s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
65 break;
66
67 default:
68 dev_err(&pdev->dev, "Invalid SPI Controller number!");
69 return -EINVAL;
70 }
71
72 return 0;
73}
74
75static struct resource s5pc100_spi0_resource[] = {
76 [0] = {
77 .start = S5PC100_PA_SPI0,
78 .end = S5PC100_PA_SPI0 + 0x100 - 1,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = DMACH_SPI0_TX,
83 .end = DMACH_SPI0_TX,
84 .flags = IORESOURCE_DMA,
85 },
86 [2] = {
87 .start = DMACH_SPI0_RX,
88 .end = DMACH_SPI0_RX,
89 .flags = IORESOURCE_DMA,
90 },
91 [3] = {
92 .start = IRQ_SPI0,
93 .end = IRQ_SPI0,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
99 .cfg_gpio = s5pc100_spi_cfg_gpio,
100 .fifo_lvl_mask = 0x7f,
101 .rx_lvl_offset = 13,
102 .high_speed = 1,
103};
104
105static u64 spi_dmamask = DMA_BIT_MASK(32);
106
107struct platform_device s5pc100_device_spi0 = {
108 .name = "s3c64xx-spi",
109 .id = 0,
110 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
111 .resource = s5pc100_spi0_resource,
112 .dev = {
113 .dma_mask = &spi_dmamask,
114 .coherent_dma_mask = DMA_BIT_MASK(32),
115 .platform_data = &s5pc100_spi0_pdata,
116 },
117};
118
119static struct resource s5pc100_spi1_resource[] = {
120 [0] = {
121 .start = S5PC100_PA_SPI1,
122 .end = S5PC100_PA_SPI1 + 0x100 - 1,
123 .flags = IORESOURCE_MEM,
124 },
125 [1] = {
126 .start = DMACH_SPI1_TX,
127 .end = DMACH_SPI1_TX,
128 .flags = IORESOURCE_DMA,
129 },
130 [2] = {
131 .start = DMACH_SPI1_RX,
132 .end = DMACH_SPI1_RX,
133 .flags = IORESOURCE_DMA,
134 },
135 [3] = {
136 .start = IRQ_SPI1,
137 .end = IRQ_SPI1,
138 .flags = IORESOURCE_IRQ,
139 },
140};
141
142static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
143 .cfg_gpio = s5pc100_spi_cfg_gpio,
144 .fifo_lvl_mask = 0x7f,
145 .rx_lvl_offset = 13,
146 .high_speed = 1,
147};
148
149struct platform_device s5pc100_device_spi1 = {
150 .name = "s3c64xx-spi",
151 .id = 1,
152 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
153 .resource = s5pc100_spi1_resource,
154 .dev = {
155 .dma_mask = &spi_dmamask,
156 .coherent_dma_mask = DMA_BIT_MASK(32),
157 .platform_data = &s5pc100_spi1_pdata,
158 },
159};
160
161static struct resource s5pc100_spi2_resource[] = {
162 [0] = {
163 .start = S5PC100_PA_SPI2,
164 .end = S5PC100_PA_SPI2 + 0x100 - 1,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = DMACH_SPI2_TX,
169 .end = DMACH_SPI2_TX,
170 .flags = IORESOURCE_DMA,
171 },
172 [2] = {
173 .start = DMACH_SPI2_RX,
174 .end = DMACH_SPI2_RX,
175 .flags = IORESOURCE_DMA,
176 },
177 [3] = {
178 .start = IRQ_SPI2,
179 .end = IRQ_SPI2,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
185 .cfg_gpio = s5pc100_spi_cfg_gpio,
186 .fifo_lvl_mask = 0x7f,
187 .rx_lvl_offset = 13,
188 .high_speed = 1,
189};
190
191struct platform_device s5pc100_device_spi2 = {
192 .name = "s3c64xx-spi",
193 .id = 2,
194 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
195 .resource = s5pc100_spi2_resource,
196 .dev = {
197 .dma_mask = &spi_dmamask,
198 .coherent_dma_mask = DMA_BIT_MASK(32),
199 .platform_data = &s5pc100_spi2_pdata,
200 },
201};
202
203void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
204{
205 struct s3c64xx_spi_info *pd;
206
207 /* Reject invalid configuration */
208 if (!num_cs || src_clk_nr < 0
209 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
210 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
211 return;
212 }
213
214 switch (cntrlr) {
215 case 0:
216 pd = &s5pc100_spi0_pdata;
217 break;
218 case 1:
219 pd = &s5pc100_spi1_pdata;
220 break;
221 case 2:
222 pd = &s5pc100_spi2_pdata;
223 break;
224 default:
225 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
226 __func__, cntrlr);
227 return;
228 }
229
230 pd->num_cs = num_cs;
231 pd->src_clk_nr = src_clk_nr;
232 pd->src_clk_name = spi_src_clks[src_clk_nr];
233}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
new file mode 100644
index 000000000000..0f5517571e2c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -0,0 +1,167 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24
25#include <mach/map.h>
26#include <mach/irqs.h>
27
28#include <plat/s3c-pl330-pdata.h>
29
30static u64 dma_dmamask = DMA_BIT_MASK(32);
31
32static struct resource s5pc100_pdma0_resource[] = {
33 [0] = {
34 .start = S5PC100_PA_PDMA0,
35 .end = S5PC100_PA_PDMA0 + SZ_4K,
36 .flags = IORESOURCE_MEM,
37 },
38 [1] = {
39 .start = IRQ_PDMA0,
40 .end = IRQ_PDMA0,
41 .flags = IORESOURCE_IRQ,
42 },
43};
44
45static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
46 .peri = {
47 [0] = DMACH_UART0_RX,
48 [1] = DMACH_UART0_TX,
49 [2] = DMACH_UART1_RX,
50 [3] = DMACH_UART1_TX,
51 [4] = DMACH_UART2_RX,
52 [5] = DMACH_UART2_TX,
53 [6] = DMACH_UART3_RX,
54 [7] = DMACH_UART3_TX,
55 [8] = DMACH_IRDA,
56 [9] = DMACH_I2S0_RX,
57 [10] = DMACH_I2S0_TX,
58 [11] = DMACH_I2S0S_TX,
59 [12] = DMACH_I2S1_RX,
60 [13] = DMACH_I2S1_TX,
61 [14] = DMACH_I2S2_RX,
62 [15] = DMACH_I2S2_TX,
63 [16] = DMACH_SPI0_RX,
64 [17] = DMACH_SPI0_TX,
65 [18] = DMACH_SPI1_RX,
66 [19] = DMACH_SPI1_TX,
67 [20] = DMACH_SPI2_RX,
68 [21] = DMACH_SPI2_TX,
69 [22] = DMACH_AC97_MICIN,
70 [23] = DMACH_AC97_PCMIN,
71 [24] = DMACH_AC97_PCMOUT,
72 [25] = DMACH_EXTERNAL,
73 [26] = DMACH_PWM,
74 [27] = DMACH_SPDIF,
75 [28] = DMACH_HSI_RX,
76 [29] = DMACH_HSI_TX,
77 [30] = DMACH_MAX,
78 [31] = DMACH_MAX,
79 },
80};
81
82static struct platform_device s5pc100_device_pdma0 = {
83 .name = "s3c-pl330",
84 .id = 1,
85 .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource),
86 .resource = s5pc100_pdma0_resource,
87 .dev = {
88 .dma_mask = &dma_dmamask,
89 .coherent_dma_mask = DMA_BIT_MASK(32),
90 .platform_data = &s5pc100_pdma0_pdata,
91 },
92};
93
94static struct resource s5pc100_pdma1_resource[] = {
95 [0] = {
96 .start = S5PC100_PA_PDMA1,
97 .end = S5PC100_PA_PDMA1 + SZ_4K,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = IRQ_PDMA1,
102 .end = IRQ_PDMA1,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
108 .peri = {
109 [0] = DMACH_UART0_RX,
110 [1] = DMACH_UART0_TX,
111 [2] = DMACH_UART1_RX,
112 [3] = DMACH_UART1_TX,
113 [4] = DMACH_UART2_RX,
114 [5] = DMACH_UART2_TX,
115 [6] = DMACH_UART3_RX,
116 [7] = DMACH_UART3_TX,
117 [8] = DMACH_IRDA,
118 [9] = DMACH_I2S0_RX,
119 [10] = DMACH_I2S0_TX,
120 [11] = DMACH_I2S0S_TX,
121 [12] = DMACH_I2S1_RX,
122 [13] = DMACH_I2S1_TX,
123 [14] = DMACH_I2S2_RX,
124 [15] = DMACH_I2S2_TX,
125 [16] = DMACH_SPI0_RX,
126 [17] = DMACH_SPI0_TX,
127 [18] = DMACH_SPI1_RX,
128 [19] = DMACH_SPI1_TX,
129 [20] = DMACH_SPI2_RX,
130 [21] = DMACH_SPI2_TX,
131 [22] = DMACH_PCM0_RX,
132 [23] = DMACH_PCM0_TX,
133 [24] = DMACH_PCM1_RX,
134 [25] = DMACH_PCM1_TX,
135 [26] = DMACH_MSM_REQ0,
136 [27] = DMACH_MSM_REQ1,
137 [28] = DMACH_MSM_REQ2,
138 [29] = DMACH_MSM_REQ3,
139 [30] = DMACH_MAX,
140 [31] = DMACH_MAX,
141 },
142};
143
144static struct platform_device s5pc100_device_pdma1 = {
145 .name = "s3c-pl330",
146 .id = 2,
147 .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource),
148 .resource = s5pc100_pdma1_resource,
149 .dev = {
150 .dma_mask = &dma_dmamask,
151 .coherent_dma_mask = DMA_BIT_MASK(32),
152 .platform_data = &s5pc100_pdma1_pdata,
153 },
154};
155
156static struct platform_device *s5pc100_dmacs[] __initdata = {
157 &s5pc100_device_pdma0,
158 &s5pc100_device_pdma1,
159};
160
161static int __init s5pc100_dma_init(void)
162{
163 platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs));
164
165 return 0;
166}
167arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index c8e8336a3a12..0fab7f2cd8bf 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -1,10 +1,10 @@
1/* 1/*
2 * arch/arm/plat-s5pc1xx/gpiolib.c 2 * arch/arm/plat-s5pc100/gpiolib.c
3 * 3 *
4 * Copyright 2009 Samsung Electronics Co 4 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Kyungmin Park <kyungmin.park@samsung.com>
6 * 6 *
7 * S5PC1XX - GPIOlib support 7 * S5PC100 - GPIOlib support
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -61,13 +61,12 @@
61 * L3 8 4Bit None 61 * L3 8 4Bit None
62 */ 62 */
63 63
64#if 0 64static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
65static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
66{ 65{
67 return S3C_IRQ_GPIO(chip->base + offset); 66 return S3C_IRQ_GPIO(chip->base + offset);
68} 67}
69 68
70static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) 69static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
71{ 70{
72 int base; 71 int base;
73 72
@@ -85,7 +84,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
85 return IRQ_EINT(24 + offset); 84 return IRQ_EINT(24 + offset);
86 return -EINVAL; 85 return -EINVAL;
87} 86}
88#endif 87
89static struct s3c_gpio_cfg gpio_cfg = { 88static struct s3c_gpio_cfg gpio_cfg = {
90 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 89 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
91 .set_pull = s3c_gpio_setpull_updown, 90 .set_pull = s3c_gpio_setpull_updown,
@@ -382,31 +381,30 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
382}; 381};
383 382
384/* FIXME move from irq-gpio.c */ 383/* FIXME move from irq-gpio.c */
385extern struct irq_chip s5pc1xx_gpioint; 384extern struct irq_chip s5pc100_gpioint;
386extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); 385extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
387 386
388static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) 387static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
389{ 388{
390#if 0
391 /* Interrupt */ 389 /* Interrupt */
392 if (chip->config == &gpio_cfg) { 390 if (chip->config == &gpio_cfg) {
393 int i, irq; 391 int i, irq;
394 392
395 chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; 393 chip->chip.to_irq = s5pc100_gpiolib_to_irq;
396 394
397 for (i = 0; i < chip->chip.ngpio; i++) { 395 for (i = 0; i < chip->chip.ngpio; i++) {
398 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; 396 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
399 set_irq_chip(irq, &s5pc1xx_gpioint); 397 set_irq_chip(irq, &s5pc100_gpioint);
400 set_irq_data(irq, &chip->chip); 398 set_irq_data(irq, &chip->chip);
401 set_irq_handler(irq, handle_level_irq); 399 set_irq_handler(irq, handle_level_irq);
402 set_irq_flags(irq, IRQF_VALID); 400 set_irq_flags(irq, IRQF_VALID);
403 } 401 }
404 } else if (chip->config == &gpio_cfg_eint) 402 } else if (chip->config == &gpio_cfg_eint) {
405 chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; 403 chip->chip.to_irq = s5pc100_gpiolib_to_eint;
406#endif 404 }
407} 405}
408 406
409static __init int s5pc1xx_gpiolib_init(void) 407static __init int s5pc100_gpiolib_init(void)
410{ 408{
411 struct s3c_gpio_chip *chip; 409 struct s3c_gpio_chip *chip;
412 int nr_chips; 410 int nr_chips;
@@ -419,10 +417,10 @@ static __init int s5pc1xx_gpiolib_init(void)
419 417
420 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, 418 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
421 ARRAY_SIZE(s5pc100_gpio_chips)); 419 ARRAY_SIZE(s5pc100_gpio_chips));
422#if 0 420
423 /* Interrupt */ 421 /* Interrupt */
424 set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); 422 set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
425#endif 423
426 return 0; 424 return 0;
427} 425}
428core_initcall(s5pc1xx_gpiolib_init); 426core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index e181f5789482..70e02e91ee3c 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,12 +22,14 @@
22 * aligned and add in the offset when we load the value here. 22 * aligned and add in the offset when we load the value here.
23 */ 23 */
24 24
25 .macro addruart, rx, tmp 25 .macro addruart, rx, rtmp
26 mrc p15, 0, \rx, c1, c0 26 mrc p15, 0, \rx, c1, c0
27 tst \rx, #1 27 tst \rx, #1
28 ldreq \rx, = S3C_PA_UART 28 ldreq \rx, = S3C_PA_UART
29 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) 29 ldrne \rx, = S3C_VA_UART
30#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 31 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
32#endif
31 .endm 33 .endm
32 34
33/* include the reset of the code which will do the work, we're only 35/* include the reset of the code which will do the work, we're only
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/dma.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index 67131939e626..ba76af052c81 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -20,7 +20,7 @@
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp 22 .macro get_irqnr_preamble, base, tmp
23 ldr \base, =S3C_VA_VIC0 23 ldr \base, =VA_VIC0
24 .endm 24 .endm
25 25
26 .macro arch_ret_to_user, tmp1, tmp2 26 .macro arch_ret_to_user, tmp1, tmp2
@@ -29,18 +29,18 @@
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30 30
31 @ check the vic0 31 @ check the vic0
32 mov \irqnr, # S3C_IRQ_OFFSET + 31 32 mov \irqnr, # S5P_IRQ_OFFSET + 31
33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] 33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
34 teq \irqstat, #0 34 teq \irqstat, #0
35 35
36 @ otherwise try vic1 36 @ otherwise try vic1
37 addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) 37 addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
38 addeq \irqnr, \irqnr, #32 38 addeq \irqnr, \irqnr, #32
39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
40 teqeq \irqstat, #0 40 teqeq \irqstat, #0
41 41
42 @ otherwise try vic2 42 @ otherwise try vic2
43 addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) 43 addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
44 addeq \irqnr, \irqnr, #32 44 addeq \irqnr, \irqnr, #32
45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
46 teqeq \irqstat, #0 46 teqeq \irqstat, #0
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 29a8a12d9b4f..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
146/* define the number of gpios we need to the one after the MP04() range */ 146/* define the number of gpios we need to the one after the MP04() range */
147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) 147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
148 148
149#define EINT_MODE S3C_GPIO_SFN(0x2)
150
151#define EINT_GPIO_0(x) S5PC100_GPH0(x)
152#define EINT_GPIO_1(x) S5PC100_GPH1(x)
153#define EINT_GPIO_2(x) S5PC100_GPH2(x)
154#define EINT_GPIO_3(x) S5PC100_GPH3(x)
155
149#include <asm-generic/gpio.h> 156#include <asm-generic/gpio.h>
150 157
151#endif /* __ASM_ARCH_GPIO_H */ 158#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index b53fa48a52c6..15066df3ced9 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,9 +11,107 @@
11 11
12#include <plat/irqs.h> 12#include <plat/irqs.h>
13 13
14/* LCD */ 14/* VIC0: system, DMA, timer */
15#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
16#define IRQ_BATF S5P_IRQ_VIC0(17)
17#define IRQ_MDMA S5P_IRQ_VIC0(18)
18#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
19#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
20#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
21#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
22#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
23#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
24#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
25#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
26#define IRQ_WDT S5P_IRQ_VIC0(27)
27#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
28#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30
31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_CORTEX0 S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
36#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
37#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFC S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12)
45#define IRQ_UART3 S5P_IRQ_VIC1(13)
46#define IRQ_IIC S5P_IRQ_VIC1(14)
47#define IRQ_SPI0 S5P_IRQ_VIC1(15)
48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_CAN0 S5P_IRQ_VIC1(19)
52#define IRQ_CAN1 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23)
56#define IRQ_OTG S5P_IRQ_VIC1(24)
57#define IRQ_MSM S5P_IRQ_VIC1(25)
58#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
59#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
60#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
61#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
62#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
63
64/* VIC2: multimedia, audio, security */
65#define IRQ_LCD0 S5P_IRQ_VIC2(0)
66#define IRQ_LCD1 S5P_IRQ_VIC2(1)
67#define IRQ_LCD2 S5P_IRQ_VIC2(2)
68#define IRQ_LCD3 S5P_IRQ_VIC2(3)
69#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
70#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
71#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
72#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
73#define IRQ_JPEG S5P_IRQ_VIC2(8)
74#define IRQ_2D S5P_IRQ_VIC2(9)
75#define IRQ_3D S5P_IRQ_VIC2(10)
76#define IRQ_MIXER S5P_IRQ_VIC2(11)
77#define IRQ_HDMI S5P_IRQ_VIC2(12)
78#define IRQ_IIC1 S5P_IRQ_VIC2(13)
79#define IRQ_MFC S5P_IRQ_VIC2(14)
80#define IRQ_TVENC S5P_IRQ_VIC2(15)
81#define IRQ_I2S0 S5P_IRQ_VIC2(16)
82#define IRQ_I2S1 S5P_IRQ_VIC2(17)
83#define IRQ_I2S2 S5P_IRQ_VIC2(18)
84#define IRQ_AC97 S5P_IRQ_VIC2(19)
85#define IRQ_PCM0 S5P_IRQ_VIC2(20)
86#define IRQ_PCM1 S5P_IRQ_VIC2(21)
87#define IRQ_SPDIF S5P_IRQ_VIC2(22)
88#define IRQ_ADC S5P_IRQ_VIC2(23)
89#define IRQ_PENDN S5P_IRQ_VIC2(24)
90#define IRQ_TC IRQ_PENDN
91#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
92#define IRQ_CG S5P_IRQ_VIC2(26)
93#define IRQ_SEC S5P_IRQ_VIC2(27)
94#define IRQ_SECRX S5P_IRQ_VIC2(28)
95#define IRQ_SECTX S5P_IRQ_VIC2(29)
96#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102
103#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \
104 (S5P_EINT_BASE2 + (x) - 16))
105
106#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
107#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
108
109/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
110#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
111
112/* Compatibility */
15#define IRQ_LCD_FIFO IRQ_LCD0 113#define IRQ_LCD_FIFO IRQ_LCD0
16#define IRQ_LCD_VSYNC IRQ_LCD1 114#define IRQ_LCD_VSYNC IRQ_LCD1
17#define IRQ_LCD_SYSTEM IRQ_LCD2 115#define IRQ_LCD_SYSTEM IRQ_LCD2
18 116
19#endif /* __ASM_ARCH_IRQ_H */ 117#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe8bef6..cadae4305688 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -3,9 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * Based on mach-s3c6400/include/mach/map.h 6 * S5PC100 - Memory map definitions
7 *
8 * S5PC1XX - Memory map definitions
9 * 7 *
10 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,6 +14,7 @@
16#define __ASM_ARCH_MAP_H __FILE__ 14#define __ASM_ARCH_MAP_H __FILE__
17 15
18#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
19 18
20/* 19/*
21 * map-base.h has already defined virtual memory address 20 * map-base.h has already defined virtual memory address
@@ -31,25 +30,21 @@
31 * 30 *
32 */ 31 */
33 32
33#define S5PC100_PA_ONENAND_BUF (0xB0000000)
34#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
35
34/* Chip ID */ 36/* Chip ID */
37
35#define S5PC100_PA_CHIPID (0xE0000000) 38#define S5PC100_PA_CHIPID (0xE0000000)
36#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID 39#define S5P_PA_CHIPID S5PC100_PA_CHIPID
37#define S5PC1XX_VA_CHIPID S3C_VA_SYS 40
38 41#define S5PC100_PA_SYSCON (0xE0100000)
39/* System */ 42#define S5P_PA_SYSCON S5PC100_PA_SYSCON
40#define S5PC100_PA_CLK (0xE0100000) 43
41#define S5PC100_PA_CLK_OTHER (0xE0200000) 44#define S5PC100_PA_OTHERS (0xE0200000)
42#define S5PC100_PA_PWR (0xE0108000) 45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
43#define S5PC1XX_PA_CLK S5PC100_PA_CLK 46
44#define S5PC1XX_PA_PWR S5PC100_PA_PWR 47#define S5P_PA_GPIO (0xE0300000)
45#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
46#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
47#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
48#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
49
50/* GPIO */
51#define S5PC100_PA_GPIO (0xE0300000)
52#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
53#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
54 49
55/* Interrupt */ 50/* Interrupt */
@@ -59,6 +54,12 @@
59#define S5PC100_VA_VIC_OFFSET 0x10000 54#define S5PC100_VA_VIC_OFFSET 0x10000
60#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) 55#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
61#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
58#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
59#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
60
61
62#define S5PC100_PA_ONENAND (0xE7100000)
62 63
63/* DMA */ 64/* DMA */
64#define S5PC100_PA_MDMA (0xE8100000) 65#define S5PC100_PA_MDMA (0xE8100000)
@@ -67,84 +68,71 @@
67 68
68/* Timer */ 69/* Timer */
69#define S5PC100_PA_TIMER (0xEA000000) 70#define S5PC100_PA_TIMER (0xEA000000)
70#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER 71#define S5P_PA_TIMER S5PC100_PA_TIMER
71#define S5PC1XX_VA_TIMER S3C_VA_TIMER
72 72
73/* RTC */ 73#define S5PC100_PA_SYSTIMER (0xEA100000)
74#define S5PC100_PA_RTC (0xEA300000)
75 74
76/* UART */
77#define S5PC100_PA_UART (0xEC000000) 75#define S5PC100_PA_UART (0xEC000000)
78#define S5PC1XX_PA_UART S5PC100_PA_UART
79#define S5PC1XX_VA_UART S3C_VA_UART
80 76
81/* I2C */ 77#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
82#define S5PC100_PA_I2C (0xEC100000) 78#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
83#define S5PC100_PA_I2C1 (0xEC200000) 79#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
80#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
81#define S5P_SZ_UART SZ_256
82
83#define S5PC100_PA_IIC0 (0xEC100000)
84#define S5PC100_PA_IIC1 (0xEC200000)
85
86/* SPI */
87#define S5PC100_PA_SPI0 0xEC300000
88#define S5PC100_PA_SPI1 0xEC400000
89#define S5PC100_PA_SPI2 0xEC500000
84 90
85/* USB HS OTG */ 91/* USB HS OTG */
86#define S5PC100_PA_USB_HSOTG (0xED200000) 92#define S5PC100_PA_USB_HSOTG (0xED200000)
87#define S5PC100_PA_USB_HSPHY (0xED300000) 93#define S5PC100_PA_USB_HSPHY (0xED300000)
88 94
89/* SD/MMC */
90#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
91#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
92#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
93#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
94
95/* LCD */
96#define S5PC100_PA_FB (0xEE000000) 95#define S5PC100_PA_FB (0xEE000000)
97 96
98/* Multimedia */
99#define S5PC100_PA_G2D (0xEE800000)
100#define S5PC100_PA_JPEG (0xEE500000)
101#define S5PC100_PA_ROTATOR (0xEE100000)
102#define S5PC100_PA_G3D (0xEF000000)
103
104/* I2S */
105#define S5PC100_PA_I2S0 (0xF2000000) 97#define S5PC100_PA_I2S0 (0xF2000000)
106#define S5PC100_PA_I2S1 (0xF2100000) 98#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000) 99#define S5PC100_PA_I2S2 (0xF2200000)
108 100
101#define S5PC100_PA_AC97 0xF2300000
102
103/* PCM */
104#define S5PC100_PA_PCM0 0xF2400000
105#define S5PC100_PA_PCM1 0xF2500000
106
109/* KEYPAD */ 107/* KEYPAD */
110#define S5PC100_PA_KEYPAD (0xF3100000) 108#define S5PC100_PA_KEYPAD (0xF3100000)
111 109
112/* ADC & TouchScreen */ 110#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
113#define S5PC100_PA_TSADC (0xF3000000)
114 111
115/* ETC */
116#define S5PC100_PA_SDRAM (0x20000000) 112#define S5PC100_PA_SDRAM (0x20000000)
117#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM 113#define S5P_PA_SDRAM S5PC100_PA_SDRAM
118 114
119/* compatibility defines. */ 115/* compatibiltiy defines. */
120#define S3C_PA_RTC S5PC100_PA_RTC
121#define S3C_PA_UART S5PC100_PA_UART 116#define S3C_PA_UART S5PC100_PA_UART
122#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) 117#define S3C_PA_IIC S5PC100_PA_IIC0
123#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) 118#define S3C_PA_IIC1 S5PC100_PA_IIC1
124#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800)
125#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00)
126#define S3C_VA_UART0 (S3C_VA_UART + 0x0)
127#define S3C_VA_UART1 (S3C_VA_UART + 0x400)
128#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
129#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
130#define S3C_UART_OFFSET 0x400
131#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
132#define S3C_PA_FB S5PC100_PA_FB 119#define S3C_PA_FB S5PC100_PA_FB
133#define S3C_PA_G2D S5PC100_PA_G2D 120#define S3C_PA_G2D S5PC100_PA_G2D
134#define S3C_PA_G3D S5PC100_PA_G3D 121#define S3C_PA_G3D S5PC100_PA_G3D
135#define S3C_PA_JPEG S5PC100_PA_JPEG 122#define S3C_PA_JPEG S5PC100_PA_JPEG
136#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR 123#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
137#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) 124#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
138#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 125#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
139#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) 126#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
140#define S3C_PA_IIC S5PC100_PA_I2C
141#define S3C_PA_IIC1 S5PC100_PA_I2C1
142#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 127#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
143#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 128#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
144#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 129#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
145#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 130#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
146#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 131#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
147#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD 132#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
148#define S3C_PA_TSADC S5PC100_PA_TSADC 133#define S3C_PA_TSADC S5PC100_PA_TSADC
134#define S3C_PA_ONENAND S5PC100_PA_ONENAND
135#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
136#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
149 137
150#endif /* __ASM_ARCH_C100_MAP_H */ 138#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index f2283bdc941e..5d27d286d504 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -17,6 +17,8 @@
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19 19
20#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
21
20#define S5P_APLL_LOCK S5P_CLKREG(0x00) 22#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04) 23#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08) 24#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
@@ -68,4 +70,8 @@
68#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) 70#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
69#define S5P_CLKDIV1_PCLKD1_SHIFT (16) 71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
70 72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74
75#define S5PC100_SWRESET_RESETVAL 0xc100
76
71#endif /* __ASM_ARCH_REGS_CLOCK_H */ 77#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index 68666913354c..763edebdd577 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 1/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
@@ -12,7 +12,7 @@
12#include <mach/map.h> 12#include <mach/map.h>
13 13
14/* S5PC100 */ 14/* S5PC100 */
15#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO 15#define S5PC100_GPIO_BASE S5P_VA_GPIO
16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) 16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) 17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) 18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
@@ -47,24 +47,32 @@
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) 47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) 48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) 49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
51 50
52#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) 51#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
53#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) 52#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
54 53
55/* PDNEN */ 54#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
56#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) 55#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
57#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
58#define S5PC100_PDNEN_POWERDOWN (1 << 0)
59#define S5PC100_PDNEN_NORMAL (0 << 0)
60 56
61/* Common part */ 57#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
62/* External interrupt base is same at both s5pc100 and s5pc110 */ 58#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
63#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
64 59
65#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 60#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
66#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 61#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
67#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 62
63#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) : \
64 (((irq) - S5P_EINT_BASE2)))
65
66#define EINT_REG_NR(x) (eint_offset(x) >> 3)
67
68#define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7))
69
70/* values for S5P_EXTINT0 */
71#define S5P_EXTINT_LOWLEV (0x00)
72#define S5P_EXTINT_HILEV (0x01)
73#define S5P_EXTINT_FALLEDGE (0x02)
74#define S5P_EXTINT_RISEEDGE (0x03)
75#define S5P_EXTINT_BOTHEDGE (0x04)
68 76
69#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ 77#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
70 78
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 751ac15438c8..4d9036d0f288 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - IRQ register definitions 6 * S5PC100 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,9 +16,4 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <asm/hardware/vic.h> 17#include <asm/hardware/vic.h>
18 18
19/* interrupt controller */
20#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0))
21#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1))
22#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2))
23
24#endif /* __ASM_ARCH_REGS_IRQ_H */ 19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..65e426370bb2
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5PC100_PLAT_SPI_CLKS_H
12#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
13
14#define S5PC100_SPI_SRCCLK_PCLK 0
15#define S5PC100_SPI_SRCCLK_48M 1
16#define S5PC100_SPI_SRCCLK_SPIBUS 2
17
18#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index f0d31a2a598c..681f626a9ae1 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - system implementation 6 * S5PC100 - system implementation
7 * 7 *
8 * Based on mach-s3c6400/include/mach/system.h 8 * Based on mach-s3c6400/include/mach/system.h
9 */ 9 */
@@ -13,14 +13,11 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/map.h> 15#include <mach/map.h>
16#include <plat/regs-clock.h> 16#include <mach/regs-clock.h>
17
18void (*s5pc1xx_idle)(void);
19 17
20static void arch_idle(void) 18static void arch_idle(void)
21{ 19{
22 if (s5pc1xx_idle) 20 /* nothing here yet */
23 s5pc1xx_idle();
24} 21}
25 22
26static void arch_reset(char mode, const char *cmd) 23static void arch_reset(char mode, const char *cmd)
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index f338c9eec717..20f68730ed18 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -20,8 +20,8 @@
20 */ 20 */
21static inline u32 s3c24xx_ostimer_pending(void) 21static inline u32 s3c24xx_ostimer_pending(void)
22{ 22{
23 u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); 23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); 24 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
25} 25}
26 26
27#define TICK_MAX (0xffffffff) 27#define TICK_MAX (0xffffffff)
diff --git a/arch/arm/mach-s5pc100/init.c b/arch/arm/mach-s5pc100/init.c
new file mode 100644
index 000000000000..19d7b523c137
--- /dev/null
+++ b/arch/arm/mach-s5pc100/init.c
@@ -0,0 +1,24 @@
1/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/init.h>
15
16#include <plat/cpu.h>
17#include <plat/devs.h>
18#include <plat/s5pc100.h>
19
20/* uart registration process */
21void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
22{
23 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
24}
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
new file mode 100644
index 000000000000..2bf86c18bc73
--- /dev/null
+++ b/arch/arm/mach-s5pc100/irq-gpio.c
@@ -0,0 +1,266 @@
1/*
2 * arch/arm/mach-s5pc100/irq-gpio.c
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 *
6 * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <mach/map.h>
20#include <plat/gpio-cfg.h>
21
22#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
23
24#define CON_OFFSET 0x700
25#define MASK_OFFSET 0x900
26#define PEND_OFFSET 0xA00
27#define CON_OFFSET_2 0xE00
28#define MASK_OFFSET_2 0xF00
29#define PEND_OFFSET_2 0xF40
30
31#define GPIOINT_LEVEL_LOW 0x0
32#define GPIOINT_LEVEL_HIGH 0x1
33#define GPIOINT_EDGE_FALLING 0x2
34#define GPIOINT_EDGE_RISING 0x3
35#define GPIOINT_EDGE_BOTH 0x4
36
37static int group_to_con_offset(int group)
38{
39 return group << 2;
40}
41
42static int group_to_mask_offset(int group)
43{
44 return group << 2;
45}
46
47static int group_to_pend_offset(int group)
48{
49 return group << 2;
50}
51
52static int s5pc100_get_start(unsigned int group)
53{
54 switch (group) {
55 case 0: return S5PC100_GPIO_A0_START;
56 case 1: return S5PC100_GPIO_A1_START;
57 case 2: return S5PC100_GPIO_B_START;
58 case 3: return S5PC100_GPIO_C_START;
59 case 4: return S5PC100_GPIO_D_START;
60 case 5: return S5PC100_GPIO_E0_START;
61 case 6: return S5PC100_GPIO_E1_START;
62 case 7: return S5PC100_GPIO_F0_START;
63 case 8: return S5PC100_GPIO_F1_START;
64 case 9: return S5PC100_GPIO_F2_START;
65 case 10: return S5PC100_GPIO_F3_START;
66 case 11: return S5PC100_GPIO_G0_START;
67 case 12: return S5PC100_GPIO_G1_START;
68 case 13: return S5PC100_GPIO_G2_START;
69 case 14: return S5PC100_GPIO_G3_START;
70 case 15: return S5PC100_GPIO_I_START;
71 case 16: return S5PC100_GPIO_J0_START;
72 case 17: return S5PC100_GPIO_J1_START;
73 case 18: return S5PC100_GPIO_J2_START;
74 case 19: return S5PC100_GPIO_J3_START;
75 case 20: return S5PC100_GPIO_J4_START;
76 default:
77 BUG();
78 }
79
80 return -EINVAL;
81}
82
83static int s5pc100_get_group(unsigned int irq)
84{
85 irq -= S3C_IRQ_GPIO(0);
86
87 switch (irq) {
88 case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
89 return 0;
90 case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
91 return 1;
92 case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
93 return 2;
94 case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
95 return 3;
96 case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
97 return 4;
98 case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
99 return 5;
100 case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
101 return 6;
102 case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
103 return 7;
104 case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
105 return 8;
106 case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
107 return 9;
108 case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
109 return 10;
110 case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
111 return 11;
112 case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
113 return 12;
114 case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
115 return 13;
116 case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
117 return 14;
118 case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
119 return 15;
120 case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
121 return 16;
122 case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
123 return 17;
124 case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
125 return 18;
126 case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
127 return 19;
128 case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
129 return 20;
130 default:
131 BUG();
132 }
133
134 return -EINVAL;
135}
136
137static int s5pc100_get_offset(unsigned int irq)
138{
139 struct gpio_chip *chip = get_irq_data(irq);
140 return irq - S3C_IRQ_GPIO(chip->base);
141}
142
143static void s5pc100_gpioint_ack(unsigned int irq)
144{
145 int group, offset, pend_offset;
146 unsigned int value;
147
148 group = s5pc100_get_group(irq);
149 offset = s5pc100_get_offset(irq);
150 pend_offset = group_to_pend_offset(group);
151
152 value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
153 value |= 1 << offset;
154 __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
155}
156
157static void s5pc100_gpioint_mask(unsigned int irq)
158{
159 int group, offset, mask_offset;
160 unsigned int value;
161
162 group = s5pc100_get_group(irq);
163 offset = s5pc100_get_offset(irq);
164 mask_offset = group_to_mask_offset(group);
165
166 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
167 value |= 1 << offset;
168 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
169}
170
171static void s5pc100_gpioint_unmask(unsigned int irq)
172{
173 int group, offset, mask_offset;
174 unsigned int value;
175
176 group = s5pc100_get_group(irq);
177 offset = s5pc100_get_offset(irq);
178 mask_offset = group_to_mask_offset(group);
179
180 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
181 value &= ~(1 << offset);
182 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
183}
184
185static void s5pc100_gpioint_mask_ack(unsigned int irq)
186{
187 s5pc100_gpioint_mask(irq);
188 s5pc100_gpioint_ack(irq);
189}
190
191static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
192{
193 int group, offset, con_offset;
194 unsigned int value;
195
196 group = s5pc100_get_group(irq);
197 offset = s5pc100_get_offset(irq);
198 con_offset = group_to_con_offset(group);
199
200 switch (type) {
201 case IRQ_TYPE_NONE:
202 printk(KERN_WARNING "No irq type\n");
203 return -EINVAL;
204 case IRQ_TYPE_EDGE_RISING:
205 type = GPIOINT_EDGE_RISING;
206 break;
207 case IRQ_TYPE_EDGE_FALLING:
208 type = GPIOINT_EDGE_FALLING;
209 break;
210 case IRQ_TYPE_EDGE_BOTH:
211 type = GPIOINT_EDGE_BOTH;
212 break;
213 case IRQ_TYPE_LEVEL_HIGH:
214 type = GPIOINT_LEVEL_HIGH;
215 break;
216 case IRQ_TYPE_LEVEL_LOW:
217 type = GPIOINT_LEVEL_LOW;
218 break;
219 default:
220 BUG();
221 }
222
223
224 value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
225 value &= ~(0xf << (offset * 0x4));
226 value |= (type << (offset * 0x4));
227 __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
228
229 return 0;
230}
231
232struct irq_chip s5pc100_gpioint = {
233 .name = "GPIO",
234 .ack = s5pc100_gpioint_ack,
235 .mask = s5pc100_gpioint_mask,
236 .mask_ack = s5pc100_gpioint_mask_ack,
237 .unmask = s5pc100_gpioint_unmask,
238 .set_type = s5pc100_gpioint_set_type,
239};
240
241void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
242{
243 int group, offset, pend_offset, mask_offset;
244 int real_irq, group_end;
245 unsigned int pend, mask;
246
247 group_end = 21;
248
249 for (group = 0; group < group_end; group++) {
250 pend_offset = group_to_pend_offset(group);
251 pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
252 if (!pend)
253 continue;
254
255 mask_offset = group_to_mask_offset(group);
256 mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
257 pend &= ~mask;
258
259 for (offset = 0; offset < 8; offset++) {
260 if (pend & (1 << offset)) {
261 real_irq = s5pc100_get_start(group) + offset;
262 generic_handle_irq(S3C_IRQ_GPIO(real_irq));
263 }
264 }
265 }
266}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index bfe67db34f04..af22f8202a07 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -43,38 +43,48 @@
43#include <plat/fb.h> 43#include <plat/fb.h>
44#include <plat/iic.h> 44#include <plat/iic.h>
45 45
46#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 46/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) 47#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) 48 S3C2410_UCON_RXILEVEL | \
49 S3C2410_UCON_TXIRQMODE | \
50 S3C2410_UCON_RXIRQMODE | \
51 S3C2410_UCON_RXFIFO_TOI | \
52 S3C2443_UCON_RXERR_IRQEN)
53
54#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8
55
56#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
57 S3C2440_UFCON_RXTRIG8 | \
58 S3C2440_UFCON_TXTRIG16)
49 59
50static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
51 [0] = { 61 [0] = {
52 .hwport = 0, 62 .hwport = 0,
53 .flags = 0, 63 .flags = 0,
54 .ucon = 0x3c5, 64 .ucon = S5PC100_UCON_DEFAULT,
55 .ulcon = 0x03, 65 .ulcon = S5PC100_ULCON_DEFAULT,
56 .ufcon = 0x51, 66 .ufcon = S5PC100_UFCON_DEFAULT,
57 }, 67 },
58 [1] = { 68 [1] = {
59 .hwport = 1, 69 .hwport = 1,
60 .flags = 0, 70 .flags = 0,
61 .ucon = 0x3c5, 71 .ucon = S5PC100_UCON_DEFAULT,
62 .ulcon = 0x03, 72 .ulcon = S5PC100_ULCON_DEFAULT,
63 .ufcon = 0x51, 73 .ufcon = S5PC100_UFCON_DEFAULT,
64 }, 74 },
65 [2] = { 75 [2] = {
66 .hwport = 2, 76 .hwport = 2,
67 .flags = 0, 77 .flags = 0,
68 .ucon = 0x3c5, 78 .ucon = S5PC100_UCON_DEFAULT,
69 .ulcon = 0x03, 79 .ulcon = S5PC100_ULCON_DEFAULT,
70 .ufcon = 0x51, 80 .ufcon = S5PC100_UFCON_DEFAULT,
71 }, 81 },
72 [3] = { 82 [3] = {
73 .hwport = 3, 83 .hwport = 3,
74 .flags = 0, 84 .flags = 0,
75 .ucon = 0x3c5, 85 .ucon = S5PC100_UCON_DEFAULT,
76 .ulcon = 0x03, 86 .ulcon = S5PC100_ULCON_DEFAULT,
77 .ufcon = 0x51, 87 .ufcon = S5PC100_UFCON_DEFAULT,
78 }, 88 },
79}; 89};
80 90
@@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = {
118static struct s3c_fb_pd_win smdkc100_fb_win0 = { 128static struct s3c_fb_pd_win smdkc100_fb_win0 = {
119 /* this is to ensure we use win0 */ 129 /* this is to ensure we use win0 */
120 .win_mode = { 130 .win_mode = {
121 .refresh = 70, 131 .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80),
122 .pixclock = (8+13+3+800)*(7+5+1+480),
123 .left_margin = 8, 132 .left_margin = 8,
124 .right_margin = 13, 133 .right_margin = 13,
125 .upper_margin = 7, 134 .upper_margin = 7,
@@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
140 .setup_gpio = s5pc100_fb_gpio_setup_24bpp, 149 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
141}; 150};
142 151
143static struct map_desc smdkc100_iodesc[] = {};
144
145static struct platform_device *smdkc100_devices[] __initdata = { 152static struct platform_device *smdkc100_devices[] __initdata = {
146 &s3c_device_i2c0, 153 &s3c_device_i2c0,
147 &s3c_device_i2c1, 154 &s3c_device_i2c1,
@@ -150,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = {
150 &s3c_device_hsmmc1, 157 &s3c_device_hsmmc1,
151 &s3c_device_hsmmc2, 158 &s3c_device_hsmmc2,
152 &smdkc100_lcd_powerdev, 159 &smdkc100_lcd_powerdev,
160 &s5pc100_device_iis0,
161 &s5pc100_device_ac97,
153}; 162};
154 163
155static void __init smdkc100_map_io(void) 164static void __init smdkc100_map_io(void)
156{ 165{
157 s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); 166 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
158 s3c24xx_init_clocks(12000000); 167 s3c24xx_init_clocks(12000000);
159 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); 168 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
160} 169}
@@ -178,10 +187,9 @@ static void __init smdkc100_machine_init(void)
178 187
179MACHINE_START(SMDKC100, "SMDKC100") 188MACHINE_START(SMDKC100, "SMDKC100")
180 /* Maintainer: Byungho Min <bhmin@samsung.com> */ 189 /* Maintainer: Byungho Min <bhmin@samsung.com> */
181 .phys_io = S5PC100_PA_UART & 0xfff00000, 190 .phys_io = S3C_PA_UART & 0xfff00000,
182 .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, 191 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
183 .boot_params = S5PC100_PA_SDRAM + 0x100, 192 .boot_params = S5P_PA_SDRAM + 0x100,
184
185 .init_irq = s5pc100_init_irq, 193 .init_irq = s5pc100_init_irq,
186 .map_io = smdkc100_map_io, 194 .map_io = smdkc100_map_io,
187 .init_machine = smdkc100_machine_init, 195 .init_machine = smdkc100_machine_init,
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..7769c760c9ef
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
2 *
3 * Copyright 2009 Samsung Eletronics
4 *
5 * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/card.h>
20
21#include <plat/gpio-cfg.h>
22#include <plat/regs-sdhci.h>
23
24void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 unsigned int gpio;
27 unsigned int end;
28 unsigned int num;
29
30 num = width;
31 /* In case of 8 width, we should decrease the 2 */
32 if (width == 8)
33 num = width - 2;
34
35 end = S5PC100_GPG0(2 + num);
36
37 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
38 for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
39 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
40 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
41 }
42
43 if (width == 8) {
44 for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
47 }
48 }
49
50 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
51 s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
52}
53
54void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
55{
56 unsigned int gpio;
57 unsigned int end;
58
59 end = S5PC100_GPG2(2 + width);
60
61 /* Set all the necessary GPG2 pins to special-function 2 */
62 for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
63 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
64 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
65 }
66
67 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
69}
70
71void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
72{
73 unsigned int gpio;
74 unsigned int end;
75
76 end = S5PC100_GPG3(2 + width);
77
78 /* Set all the necessary GPG3 pins to special-function 2 */
79 for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
80 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
81 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
82 }
83
84 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
85 s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
86}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 03:09:48 -0500