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-rw-r--r--arch/arm/mach-s5pc100/Kconfig14
-rw-r--r--arch/arm/mach-s5pc100/Makefile4
-rw-r--r--arch/arm/mach-s5pc100/cpu.c29
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h230
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h87
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-fb.h139
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h13
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c89
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c65
10 files changed, 558 insertions, 117 deletions
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b1a4ba504416..0dd2b8c6eabe 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -14,9 +14,23 @@ config CPU_S5PC100
14 help 14 help
15 Enable S5PC100 CPU support 15 Enable S5PC100 CPU support
16 16
17config S5PC100_SETUP_SDHCI
18 bool
19 select S5PC1XX_SETUP_SDHCI_GPIO
20 help
21 Internal helper functions for S5PC100 based SDHCI systems
22
17config MACH_SMDKC100 23config MACH_SMDKC100
18 bool "SMDKC100" 24 bool "SMDKC100"
19 select CPU_S5PC100 25 select CPU_S5PC100
26 select S3C_DEV_FB
27 select S3C_DEV_I2C1
28 select S3C_DEV_HSMMC
29 select S3C_DEV_HSMMC1
30 select S3C_DEV_HSMMC2
31 select S5PC1XX_SETUP_I2C0
20 select S5PC1XX_SETUP_I2C1 32 select S5PC1XX_SETUP_I2C1
33 select S5PC1XX_SETUP_FB_24BPP
34 select S5PC100_SETUP_SDHCI
21 help 35 help
22 Machine support for the Samsung SMDKC100 36 Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index afc89b381d7a..809ff10f768f 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -13,5 +13,9 @@ obj- :=
13 13
14obj-$(CONFIG_CPU_S5PC100) += cpu.o 14obj-$(CONFIG_CPU_S5PC100) += cpu.o
15 15
16# Helper and device support
17
18obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
19
16# machine support 20# machine support
17obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o 21obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 0e718890da32..d79e7574a852 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,6 +22,8 @@
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25#include <asm/proc-fns.h>
26
25#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 28#include <asm/mach/map.h>
27#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
@@ -32,6 +34,7 @@
32 34
33#include <plat/cpu-freq.h> 35#include <plat/cpu-freq.h>
34#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
37#include <plat/regs-power.h>
35 38
36#include <plat/cpu.h> 39#include <plat/cpu.h>
37#include <plat/devs.h> 40#include <plat/devs.h>
@@ -45,6 +48,23 @@
45static struct map_desc s5pc100_iodesc[] __initdata = { 48static struct map_desc s5pc100_iodesc[] __initdata = {
46}; 49};
47 50
51static void s5pc100_idle(void)
52{
53 unsigned long tmp;
54
55 tmp = __raw_readl(S5PC100_PWR_CFG);
56 tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
57 tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
58 tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
59 __raw_writel(tmp, S5PC100_PWR_CFG);
60
61 tmp = __raw_readl(S5PC100_OTHERS);
62 tmp |= S5PC100_PMU_INT_DISABLE;
63 __raw_writel(tmp, S5PC100_OTHERS);
64
65 cpu_do_idle();
66}
67
48/* s5pc100_map_io 68/* s5pc100_map_io
49 * 69 *
50 * register the standard cpu IO areas 70 * register the standard cpu IO areas
@@ -55,6 +75,13 @@ void __init s5pc100_map_io(void)
55 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); 75 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
56 76
57 /* initialise device information early */ 77 /* initialise device information early */
78 s5pc100_default_sdhci0();
79 s5pc100_default_sdhci1();
80 s5pc100_default_sdhci2();
81
82 /* the i2c devices are directly compatible with s3c2440 */
83 s3c_i2c0_setname("s3c2440-i2c");
84 s3c_i2c1_setname("s3c2440-i2c");
58} 85}
59 86
60void __init s5pc100_init_clocks(int xtal) 87void __init s5pc100_init_clocks(int xtal)
@@ -93,5 +120,7 @@ int __init s5pc100_init(void)
93{ 120{
94 printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); 121 printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
95 122
123 s5pc1xx_idle = s5pc100_idle;
124
96 return sysdev_register(&s5pc100_sysdev); 125 return sysdev_register(&s5pc100_sysdev);
97} 126}
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index c74fc93d7d15..2c4cbe8ee6b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -18,40 +18,45 @@
18#define gpio_to_irq __gpio_to_irq 18#define gpio_to_irq __gpio_to_irq
19 19
20/* GPIO bank sizes */ 20/* GPIO bank sizes */
21#define S5PC1XX_GPIO_A0_NR (8) 21#define S5PC100_GPIO_A0_NR (8)
22#define S5PC1XX_GPIO_A1_NR (5) 22#define S5PC100_GPIO_A1_NR (5)
23#define S5PC1XX_GPIO_B_NR (8) 23#define S5PC100_GPIO_B_NR (8)
24#define S5PC1XX_GPIO_C_NR (5) 24#define S5PC100_GPIO_C_NR (5)
25#define S5PC1XX_GPIO_D_NR (7) 25#define S5PC100_GPIO_D_NR (7)
26#define S5PC1XX_GPIO_E0_NR (8) 26#define S5PC100_GPIO_E0_NR (8)
27#define S5PC1XX_GPIO_E1_NR (6) 27#define S5PC100_GPIO_E1_NR (6)
28#define S5PC1XX_GPIO_F0_NR (8) 28#define S5PC100_GPIO_F0_NR (8)
29#define S5PC1XX_GPIO_F1_NR (8) 29#define S5PC100_GPIO_F1_NR (8)
30#define S5PC1XX_GPIO_F2_NR (8) 30#define S5PC100_GPIO_F2_NR (8)
31#define S5PC1XX_GPIO_F3_NR (4) 31#define S5PC100_GPIO_F3_NR (4)
32#define S5PC1XX_GPIO_G0_NR (8) 32#define S5PC100_GPIO_G0_NR (8)
33#define S5PC1XX_GPIO_G1_NR (3) 33#define S5PC100_GPIO_G1_NR (3)
34#define S5PC1XX_GPIO_G2_NR (7) 34#define S5PC100_GPIO_G2_NR (7)
35#define S5PC1XX_GPIO_G3_NR (7) 35#define S5PC100_GPIO_G3_NR (7)
36#define S5PC1XX_GPIO_H0_NR (8) 36#define S5PC100_GPIO_H0_NR (8)
37#define S5PC1XX_GPIO_H1_NR (8) 37#define S5PC100_GPIO_H1_NR (8)
38#define S5PC1XX_GPIO_H2_NR (8) 38#define S5PC100_GPIO_H2_NR (8)
39#define S5PC1XX_GPIO_H3_NR (8) 39#define S5PC100_GPIO_H3_NR (8)
40#define S5PC1XX_GPIO_I_NR (8) 40#define S5PC100_GPIO_I_NR (8)
41#define S5PC1XX_GPIO_J0_NR (8) 41#define S5PC100_GPIO_J0_NR (8)
42#define S5PC1XX_GPIO_J1_NR (5) 42#define S5PC100_GPIO_J1_NR (5)
43#define S5PC1XX_GPIO_J2_NR (8) 43#define S5PC100_GPIO_J2_NR (8)
44#define S5PC1XX_GPIO_J3_NR (8) 44#define S5PC100_GPIO_J3_NR (8)
45#define S5PC1XX_GPIO_J4_NR (4) 45#define S5PC100_GPIO_J4_NR (4)
46#define S5PC1XX_GPIO_K0_NR (8) 46#define S5PC100_GPIO_K0_NR (8)
47#define S5PC1XX_GPIO_K1_NR (6) 47#define S5PC100_GPIO_K1_NR (6)
48#define S5PC1XX_GPIO_K2_NR (8) 48#define S5PC100_GPIO_K2_NR (8)
49#define S5PC1XX_GPIO_K3_NR (8) 49#define S5PC100_GPIO_K3_NR (8)
50#define S5PC1XX_GPIO_MP00_NR (8) 50#define S5PC100_GPIO_L0_NR (8)
51#define S5PC1XX_GPIO_MP01_NR (8) 51#define S5PC100_GPIO_L1_NR (8)
52#define S5PC1XX_GPIO_MP02_NR (8) 52#define S5PC100_GPIO_L2_NR (8)
53#define S5PC1XX_GPIO_MP03_NR (8) 53#define S5PC100_GPIO_L3_NR (8)
54#define S5PC1XX_GPIO_MP04_NR (5) 54#define S5PC100_GPIO_L4_NR (8)
55#define S5PC100_GPIO_MP00_NR (8)
56#define S5PC100_GPIO_MP01_NR (8)
57#define S5PC100_GPIO_MP02_NR (8)
58#define S5PC100_GPIO_MP03_NR (8)
59#define S5PC100_GPIO_MP04_NR (5)
55 60
56/* GPIO bank numbes */ 61/* GPIO bank numbes */
57 62
@@ -64,83 +69,94 @@
64 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) 69 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
65 70
66enum s3c_gpio_number { 71enum s3c_gpio_number {
67 S5PC1XX_GPIO_A0_START = 0, 72 S5PC100_GPIO_A0_START = 0,
68 S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), 73 S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
69 S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), 74 S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
70 S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), 75 S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
71 S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), 76 S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
72 S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), 77 S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
73 S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), 78 S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
74 S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), 79 S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
75 S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), 80 S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
76 S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), 81 S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
77 S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), 82 S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
78 S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), 83 S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
79 S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), 84 S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
80 S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), 85 S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
81 S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), 86 S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
82 S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), 87 S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
83 S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), 88 S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
84 S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), 89 S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
85 S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), 90 S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
86 S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), 91 S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
87 S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), 92 S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
88 S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), 93 S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
89 S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), 94 S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
90 S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), 95 S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
91 S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), 96 S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
92 S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), 97 S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
93 S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), 98 S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
94 S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), 99 S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
95 S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), 100 S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
96 S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), 101 S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
97 S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), 102 S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
98 S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), 103 S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
99 S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), 104 S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
100 S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), 105 S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
106 S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
107 S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
108 S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
109 S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
110 S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
111 S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
101}; 112};
102 113
103/* S5PC1XX GPIO number definitions. */ 114/* S5PC100 GPIO number definitions. */
104#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) 115#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr))
105#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) 116#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr))
106#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) 117#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr))
107#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) 118#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr))
108#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) 119#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr))
109#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) 120#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr))
110#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) 121#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr))
111#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) 122#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr))
112#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) 123#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr))
113#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) 124#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr))
114#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) 125#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr))
115#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) 126#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr))
116#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) 127#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr))
117#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) 128#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr))
118#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) 129#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr))
119#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) 130#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr))
120#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) 131#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr))
121#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) 132#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr))
122#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) 133#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr))
123#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) 134#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr))
124#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) 135#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr))
125#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) 136#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr))
126#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) 137#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr))
127#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) 138#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr))
128#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) 139#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr))
129#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) 140#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr))
130#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) 141#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr))
131#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) 142#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr))
132#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) 143#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr))
133#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) 144#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr))
134#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) 145#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr))
135#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) 146#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
136#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) 147#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
137#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) 148#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
149#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr))
150#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr))
151#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr))
152#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr))
153#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr))
154#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr))
138 155
139/* the end of the S5PC1XX specific gpios */ 156/* It used the end of the S5PC1XX gpios */
140#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) 157#define S3C_GPIO_END S5PC100_GPIO_END
141#define S3C_GPIO_END S5PC1XX_GPIO_END
142 158
143/* define the number of gpios we need to the one after the MP04() range */ 159/* define the number of gpios we need to the one after the MP04() range */
144#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) 160#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
145 161
146#include <asm-generic/gpio.h> 162#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 622720dba289..b53fa48a52c6 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,4 +11,9 @@
11 11
12#include <plat/irqs.h> 12#include <plat/irqs.h>
13 13
14/* LCD */
15#define IRQ_LCD_FIFO IRQ_LCD0
16#define IRQ_LCD_VSYNC IRQ_LCD1
17#define IRQ_LCD_SYSTEM IRQ_LCD2
18
14#endif /* __ASM_ARCH_IRQ_H */ 19#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 9e9f39130b2c..4681ebe8bef6 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -17,6 +17,19 @@
17 17
18#include <plat/map-base.h> 18#include <plat/map-base.h>
19 19
20/*
21 * map-base.h has already defined virtual memory address
22 * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
23 * S3C_VA_SYS S3C_ADDR(0x00100000) system control
24 * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
25 * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
26 * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
27 * S3C_VA_UART S3C_ADDR(0x01000000) UART
28 *
29 * S5PC100 specific virtual memory address can be defined here
30 * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
31 *
32 */
20 33
21/* Chip ID */ 34/* Chip ID */
22#define S5PC100_PA_CHIPID (0xE0000000) 35#define S5PC100_PA_CHIPID (0xE0000000)
@@ -24,13 +37,20 @@
24#define S5PC1XX_VA_CHIPID S3C_VA_SYS 37#define S5PC1XX_VA_CHIPID S3C_VA_SYS
25 38
26/* System */ 39/* System */
27#define S5PC100_PA_SYS (0xE0100000) 40#define S5PC100_PA_CLK (0xE0100000)
28#define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0) 41#define S5PC100_PA_CLK_OTHER (0xE0200000)
29#define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000) 42#define S5PC100_PA_PWR (0xE0108000)
30#define S5PC1XX_PA_CLK S5PC100_PA_CLK 43#define S5PC1XX_PA_CLK S5PC100_PA_CLK
31#define S5PC1XX_PA_PWR S5PC100_PA_PWR 44#define S5PC1XX_PA_PWR S5PC100_PA_PWR
45#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
32#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) 46#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
33#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) 47#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
48#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
49
50/* GPIO */
51#define S5PC100_PA_GPIO (0xE0300000)
52#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
53#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
34 54
35/* Interrupt */ 55/* Interrupt */
36#define S5PC100_PA_VIC (0xE4000000) 56#define S5PC100_PA_VIC (0xE4000000)
@@ -40,23 +60,64 @@
40#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) 60#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
41#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 61#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
42 62
63/* DMA */
64#define S5PC100_PA_MDMA (0xE8100000)
65#define S5PC100_PA_PDMA0 (0xE9000000)
66#define S5PC100_PA_PDMA1 (0xE9200000)
67
43/* Timer */ 68/* Timer */
44#define S5PC100_PA_TIMER (0xEA000000) 69#define S5PC100_PA_TIMER (0xEA000000)
45#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER 70#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER
46#define S5PC1XX_VA_TIMER S3C_VA_TIMER 71#define S5PC1XX_VA_TIMER S3C_VA_TIMER
47 72
73/* RTC */
74#define S5PC100_PA_RTC (0xEA300000)
75
48/* UART */ 76/* UART */
49#define S5PC100_PA_UART (0xEC000000) 77#define S5PC100_PA_UART (0xEC000000)
50#define S5PC1XX_PA_UART S5PC100_PA_UART 78#define S5PC1XX_PA_UART S5PC100_PA_UART
51#define S5PC1XX_VA_UART S3C_VA_UART 79#define S5PC1XX_VA_UART S3C_VA_UART
52 80
53/* IIC */ 81/* I2C */
54#define S5PC100_PA_IIC (0xEC100000) 82#define S5PC100_PA_I2C (0xEC100000)
83#define S5PC100_PA_I2C1 (0xEC200000)
84
85/* USB HS OTG */
86#define S5PC100_PA_USB_HSOTG (0xED200000)
87#define S5PC100_PA_USB_HSPHY (0xED300000)
88
89/* SD/MMC */
90#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
91#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
92#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
93#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
94
95/* LCD */
96#define S5PC100_PA_FB (0xEE000000)
97
98/* Multimedia */
99#define S5PC100_PA_G2D (0xEE800000)
100#define S5PC100_PA_JPEG (0xEE500000)
101#define S5PC100_PA_ROTATOR (0xEE100000)
102#define S5PC100_PA_G3D (0xEF000000)
103
104/* I2S */
105#define S5PC100_PA_I2S0 (0xF2000000)
106#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000)
108
109/* KEYPAD */
110#define S5PC100_PA_KEYPAD (0xF3100000)
111
112/* ADC & TouchScreen */
113#define S5PC100_PA_TSADC (0xF3000000)
55 114
56/* ETC */ 115/* ETC */
57#define S5PC100_PA_SDRAM (0x20000000) 116#define S5PC100_PA_SDRAM (0x20000000)
117#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM
58 118
59/* compatibility defines. */ 119/* compatibility defines. */
120#define S3C_PA_RTC S5PC100_PA_RTC
60#define S3C_PA_UART S5PC100_PA_UART 121#define S3C_PA_UART S5PC100_PA_UART
61#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) 122#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0)
62#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) 123#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400)
@@ -67,9 +128,23 @@
67#define S3C_VA_UART2 (S3C_VA_UART + 0x800) 128#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
68#define S3C_VA_UART3 (S3C_VA_UART + 0xC00) 129#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
69#define S3C_UART_OFFSET 0x400 130#define S3C_UART_OFFSET 0x400
131#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
132#define S3C_PA_FB S5PC100_PA_FB
133#define S3C_PA_G2D S5PC100_PA_G2D
134#define S3C_PA_G3D S5PC100_PA_G3D
135#define S3C_PA_JPEG S5PC100_PA_JPEG
136#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
70#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) 137#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0)
71#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 138#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
72#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) 139#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
73#define S3C_PA_IIC S5PC100_PA_IIC 140#define S3C_PA_IIC S5PC100_PA_I2C
141#define S3C_PA_IIC1 S5PC100_PA_I2C1
142#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
143#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
144#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0
145#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1
146#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2
147#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
148#define S3C_PA_TSADC S5PC100_PA_TSADC
74 149
75#endif /* __ASM_ARCH_C100_MAP_H */ 150#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
new file mode 100644
index 000000000000..1732cd28c765
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -0,0 +1,139 @@
1/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Pawel Osciak <p.osciak@samsung.com>
5 *
6 * Framebuffer register definitions for Samsung S5PC100.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_FB_H
14#define __ASM_ARCH_REGS_FB_H __FILE__
15
16#include <plat/regs-fb-v4.h>
17
18/* VP1 interface timing control */
19#define VP1CON0 (0x118)
20#define VP1_RATECON_EN (1 << 31)
21#define VP1_CLKRATE_MASK (0xff)
22
23#define VP1CON1 (0x11c)
24#define VP1_VTREGCON_EN (1 << 31)
25#define VP1_VBPD_MASK (0xfff)
26#define VP1_VBPD_SHIFT (16)
27
28
29#define WPALCON_H (0x19c)
30#define WPALCON_L (0x1a0)
31
32/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
33 * different for WPAL2-4
34 */
35/* In WPALCON_L (aka WPALCON) */
36#define WPALCON_W1PAL_32BPP_A888 (0x7 << 3)
37#define WPALCON_W0PAL_32BPP_A888 (0x7 << 0)
38
39/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
40 * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
41 */
42#define WPALCON_L_WxPAL_L_MASK (0x1)
43#define WPALCON_L_W2PAL_L_SHIFT (6)
44#define WPALCON_L_W3PAL_L_SHIFT (7)
45#define WPALCON_L_W4PAL_L_SHIFT (8)
46
47#define WPALCON_L_WxPAL_H_MASK (0x3)
48#define WPALCON_H_W2PAL_H_SHIFT (9)
49#define WPALCON_H_W3PAL_H_SHIFT (13)
50#define WPALCON_H_W4PAL_H_SHIFT (17)
51
52/* Per-window alpha value registers */
53/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
54 * for windows 1-4 alpha values consist of two parts, the 4 low bits are
55 * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
56 * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
57 */
58#define VIDWxALPHA0(_win) (0x200 + (_win * 8))
59#define VIDWxALPHA1(_win) (0x204 + (_win * 8))
60
61/* Only for window 0 in VIDW0ALPHAx. */
62#define VIDW0ALPHAx_R(_x) ((_x) << 16)
63#define VIDW0ALPHAx_R_MASK (0xff << 16)
64#define VIDW0ALPHAx_R_SHIFT (16)
65#define VIDW0ALPHAx_G(_x) ((_x) << 8)
66#define VIDW0ALPHAx_G_MASK (0xff << 8)
67#define VIDW0ALPHAx_G_SHIFT (8)
68#define VIDW0ALPHAx_B(_x) ((_x) << 0)
69#define VIDW0ALPHAx_B_MASK (0xff << 0)
70#define VIDW0ALPHAx_B_SHIFT (0)
71
72/* Low 4 bits of alpha0-1 for windows 1-4 */
73#define VIDW14ALPHAx_R_L(_x) ((_x) << 16)
74#define VIDW14ALPHAx_R_L_MASK (0xf << 16)
75#define VIDW14ALPHAx_R_L_SHIFT (16)
76#define VIDW14ALPHAx_G_L(_x) ((_x) << 8)
77#define VIDW14ALPHAx_G_L_MASK (0xf << 8)
78#define VIDW14ALPHAx_G_L_SHIFT (8)
79#define VIDW14ALPHAx_B_L(_x) ((_x) << 0)
80#define VIDW14ALPHAx_B_L_MASK (0xf << 0)
81#define VIDW14ALPHAx_B_L_SHIFT (0)
82
83
84/* Per-window blending equation control registers */
85#define BLENDEQx(_win) (0x244 + ((_win) * 4))
86#define BLENDEQ1 (0x244)
87#define BLENDEQ2 (0x248)
88#define BLENDEQ3 (0x24c)
89#define BLENDEQ4 (0x250)
90
91#define BLENDEQx_Q_FUNC(_x) ((_x) << 18)
92#define BLENDEQx_Q_FUNC_MASK (0xf << 18)
93#define BLENDEQx_P_FUNC(_x) ((_x) << 12)
94#define BLENDEQx_P_FUNC_MASK (0xf << 12)
95#define BLENDEQx_B_FUNC(_x) ((_x) << 6)
96#define BLENDEQx_B_FUNC_MASK (0xf << 6)
97#define BLENDEQx_A_FUNC(_x) ((_x) << 0)
98#define BLENDEQx_A_FUNC_MASK (0xf << 0)
99
100#define BLENDCON (0x260)
101#define BLENDCON_8BIT_ALPHA (1 << 0)
102
103/* Per-window palette base addresses (start of palette memory).
104 * Each window palette area consists of 256 32-bit entries.
105 * START is the first address (entry 0th), END is the address of 255th entry.
106 */
107#define WIN0_PAL_BASE (0x2400)
108#define WIN0_PAL_END (0x27fc)
109#define WIN1_PAL_BASE (0x2800)
110#define WIN1_PAL_END (0x2bfc)
111#define WIN2_PAL_BASE (0x2c00)
112#define WIN2_PAL_END (0x2ffc)
113#define WIN3_PAL_BASE (0x3000)
114#define WIN3_PAL_END (0x33fc)
115#define WIN4_PAL_BASE (0x3400)
116#define WIN4_PAL_END (0x37fc)
117
118#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4))
119#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4))
120#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4))
121#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4))
122#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4))
123
124static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
125{
126 switch (window) {
127 case 0: return WIN0_PAL(reg);
128 case 1: return WIN1_PAL(reg);
129 case 2: return WIN2_PAL(reg);
130 case 3: return WIN3_PAL(reg);
131 case 4: return WIN4_PAL(reg);
132 }
133
134 BUG();
135}
136
137
138#endif /* __ASM_ARCH_REGS_FB_H */
139
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index e39014375470..f0d31a2a598c 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,14 +11,21 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__ 12#define __ASM_ARCH_SYSTEM_H __FILE__
13 13
14#include <linux/io.h>
15#include <mach/map.h>
16#include <plat/regs-clock.h>
17
18void (*s5pc1xx_idle)(void);
19
14static void arch_idle(void) 20static void arch_idle(void)
15{ 21{
16 /* nothing here yet */ 22 if (s5pc1xx_idle)
23 s5pc1xx_idle();
17} 24}
18 25
19static void arch_reset(char mode, const char *cmd) 26static void arch_reset(char mode, const char *cmd)
20{ 27{
21 /* nothing here yet */ 28 __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
29 return;
22} 30}
23
24#endif /* __ASM_ARCH_IRQ_H */ 31#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 214093cd7632..ae3c52cd0ebb 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -27,16 +27,22 @@
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28 28
29#include <mach/map.h> 29#include <mach/map.h>
30#include <mach/regs-fb.h>
31#include <video/platform_lcd.h>
30 32
31#include <asm/irq.h> 33#include <asm/irq.h>
32#include <asm/mach-types.h> 34#include <asm/mach-types.h>
33 35
34#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
37#include <plat/gpio-cfg.h>
38#include <plat/regs-gpio.h>
35 39
36#include <plat/clock.h> 40#include <plat/clock.h>
37#include <plat/devs.h> 41#include <plat/devs.h>
38#include <plat/cpu.h> 42#include <plat/cpu.h>
39#include <plat/s5pc100.h> 43#include <plat/s5pc100.h>
44#include <plat/fb.h>
45#include <plat/iic.h>
40 46
41#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 47#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
42#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) 48#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -73,9 +79,78 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
73 }, 79 },
74}; 80};
75 81
82/* I2C0 */
83static struct i2c_board_info i2c_devs0[] __initdata = {
84};
85
86/* I2C1 */
87static struct i2c_board_info i2c_devs1[] __initdata = {
88};
89
90/* LCD power controller */
91static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
92 unsigned int power)
93{
94 /* backlight */
95 gpio_direction_output(S5PC100_GPD(0), power);
96
97 if (power) {
98 /* module reset */
99 gpio_direction_output(S5PC100_GPH0(6), 1);
100 mdelay(100);
101 gpio_direction_output(S5PC100_GPH0(6), 0);
102 mdelay(10);
103 gpio_direction_output(S5PC100_GPH0(6), 1);
104 mdelay(10);
105 }
106}
107
108static struct plat_lcd_data smdkc100_lcd_power_data = {
109 .set_power = smdkc100_lcd_power_set,
110};
111
112static struct platform_device smdkc100_lcd_powerdev = {
113 .name = "platform-lcd",
114 .dev.parent = &s3c_device_fb.dev,
115 .dev.platform_data = &smdkc100_lcd_power_data,
116};
117
118/* Frame Buffer */
119static struct s3c_fb_pd_win smdkc100_fb_win0 = {
120 /* this is to ensure we use win0 */
121 .win_mode = {
122 .refresh = 70,
123 .pixclock = (8+13+3+800)*(7+5+1+480),
124 .left_margin = 8,
125 .right_margin = 13,
126 .upper_margin = 7,
127 .lower_margin = 5,
128 .hsync_len = 3,
129 .vsync_len = 1,
130 .xres = 800,
131 .yres = 480,
132 },
133 .max_bpp = 32,
134 .default_bpp = 16,
135};
136
137static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
138 .win[0] = &smdkc100_fb_win0,
139 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
140 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
141 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
142};
143
76static struct map_desc smdkc100_iodesc[] = {}; 144static struct map_desc smdkc100_iodesc[] = {};
77 145
78static struct platform_device *smdkc100_devices[] __initdata = { 146static struct platform_device *smdkc100_devices[] __initdata = {
147 &s3c_device_i2c0,
148 &s3c_device_i2c1,
149 &s3c_device_fb,
150 &s3c_device_hsmmc0,
151 &s3c_device_hsmmc1,
152 &s3c_device_hsmmc2,
153 &smdkc100_lcd_powerdev,
79}; 154};
80 155
81static void __init smdkc100_map_io(void) 156static void __init smdkc100_map_io(void)
@@ -87,12 +162,24 @@ static void __init smdkc100_map_io(void)
87 162
88static void __init smdkc100_machine_init(void) 163static void __init smdkc100_machine_init(void)
89{ 164{
165 /* I2C */
166 s3c_i2c0_set_platdata(NULL);
167 s3c_i2c1_set_platdata(NULL);
168 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
169 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
170
171 s3c_fb_set_platdata(&smdkc100_lcd_pdata);
172
173 /* LCD init */
174 gpio_request(S5PC100_GPD(0), "GPD");
175 gpio_request(S5PC100_GPH0(6), "GPH0");
176 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
90 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); 177 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
91} 178}
92 179
93MACHINE_START(SMDKC100, "SMDKC100") 180MACHINE_START(SMDKC100, "SMDKC100")
94 /* Maintainer: Byungho Min <bhmin@samsung.com> */ 181 /* Maintainer: Byungho Min <bhmin@samsung.com> */
95 .phys_io = S5PC1XX_PA_UART & 0xfff00000, 182 .phys_io = S5PC100_PA_UART & 0xfff00000,
96 .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, 183 .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
97 .boot_params = S5PC100_PA_SDRAM + 0x100, 184 .boot_params = S5PC100_PA_SDRAM + 0x100,
98 185
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
new file mode 100644
index 000000000000..4385986a3da0
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
2 *
3 * Copyright 2008 Samsung Electronics
4 *
5 * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
6 *
7 * Based on mach-s3c6410/setup-sdhci.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19
20#include <linux/mmc/card.h>
21#include <linux/mmc/host.h>
22
23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h>
25
26/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
27
28char *s5pc100_hsmmc_clksrcs[4] = {
29 [0] = "hsmmc",
30 [1] = "hsmmc",
31 /* [2] = "mmc_bus", not yet succesfuuly used yet */
32 /* [3] = "48m", - note not succesfully used yet */
33};
34
35
36void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 /* don't need to alter anything acording to card-type */
44
45 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
46
47 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
48 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
49 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
50 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
51 S3C_SDHCI_CTRL2_ENFBCLKRX |
52 S3C_SDHCI_CTRL2_DFCNT_NONE |
53 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
54
55 if (ios->clock < 25 * 1000000)
56 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
57 S3C_SDHCI_CTRL3_FCSEL2 |
58 S3C_SDHCI_CTRL3_FCSEL1 |
59 S3C_SDHCI_CTRL3_FCSEL0);
60 else
61 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
62
63 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
64 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
65}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 00:48:38 -0500