27 files changed, 3478 insertions, 203 deletions

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 27ec167d2808..b2a11dfa3399 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,18 +5,36 @@
 
 # Configuration options for the S5PC100 CPU
 
+if ARCH_S5PC100
+
 config CPU_S5PC100
         bool
-        select CPU_S5PC100_INIT
-        select CPU_S5PC100_CLOCK
+        select PLAT_S5P
+        select S5P_EXT_INT
+        select S3C_PL330_DMA
         help
           Enable S5PC100 CPU support
 
+config S5PC100_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5PC1XX with an 24bpp RGB display helper.
+
+config S5PC100_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
 config S5PC100_SETUP_SDHCI
-        bool
-        select S5PC1XX_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S5PC100 based SDHCI systems
+        bool
+        select S5PC100_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC100 based SDHCI systems
+
+config S5PC100_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
 
 config MACH_SMDKC100
         bool "SMDKC100"
@@ -26,9 +44,10 @@ config MACH_SMDKC100
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
-        select S5PC1XX_SETUP_I2C0
-        select S5PC1XX_SETUP_I2C1
-        select S5PC1XX_SETUP_FB_24BPP
+        select S5PC100_SETUP_FB_24BPP
+        select S5PC100_SETUP_I2C1
         select S5PC100_SETUP_SDHCI
         help
           Machine support for the Samsung SMDKC100
+
+endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 809ff10f768f..543f3de5131e 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,11 +11,24 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)       += cpu.o
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o gpiolib.o irq-gpio.o
+obj-$(CONFIG_CPU_S5PC100)       += setup-i2c0.o
+obj-$(CONFIG_CPU_S5PC100)       += dma.o
 
 # Helper and device support
 
-obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+
+# device support
+obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 # machine support
+
 obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
+
+# device support
+obj-y                           += dev-audio.o
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
new file mode 100644
index 000000000000..e3fed4cfe7ad
--- /dev/null
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -0,0 +1,1358 @@
+/* linux/arch/arm/mach-s5pc100/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PC100 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+#include <mach/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5pc100.h>
+
+static struct clk s5p_clk_otgphy = {
+        .name           = "otg_phy",
+        .id             = -1,
+};
+
+static struct clk *clk_src_mout_href_list[] = {
+        [0] = &s5p_clk_27m,
+        [1] = &clk_fin_hpll,
+};
+
+static struct clksrc_sources clk_src_mout_href = {
+        .sources        = clk_src_mout_href_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mout_href_list),
+};
+
+static struct clksrc_clk clk_mout_href = {
+        .clk = {
+                .name           = "mout_href",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mout_href,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
+};
+
+static struct clk *clk_src_mout_48m_list[] = {
+        [0] = &clk_xusbxti,
+        [1] = &s5p_clk_otgphy,
+};
+
+static struct clksrc_sources clk_src_mout_48m = {
+        .sources        = clk_src_mout_48m_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mout_48m_list),
+};
+
+static struct clksrc_clk clk_mout_48m = {
+        .clk = {
+                .name           = "mout_48m",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mout_48m,
+        .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+        .clk = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mpll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
+};
+
+
+static struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_apll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_epll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
+};
+
+static struct clk *clk_src_mout_hpll_list[] = {
+        [0] = &s5p_clk_27m,
+};
+
+static struct clksrc_sources clk_src_mout_hpll = {
+        .sources        = clk_src_mout_hpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mout_hpll_list),
+};
+
+static struct clksrc_clk clk_mout_hpll = {
+        .clk    = {
+                .name           = "mout_hpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mout_hpll,
+        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_apll = {
+        .clk    = {
+                .name   = "div_apll",
+                .id     = -1,
+                .parent = &clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_arm = {
+        .clk    = {
+                .name   = "div_arm",
+                .id     = -1,
+                .parent = &clk_div_apll.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_d0_bus = {
+        .clk    = {
+                .name   = "div_d0_bus",
+                .id     = -1,
+                .parent = &clk_div_arm.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_pclkd0 = {
+        .clk    = {
+                .name   = "div_pclkd0",
+                .id     = -1,
+                .parent = &clk_div_d0_bus.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_secss = {
+        .clk    = {
+                .name   = "div_secss",
+                .id     = -1,
+                .parent = &clk_div_d0_bus.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_apll2 = {
+        .clk    = {
+                .name   = "div_apll2",
+                .id     = -1,
+                .parent = &clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
+};
+
+static struct clk *clk_src_mout_am_list[] = {
+        [0] = &clk_mout_mpll.clk,
+        [1] = &clk_div_apll2.clk,
+};
+
+struct clksrc_sources clk_src_mout_am = {
+        .sources        = clk_src_mout_am_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
+};
+
+static struct clksrc_clk clk_mout_am = {
+        .clk    = {
+                .name   = "mout_am",
+                .id     = -1,
+        },
+        .sources = &clk_src_mout_am,
+        .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_d1_bus = {
+        .clk    = {
+                .name   = "div_d1_bus",
+                .id     = -1,
+                .parent = &clk_mout_am.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_mpll2 = {
+        .clk    = {
+                .name   = "div_mpll2",
+                .id     = -1,
+                .parent = &clk_mout_am.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_mpll = {
+        .clk    = {
+                .name   = "div_mpll",
+                .id     = -1,
+                .parent = &clk_mout_am.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
+};
+
+static struct clk *clk_src_mout_onenand_list[] = {
+        [0] = &clk_div_d0_bus.clk,
+        [1] = &clk_div_d1_bus.clk,
+};
+
+struct clksrc_sources clk_src_mout_onenand = {
+        .sources        = clk_src_mout_onenand_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
+};
+
+static struct clksrc_clk clk_mout_onenand = {
+        .clk    = {
+                .name   = "mout_onenand",
+                .id     = -1,
+        },
+        .sources = &clk_src_mout_onenand,
+        .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk clk_div_onenand = {
+        .clk    = {
+                .name   = "div_onenand",
+                .id     = -1,
+                .parent = &clk_mout_onenand.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
+};
+
+static struct clksrc_clk clk_div_pclkd1 = {
+        .clk    = {
+                .name   = "div_pclkd1",
+                .id     = -1,
+                .parent = &clk_div_d1_bus.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_div_cam = {
+        .clk    = {
+                .name   = "div_cam",
+                .id     = -1,
+                .parent = &clk_div_mpll2.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
+};
+
+static struct clksrc_clk clk_div_hdmi = {
+        .clk    = {
+                .name   = "div_hdmi",
+                .id     = -1,
+                .parent = &clk_mout_hpll.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
+};
+
+static int s5pc100_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P_EPLL_CON);
+
+        return 0;
+}
+
+static unsigned long s5pc100_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static u32 epll_div[][4] = {
+        { 32750000,     131, 3, 4 },
+        { 32768000,     131, 3, 4 },
+        { 36000000,     72,  3, 3 },
+        { 45000000,     90,  3, 3 },
+        { 45158000,     90,  3, 3 },
+        { 45158400,     90,  3, 3 },
+        { 48000000,     96,  3, 3 },
+        { 49125000,     131, 4, 3 },
+        { 49152000,     131, 4, 3 },
+        { 60000000,     120, 3, 3 },
+        { 67737600,     226, 5, 3 },
+        { 67738000,     226, 5, 3 },
+        { 73800000,     246, 5, 3 },
+        { 73728000,     246, 5, 3 },
+        { 72000000,     144, 3, 3 },
+        { 84000000,     168, 3, 3 },
+        { 96000000,     96,  3, 2 },
+        { 144000000,    144, 3, 2 },
+        { 192000000,    96,  3, 1 }
+};
+
+static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P_EPLL_CON);
+
+        epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                if (epll_div[i][0] == rate) {
+                        epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
+                                    (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P_EPLL_CON);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5pc100_epll_ops = {
+        .get_rate = s5pc100_epll_get_rate,
+        .set_rate = s5pc100_epll_set_rate,
+};
+
+static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
+}
+
+static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
+}
+
+static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
+}
+
+static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
+}
+
+static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
+}
+
+static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
+}
+
+static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
+}
+
+static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
+}
+
+static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
+}
+
+static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
+}
+
+static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
+}
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "cssys",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "secss",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "g2d",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "mdma",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "cfcon",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "nfcon",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "onenandc",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "sdm",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_2_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "seckey",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_2_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "modemif",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "usbhost",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "pdma",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "pdma",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "rotator",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "fimc",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "fimc",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "fimc",
+                .id             = 2,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "jpeg",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "mipi-dsim",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "mipi-csis",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_1_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "g3d",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_0_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "tv",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_2_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "vp",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_2_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mixer",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_2_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "hdmi",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_2_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "mfc",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_2_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "apc",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "iec",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "systimer",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "irda",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "ccan",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "ccan",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "hsitx",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "hsirx",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "iis",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "pcm",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "pcm",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "keyif",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_5_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "spi_48m",
+                .id             = 0,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "spi_48m",
+                .id             = 1,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "spi_48m",
+                .id             = 2,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 0,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 1,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 2,
+                .parent         = &clk_mout_48m.clk,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        },
+};
+
+static struct clk clk_vclk54m = {
+        .name           = "vclk_54m",
+        .id             = -1,
+        .rate           = 54000000,
+};
+
+static struct clk clk_i2scdclk0 = {
+        .name           = "i2s_cdclk0",
+        .id             = -1,
+};
+
+static struct clk clk_i2scdclk1 = {
+        .name           = "i2s_cdclk1",
+        .id             = -1,
+};
+
+static struct clk clk_i2scdclk2 = {
+        .name           = "i2s_cdclk2",
+        .id             = -1,
+};
+
+static struct clk clk_pcmcdclk0 = {
+        .name           = "pcm_cdclk0",
+        .id             = -1,
+};
+
+static struct clk clk_pcmcdclk1 = {
+        .name           = "pcm_cdclk1",
+        .id             = -1,
+};
+
+static struct clk *clk_src_group1_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll2.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group1 = {
+        .sources        = clk_src_group1_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
+};
+
+static struct clk *clk_src_group2_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+};
+
+struct clksrc_sources clk_src_group2 = {
+        .sources        = clk_src_group2_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
+};
+
+static struct clk *clk_src_group3_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_i2scdclk0,
+        [4] = &clk_pcmcdclk0,
+        [5] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group3 = {
+        .sources        = clk_src_group3_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
+};
+
+static struct clk *clk_src_group4_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_i2scdclk1,
+        [4] = &clk_pcmcdclk1,
+        [5] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group4 = {
+        .sources        = clk_src_group4_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
+};
+
+static struct clk *clk_src_group5_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_i2scdclk2,
+        [4] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_group5 = {
+        .sources        = clk_src_group5_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
+};
+
+static struct clk *clk_src_group6_list[] = {
+        [0] = &s5p_clk_27m,
+        [1] = &clk_vclk54m,
+        [2] = &clk_div_hdmi.clk,
+};
+
+struct clksrc_sources clk_src_group6 = {
+        .sources        = clk_src_group6_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
+};
+
+static struct clk *clk_src_group7_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_mout_hpll.clk,
+        [3] = &clk_vclk54m,
+};
+
+struct clksrc_sources clk_src_group7 = {
+        .sources        = clk_src_group7_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
+};
+
+static struct clk *clk_src_mmc0_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+};
+
+struct clksrc_sources clk_src_mmc0 = {
+        .sources        = clk_src_mmc0_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
+};
+
+static struct clk *clk_src_mmc12_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_mmc12 = {
+        .sources        = clk_src_mmc12_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
+};
+
+static struct clk *clk_src_irda_usb_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_div_mpll.clk,
+        [2] = &clk_fin_epll,
+        [3] = &clk_mout_hpll.clk,
+};
+
+struct clksrc_sources clk_src_irda_usb = {
+        .sources        = clk_src_irda_usb_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
+};
+
+static struct clk *clk_src_pwi_list[] = {
+        [0] = &clk_fin_epll,
+        [1] = &clk_mout_epll.clk,
+        [2] = &clk_div_mpll.clk,
+};
+
+struct clksrc_sources clk_src_pwi = {
+        .sources        = clk_src_pwi_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 4),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 6),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 3),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_group2,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mixer",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 6),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_group6,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 8),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group3,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 9),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group4,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group5,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_lcd",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 0),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group7,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group7,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group7,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 3),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_group7,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 12),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_mmc0,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 13),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_mmc12,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 14),
+                        .enable         = s5pc100_sclk1_ctrl,
+
+                },
+                .sources = &clk_src_mmc12,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_irda",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_irda_usb,
+                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_irda",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_mmc12,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_pwi",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_pwi,
+                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_uhost",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5pc100_sclk0_ctrl,
+
+                },
+                .sources = &clk_src_irda_usb,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
+        },
+};
+
+/* Clock initialisation code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_mout_hpll,
+        &clk_mout_href,
+        &clk_mout_48m,
+        &clk_div_apll,
+        &clk_div_arm,
+        &clk_div_d0_bus,
+        &clk_div_pclkd0,
+        &clk_div_secss,
+        &clk_div_apll2,
+        &clk_mout_am,
+        &clk_div_d1_bus,
+        &clk_div_mpll2,
+        &clk_div_mpll,
+        &clk_mout_onenand,
+        &clk_div_onenand,
+        &clk_div_pclkd1,
+        &clk_div_cam,
+        &clk_div_hdmi,
+};
+
+void __init_or_cpufreq s5pc100_setup_clocks(void)
+{
+        unsigned long xtal;
+        unsigned long arm;
+        unsigned long hclkd0;
+        unsigned long hclkd1;
+        unsigned long pclkd0;
+        unsigned long pclkd1;
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned long hpll;
+        unsigned int ptr;
+
+        /* Set S5PC100 functions for clk_fout_epll */
+        clk_fout_epll.enable = s5pc100_epll_enable;
+        clk_fout_epll.ops = &s5pc100_epll_ops;
+
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+        xtal = clk_get_rate(&clk_xtal);
+
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+        apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
+        mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
+        epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
+        hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
+
+        printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_mout_hpll.clk.rate = hpll;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+
+        arm = clk_get_rate(&clk_div_arm.clk);
+        hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
+        pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
+        hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
+        pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
+
+        printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
+                        print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
+
+        clk_f.rate = arm;
+        clk_h.rate = hclkd1;
+        clk_p.rate = pclkd1;
+}
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "tzic",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_0_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "ebi",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "intmem",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "dmc",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "chipid",
+                .id             = -1,
+                .parent         = &clk_div_d0_bus.clk,
+                .enable         = s5pc100_d0_1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_4_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_div_d1_bus.clk,
+                .enable         = s5pc100_d1_3_ctrl,
+                .ctrlbit        = (1 << 6),
+        },
+};
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_i2scdclk0,
+        &clk_i2scdclk1,
+        &clk_i2scdclk2,
+        &clk_pcmcdclk0,
+        &clk_pcmcdclk1,
+};
+
+void __init s5pc100_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e7574a852..7b5bdbc9a5df 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,47 +22,55 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 
-#include <asm/proc-fns.h>
-
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <asm/proc-fns.h>
+
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <asm/irq.h>
 
-#include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
-#include <plat/regs-power.h>
+#include <mach/regs-clock.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/sdhci.h>
 #include <plat/iic-core.h>
+#include <plat/sdhci.h>
+#include <plat/onenand-core.h>
+
 #include <plat/s5pc100.h>
 
 /* Initial IO mappings */
 
 static struct map_desc s5pc100_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC2,
+                .pfn            = __phys_to_pfn(S5P_PA_VIC2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC100_VA_OTHERS,
+                .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }
 };
 
 static void s5pc100_idle(void)
 {
-        unsigned long tmp;
-
-        tmp = __raw_readl(S5PC100_PWR_CFG);
-        tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
-        tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
-        tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
-        __raw_writel(tmp, S5PC100_PWR_CFG);
-
-        tmp = __raw_readl(S5PC100_OTHERS);
-        tmp |= S5PC100_PMU_INT_DISABLE;
-        __raw_writel(tmp, S5PC100_OTHERS);
+        if (!need_resched())
+                cpu_do_idle();
 
-        cpu_do_idle();
+        local_irq_enable();
 }
 
 /* s5pc100_map_io
@@ -82,26 +90,29 @@ void __init s5pc100_map_io(void)
         /* the i2c devices are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
+
+        s3c_onenand_setname("s5pc100-onenand");
 }
 
 void __init s5pc100_init_clocks(int xtal)
 {
-        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
         s3c24xx_register_baseclocks(xtal);
-        s5pc1xx_register_clocks();
+        s5p_register_clocks(xtal);
         s5pc100_register_clocks();
         s5pc100_setup_clocks();
 }
 
 void __init s5pc100_init_irq(void)
 {
-        u32 vic_valid[] = {~0, ~0, ~0};
+        u32 vic[] = {~0, ~0, ~0};
 
         /* VIC0, VIC1, and VIC2 are fully populated. */
-        s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-struct sysdev_class s5pc100_sysclass = {
+static struct sysdev_class s5pc100_sysclass = {
         .name   = "s5pc100-core",
 };
 
@@ -118,9 +129,10 @@ core_initcall(s5pc100_core_init);
 
 int __init s5pc100_init(void)
 {
-        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+        printk(KERN_INFO "S5PC100: Initializing architecture\n");
 
-        s5pc1xx_idle = s5pc100_idle;
+        /* set idle function */
+        pm_idle = s5pc100_idle;
 
         return sysdev_register(&s5pc100_sysdev);
 }
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
new file mode 100644
index 000000000000..18cfe9ae1936
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -0,0 +1,287 @@
+/* linux/arch/arm/mach-s5pc100/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5pc100_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
+                break;
+
+        case 2:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
+                break;
+
+        case -1: /* Dedicated pins */
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_i2s_pdata = {
+        .cfg_gpio = s5pc100_cfg_i2s,
+};
+
+static struct resource s5pc100_iis0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S0,
+                .end   = S5PC100_PA_I2S0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S0_TX,
+                .end   = DMACH_I2S0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S0_RX,
+                .end   = DMACH_I2S0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis0 = {
+        .name             = "s3c64xx-iis-v4",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis0_resource),
+        .resource         = s5pc100_iis0_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+static struct resource s5pc100_iis1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S1,
+                .end   = S5PC100_PA_I2S1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S1_TX,
+                .end   = DMACH_I2S1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S1_RX,
+                .end   = DMACH_I2S1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis1 = {
+        .name             = "s3c64xx-iis",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis1_resource),
+        .resource         = s5pc100_iis1_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+static struct resource s5pc100_iis2_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_I2S2,
+                .end   = S5PC100_PA_I2S2 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S2_TX,
+                .end   = DMACH_I2S2_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S2_RX,
+                .end   = DMACH_I2S2_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_iis2 = {
+        .name             = "s3c64xx-iis",
+        .id               = 2,
+        .num_resources    = ARRAY_SIZE(s5pc100_iis2_resource),
+        .resource         = s5pc100_iis2_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+        .cfg_gpio = s5pc100_pcm_cfg_gpio,
+};
+
+static struct resource s5pc100_pcm0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_PCM0,
+                .end   = S5PC100_PA_PCM0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_PCM0_TX,
+                .end   = DMACH_PCM0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_PCM0_RX,
+                .end   = DMACH_PCM0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_pcm0 = {
+        .name             = "samsung-pcm",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5pc100_pcm0_resource),
+        .resource         = s5pc100_pcm0_resource,
+        .dev = {
+                .platform_data = &s3c_pcm_pdata,
+        },
+};
+
+static struct resource s5pc100_pcm1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_PCM1,
+                .end   = S5PC100_PA_PCM1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_PCM1_TX,
+                .end   = DMACH_PCM1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_PCM1_RX,
+                .end   = DMACH_PCM1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5pc100_device_pcm1 = {
+        .name             = "samsung-pcm",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_pcm1_resource),
+        .resource         = s5pc100_pcm1_resource,
+        .dev = {
+                .platform_data = &s3c_pcm_pdata,
+        },
+};
+
+/* AC97 Controller platform devices */
+
+static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
+        s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
+
+        return 0;
+}
+
+static struct resource s5pc100_ac97_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_AC97,
+                .end   = S5PC100_PA_AC97 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_AC97_PCMOUT,
+                .end   = DMACH_AC97_PCMOUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_AC97_PCMIN,
+                .end   = DMACH_AC97_PCMIN,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = DMACH_AC97_MICIN,
+                .end   = DMACH_AC97_MICIN,
+                .flags = IORESOURCE_DMA,
+        },
+        [4] = {
+                .start = IRQ_AC97,
+                .end   = IRQ_AC97,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_audio_pdata s3c_ac97_pdata = {
+        .cfg_gpio = s5pc100_ac97_cfg_gpio,
+};
+
+static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_ac97 = {
+        .name             = "s3c-ac97",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5pc100_ac97_resource),
+        .resource         = s5pc100_ac97_resource,
+        .dev = {
+                .platform_data = &s3c_ac97_pdata,
+                .dma_mask = &s5pc100_ac97_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
new file mode 100644
index 000000000000..14618c346057
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -0,0 +1,233 @@
+/* linux/arch/arm/mach-s5pc100/dev-spi.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+#include <plat/irqs.h>
+
+static char *spi_src_clks[] = {
+        [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
+        [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
+        [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
+                break;
+
+        case 2:
+                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5pc100_spi0_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI0,
+                .end   = S5PC100_PA_SPI0 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI0_TX,
+                .end   = DMACH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI0_RX,
+                .end   = DMACH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_spi0 = {
+        .name             = "s3c64xx-spi",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
+        .resource         = s5pc100_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi0_pdata,
+        },
+};
+
+static struct resource s5pc100_spi1_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI1,
+                .end   = S5PC100_PA_SPI1 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI1_TX,
+                .end   = DMACH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI1_RX,
+                .end   = DMACH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+struct platform_device s5pc100_device_spi1 = {
+        .name             = "s3c64xx-spi",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
+        .resource         = s5pc100_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi1_pdata,
+        },
+};
+
+static struct resource s5pc100_spi2_resource[] = {
+        [0] = {
+                .start = S5PC100_PA_SPI2,
+                .end   = S5PC100_PA_SPI2 + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_SPI2_TX,
+                .end   = DMACH_SPI2_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_SPI2_RX,
+                .end   = DMACH_SPI2_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start = IRQ_SPI2,
+                .end   = IRQ_SPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
+        .cfg_gpio = s5pc100_spi_cfg_gpio,
+        .fifo_lvl_mask = 0x7f,
+        .rx_lvl_offset = 13,
+        .high_speed = 1,
+};
+
+struct platform_device s5pc100_device_spi2 = {
+        .name             = "s3c64xx-spi",
+        .id               = 2,
+        .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
+        .resource         = s5pc100_spi2_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_spi2_pdata,
+        },
+};
+
+void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        struct s3c64xx_spi_info *pd;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                pd = &s5pc100_spi0_pdata;
+                break;
+        case 1:
+                pd = &s5pc100_spi1_pdata;
+                break;
+        case 2:
+                pd = &s5pc100_spi2_pdata;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
new file mode 100644
index 000000000000..0f5517571e2c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5pc100_pdma0_resource[] = {
+        [0] = {
+                .start  = S5PC100_PA_PDMA0,
+                .end    = S5PC100_PA_PDMA0 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA0,
+                .end    = IRQ_PDMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_IRDA,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_I2S2_RX,
+                [15] = DMACH_I2S2_TX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_SPI2_RX,
+                [21] = DMACH_SPI2_TX,
+                [22] = DMACH_AC97_MICIN,
+                [23] = DMACH_AC97_PCMIN,
+                [24] = DMACH_AC97_PCMOUT,
+                [25] = DMACH_EXTERNAL,
+                [26] = DMACH_PWM,
+                [27] = DMACH_SPDIF,
+                [28] = DMACH_HSI_RX,
+                [29] = DMACH_HSI_TX,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5pc100_device_pdma0 = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5pc100_pdma0_resource),
+        .resource       = s5pc100_pdma0_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_pdma0_pdata,
+        },
+};
+
+static struct resource s5pc100_pdma1_resource[] = {
+        [0] = {
+                .start  = S5PC100_PA_PDMA1,
+                .end    = S5PC100_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PDMA1,
+                .end    = IRQ_PDMA1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_IRDA,
+                [9] = DMACH_I2S0_RX,
+                [10] = DMACH_I2S0_TX,
+                [11] = DMACH_I2S0S_TX,
+                [12] = DMACH_I2S1_RX,
+                [13] = DMACH_I2S1_TX,
+                [14] = DMACH_I2S2_RX,
+                [15] = DMACH_I2S2_TX,
+                [16] = DMACH_SPI0_RX,
+                [17] = DMACH_SPI0_TX,
+                [18] = DMACH_SPI1_RX,
+                [19] = DMACH_SPI1_TX,
+                [20] = DMACH_SPI2_RX,
+                [21] = DMACH_SPI2_TX,
+                [22] = DMACH_PCM0_RX,
+                [23] = DMACH_PCM0_TX,
+                [24] = DMACH_PCM1_RX,
+                [25] = DMACH_PCM1_TX,
+                [26] = DMACH_MSM_REQ0,
+                [27] = DMACH_MSM_REQ1,
+                [28] = DMACH_MSM_REQ2,
+                [29] = DMACH_MSM_REQ3,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5pc100_device_pdma1 = {
+        .name           = "s3c-pl330",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s5pc100_pdma1_resource),
+        .resource       = s5pc100_pdma1_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5pc100_pdma1_pdata,
+        },
+};
+
+static struct platform_device *s5pc100_dmacs[] __initdata = {
+        &s5pc100_device_pdma0,
+        &s5pc100_device_pdma1,
+};
+
+static int __init s5pc100_dma_init(void)
+{
+        platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs));
+
+        return 0;
+}
+arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
new file mode 100644
index 000000000000..0fab7f2cd8bf
--- /dev/null
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -0,0 +1,426 @@
+/*
+ * arch/arm/plat-s5pc100/gpiolib.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC100 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   INT Type
+ * A0   8       4Bit    GPIO_INT0
+ * A1   5       4Bit    GPIO_INT1
+ * B    8       4Bit    GPIO_INT2
+ * C    5       4Bit    GPIO_INT3
+ * D    7       4Bit    GPIO_INT4
+ * E0   8       4Bit    GPIO_INT5
+ * E1   6       4Bit    GPIO_INT6
+ * F0   8       4Bit    GPIO_INT7
+ * F1   8       4Bit    GPIO_INT8
+ * F2   8       4Bit    GPIO_INT9
+ * F3   4       4Bit    GPIO_INT10
+ * G0   8       4Bit    GPIO_INT11
+ * G1   3       4Bit    GPIO_INT12
+ * G2   7       4Bit    GPIO_INT13
+ * G3   7       4Bit    GPIO_INT14
+ * H0   8       4Bit    WKUP_INT
+ * H1   8       4Bit    WKUP_INT
+ * H2   8       4Bit    WKUP_INT
+ * H3   8       4Bit    WKUP_INT
+ * I    8       4Bit    GPIO_INT15
+ * J0   8       4Bit    GPIO_INT16
+ * J1   5       4Bit    GPIO_INT17
+ * J2   8       4Bit    GPIO_INT18
+ * J3   8       4Bit    GPIO_INT19
+ * J4   4       4Bit    GPIO_INT20
+ * K0   8       4Bit    None
+ * K1   6       4Bit    None
+ * K2   8       4Bit    None
+ * K3   8       4Bit    None
+ * L0   8       4Bit    None
+ * L1   8       4Bit    None
+ * L2   8       4Bit    None
+ * L3   8       4Bit    None
+ */
+
+static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+        return S3C_IRQ_GPIO(chip->base + offset);
+}
+
+static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+        int base;
+
+        base = chip->base - S5PC100_GPH0(0);
+        if (base == 0)
+                return IRQ_EINT(offset);
+        base = chip->base - S5PC100_GPH1(0);
+        if (base == 0)
+                return IRQ_EINT(8 + offset);
+        base = chip->base - S5PC100_GPH2(0);
+        if (base == 0)
+                return IRQ_EINT(16 + offset);
+        base = chip->base - S5PC100_GPH3(0);
+        if (base == 0)
+                return IRQ_EINT(24 + offset);
+        return -EINVAL;
+}
+
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_eint = {
+        .cfg_eint       = 0xf,
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
+        {
+                .base   = S5PC100_GPA0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA0(0),
+                        .ngpio  = S5PC100_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .base   = S5PC100_GPA1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA1(0),
+                        .ngpio  = S5PC100_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .base   = S5PC100_GPB_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPB(0),
+                        .ngpio  = S5PC100_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .base   = S5PC100_GPC_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPC(0),
+                        .ngpio  = S5PC100_GPIO_C_NR,
+                        .label  = "GPC",
+                },
+        }, {
+                .base   = S5PC100_GPD_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPD(0),
+                        .ngpio  = S5PC100_GPIO_D_NR,
+                        .label  = "GPD",
+                },
+        }, {
+                .base   = S5PC100_GPE0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE0(0),
+                        .ngpio  = S5PC100_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .base   = S5PC100_GPE1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE1(0),
+                        .ngpio  = S5PC100_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .base   = S5PC100_GPF0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF0(0),
+                        .ngpio  = S5PC100_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .base   = S5PC100_GPF1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF1(0),
+                        .ngpio  = S5PC100_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .base   = S5PC100_GPF2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF2(0),
+                        .ngpio  = S5PC100_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .base   = S5PC100_GPF3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF3(0),
+                        .ngpio  = S5PC100_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        }, {
+                .base   = S5PC100_GPG0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG0(0),
+                        .ngpio  = S5PC100_GPIO_G0_NR,
+                        .label  = "GPG0",
+                },
+        }, {
+                .base   = S5PC100_GPG1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG1(0),
+                        .ngpio  = S5PC100_GPIO_G1_NR,
+                        .label  = "GPG1",
+                },
+        }, {
+                .base   = S5PC100_GPG2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG2(0),
+                        .ngpio  = S5PC100_GPIO_G2_NR,
+                        .label  = "GPG2",
+                },
+        }, {
+                .base   = S5PC100_GPG3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG3(0),
+                        .ngpio  = S5PC100_GPIO_G3_NR,
+                        .label  = "GPG3",
+                },
+        }, {
+                .base   = S5PC100_GPH0_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH0(0),
+                        .ngpio  = S5PC100_GPIO_H0_NR,
+                        .label  = "GPH0",
+                },
+        }, {
+                .base   = S5PC100_GPH1_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH1(0),
+                        .ngpio  = S5PC100_GPIO_H1_NR,
+                        .label  = "GPH1",
+                },
+        }, {
+                .base   = S5PC100_GPH2_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH2(0),
+                        .ngpio  = S5PC100_GPIO_H2_NR,
+                        .label  = "GPH2",
+                },
+        }, {
+                .base   = S5PC100_GPH3_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH3(0),
+                        .ngpio  = S5PC100_GPIO_H3_NR,
+                        .label  = "GPH3",
+                },
+        }, {
+                .base   = S5PC100_GPI_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPI(0),
+                        .ngpio  = S5PC100_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .base   = S5PC100_GPJ0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ0(0),
+                        .ngpio  = S5PC100_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .base   = S5PC100_GPJ1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ1(0),
+                        .ngpio  = S5PC100_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .base   = S5PC100_GPJ2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ2(0),
+                        .ngpio  = S5PC100_GPIO_J2_NR,
+                        .label  = "GPJ2",
+                },
+        }, {
+                .base   = S5PC100_GPJ3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ3(0),
+                        .ngpio  = S5PC100_GPIO_J3_NR,
+                        .label  = "GPJ3",
+                },
+        }, {
+                .base   = S5PC100_GPJ4_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ4(0),
+                        .ngpio  = S5PC100_GPIO_J4_NR,
+                        .label  = "GPJ4",
+                },
+        }, {
+                .base   = S5PC100_GPK0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK0(0),
+                        .ngpio  = S5PC100_GPIO_K0_NR,
+                        .label  = "GPK0",
+                },
+        }, {
+                .base   = S5PC100_GPK1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK1(0),
+                        .ngpio  = S5PC100_GPIO_K1_NR,
+                        .label  = "GPK1",
+                },
+        }, {
+                .base   = S5PC100_GPK2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK2(0),
+                        .ngpio  = S5PC100_GPIO_K2_NR,
+                        .label  = "GPK2",
+                },
+        }, {
+                .base   = S5PC100_GPK3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK3(0),
+                        .ngpio  = S5PC100_GPIO_K3_NR,
+                        .label  = "GPK3",
+                },
+        }, {
+                .base   = S5PC100_GPL0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL0(0),
+                        .ngpio  = S5PC100_GPIO_L0_NR,
+                        .label  = "GPL0",
+                },
+        }, {
+                .base   = S5PC100_GPL1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL1(0),
+                        .ngpio  = S5PC100_GPIO_L1_NR,
+                        .label  = "GPL1",
+                },
+        }, {
+                .base   = S5PC100_GPL2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL2(0),
+                        .ngpio  = S5PC100_GPIO_L2_NR,
+                        .label  = "GPL2",
+                },
+        }, {
+                .base   = S5PC100_GPL3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL3(0),
+                        .ngpio  = S5PC100_GPIO_L3_NR,
+                        .label  = "GPL3",
+                },
+        }, {
+                .base   = S5PC100_GPL4_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL4(0),
+                        .ngpio  = S5PC100_GPIO_L4_NR,
+                        .label  = "GPL4",
+                },
+        },
+};
+
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc100_gpioint;
+extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+
+static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+        /* Interrupt */
+        if (chip->config == &gpio_cfg) {
+                int i, irq;
+
+                chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+
+                for (i = 0;  i < chip->chip.ngpio; i++) {
+                        irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+                        set_irq_chip(irq, &s5pc100_gpioint);
+                        set_irq_data(irq, &chip->chip);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID);
+                }
+        } else if (chip->config == &gpio_cfg_eint) {
+                chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+        }
+}
+
+static __init int s5pc100_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chip;
+        int nr_chips;
+
+        chip = s5pc100_gpio_chips;
+        nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+
+        for (; nr_chips > 0; nr_chips--, chip++)
+                s5pc100_gpiolib_link(chip);
+
+        samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
+                                       ARRAY_SIZE(s5pc100_gpio_chips));
+
+        /* Interrupt */
+        set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
+
+        return 0;
+}
+core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index e181f5789482..70e02e91ee3c 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,12 +22,14 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx, tmp
+        .macro addruart, rx, rtmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C_PA_UART
-                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+                ldrne   \rx, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
                 add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
         .endm
 
 /* include the reset of the code which will do the work, we're only
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index 67131939e626..ba76af052c81 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -20,7 +20,7 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =S3C_VA_VIC0
+        ldr     \base, =VA_VIC0
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
@@ -29,18 +29,18 @@
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
         @ check the vic0
-        mov     \irqnr, # S3C_IRQ_OFFSET + 31
+        mov     \irqnr, # S5P_IRQ_OFFSET + 31
         ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
         teq     \irqstat, #0
 
         @ otherwise try vic1
-        addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
         addeq   \irqnr, \irqnr, #32
         ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
         teqeq   \irqstat, #0
 
         @ otherwise try vic2
-        addeq   \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
         addeq   \irqnr, \irqnr, #32
         ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
         teqeq   \irqstat, #0
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 2c4cbe8ee6b7..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -12,6 +12,9 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
@@ -52,11 +55,6 @@
 #define S5PC100_GPIO_L2_NR      (8)
 #define S5PC100_GPIO_L3_NR      (8)
 #define S5PC100_GPIO_L4_NR      (8)
-#define S5PC100_GPIO_MP00_NR    (8)
-#define S5PC100_GPIO_MP01_NR    (8)
-#define S5PC100_GPIO_MP02_NR    (8)
-#define S5PC100_GPIO_MP03_NR    (8)
-#define S5PC100_GPIO_MP04_NR    (5)
 
 /* GPIO bank numbes */
 
@@ -65,50 +63,45 @@
  * change from one gpio bank to another can be caught.
 */
 
-#define S5PC1XX_GPIO_NEXT(__gpio) \
+#define S5PC100_GPIO_NEXT(__gpio) \
         ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
 
-enum s3c_gpio_number {
+enum s5p_gpio_number {
         S5PC100_GPIO_A0_START   = 0,
-        S5PC100_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
-        S5PC100_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
-        S5PC100_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
-        S5PC100_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
-        S5PC100_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
-        S5PC100_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
-        S5PC100_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
-        S5PC100_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
-        S5PC100_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
-        S5PC100_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
-        S5PC100_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
-        S5PC100_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
-        S5PC100_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
-        S5PC100_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
-        S5PC100_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
-        S5PC100_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
-        S5PC100_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
-        S5PC100_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
-        S5PC100_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
-        S5PC100_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
-        S5PC100_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
-        S5PC100_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
-        S5PC100_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
-        S5PC100_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
-        S5PC100_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
-        S5PC100_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
-        S5PC100_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
-        S5PC100_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
-        S5PC100_GPIO_L0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
-        S5PC100_GPIO_L1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
-        S5PC100_GPIO_L2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
-        S5PC100_GPIO_L3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
-        S5PC100_GPIO_L4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
-        S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
-        S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
-        S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
-        S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
-        S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
-        S5PC100_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
+        S5PC100_GPIO_A1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
+        S5PC100_GPIO_B_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
+        S5PC100_GPIO_C_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
+        S5PC100_GPIO_D_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
+        S5PC100_GPIO_E0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
+        S5PC100_GPIO_E1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
+        S5PC100_GPIO_F0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
+        S5PC100_GPIO_F1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
+        S5PC100_GPIO_F2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
+        S5PC100_GPIO_F3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
+        S5PC100_GPIO_G0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
+        S5PC100_GPIO_G1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
+        S5PC100_GPIO_G2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
+        S5PC100_GPIO_G3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
+        S5PC100_GPIO_H0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
+        S5PC100_GPIO_H1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
+        S5PC100_GPIO_H2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
+        S5PC100_GPIO_H3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
+        S5PC100_GPIO_I_START    = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
+        S5PC100_GPIO_J0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
+        S5PC100_GPIO_J1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
+        S5PC100_GPIO_J2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
+        S5PC100_GPIO_J3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
+        S5PC100_GPIO_J4_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
+        S5PC100_GPIO_K0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
+        S5PC100_GPIO_K1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
+        S5PC100_GPIO_K2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
+        S5PC100_GPIO_K3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
+        S5PC100_GPIO_L0_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
+        S5PC100_GPIO_L1_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
+        S5PC100_GPIO_L2_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
+        S5PC100_GPIO_L3_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
+        S5PC100_GPIO_L4_START   = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
+        S5PC100_GPIO_END        = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
 };
 
 /* S5PC100 GPIO number definitions. */
@@ -146,17 +139,20 @@ enum s3c_gpio_number {
 #define S5PC100_GPL2(_nr)       (S5PC100_GPIO_L2_START + (_nr))
 #define S5PC100_GPL3(_nr)       (S5PC100_GPIO_L3_START + (_nr))
 #define S5PC100_GPL4(_nr)       (S5PC100_GPIO_L4_START + (_nr))
-#define S5PC100_MP00(_nr)       (S5PC100_GPIO_MP00_START + (_nr))
-#define S5PC100_MP01(_nr)       (S5PC100_GPIO_MP01_START + (_nr))
-#define S5PC100_MP02(_nr)       (S5PC100_GPIO_MP02_START + (_nr))
-#define S5PC100_MP03(_nr)       (S5PC100_GPIO_MP03_START + (_nr))
-#define S5PC100_MP04(_nr)       (S5PC100_GPIO_MP04_START + (_nr))
-#define S5PC100_MP05(_nr)       (S5PC100_GPIO_MP05_START + (_nr))
 
-/* It used the end of the S5PC1XX gpios */
+/* It used the end of the S5PC100 gpios */
 #define S3C_GPIO_END            S5PC100_GPIO_END
 
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 
+#define EINT_MODE               S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)          S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)          S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)          S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)          S5PC100_GPH3(x)
+
 #include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index b53fa48a52c6..28aa551dc3a8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,9 +11,104 @@
 
 #include <plat/irqs.h>
 
-/* LCD */
+/* VIC0: system, DMA, timer */
+#define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
+#define IRQ_BATF                S5P_IRQ_VIC0(17)
+#define IRQ_MDMA                S5P_IRQ_VIC0(18)
+#define IRQ_PDMA0               S5P_IRQ_VIC0(19)
+#define IRQ_PDMA1               S5P_IRQ_VIC0(20)
+#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
+#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
+#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
+#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
+#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
+#define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
+#define IRQ_WDT                 S5P_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
+#define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
+#define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
+
+/* VIC1: ARM, power, memory, connectivity */
+#define IRQ_CORTEX0             S5P_IRQ_VIC1(0)
+#define IRQ_CORTEX1             S5P_IRQ_VIC1(1)
+#define IRQ_CORTEX2             S5P_IRQ_VIC1(2)
+#define IRQ_CORTEX3             S5P_IRQ_VIC1(3)
+#define IRQ_CORTEX4             S5P_IRQ_VIC1(4)
+#define IRQ_IEMAPC              S5P_IRQ_VIC1(5)
+#define IRQ_IEMIEC              S5P_IRQ_VIC1(6)
+#define IRQ_ONENAND             S5P_IRQ_VIC1(7)
+#define IRQ_NFC                 S5P_IRQ_VIC1(8)
+#define IRQ_CFC                 S5P_IRQ_VIC1(9)
+#define IRQ_UART0               S5P_IRQ_VIC1(10)
+#define IRQ_UART1               S5P_IRQ_VIC1(11)
+#define IRQ_UART2               S5P_IRQ_VIC1(12)
+#define IRQ_UART3               S5P_IRQ_VIC1(13)
+#define IRQ_IIC                 S5P_IRQ_VIC1(14)
+#define IRQ_SPI0                S5P_IRQ_VIC1(15)
+#define IRQ_SPI1                S5P_IRQ_VIC1(16)
+#define IRQ_SPI2                S5P_IRQ_VIC1(17)
+#define IRQ_IRDA                S5P_IRQ_VIC1(18)
+#define IRQ_CAN0                S5P_IRQ_VIC1(19)
+#define IRQ_CAN1                S5P_IRQ_VIC1(20)
+#define IRQ_HSIRX               S5P_IRQ_VIC1(21)
+#define IRQ_HSITX               S5P_IRQ_VIC1(22)
+#define IRQ_UHOST               S5P_IRQ_VIC1(23)
+#define IRQ_OTG                 S5P_IRQ_VIC1(24)
+#define IRQ_MSM                 S5P_IRQ_VIC1(25)
+#define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
+#define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
+#define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
+#define IRQ_MIPICSI             S5P_IRQ_VIC1(29)
+#define IRQ_MIPIDSI             S5P_IRQ_VIC1(30)
+
+/* VIC2: multimedia, audio, security */
+#define IRQ_LCD0                S5P_IRQ_VIC2(0)
+#define IRQ_LCD1                S5P_IRQ_VIC2(1)
+#define IRQ_LCD2                S5P_IRQ_VIC2(2)
+#define IRQ_LCD3                S5P_IRQ_VIC2(3)
+#define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
+#define IRQ_FIMC0               S5P_IRQ_VIC2(5)
+#define IRQ_FIMC1               S5P_IRQ_VIC2(6)
+#define IRQ_FIMC2               S5P_IRQ_VIC2(7)
+#define IRQ_JPEG                S5P_IRQ_VIC2(8)
+#define IRQ_2D                  S5P_IRQ_VIC2(9)
+#define IRQ_3D                  S5P_IRQ_VIC2(10)
+#define IRQ_MIXER               S5P_IRQ_VIC2(11)
+#define IRQ_HDMI                S5P_IRQ_VIC2(12)
+#define IRQ_IIC1                S5P_IRQ_VIC2(13)
+#define IRQ_MFC                 S5P_IRQ_VIC2(14)
+#define IRQ_TVENC               S5P_IRQ_VIC2(15)
+#define IRQ_I2S0                S5P_IRQ_VIC2(16)
+#define IRQ_I2S1                S5P_IRQ_VIC2(17)
+#define IRQ_I2S2                S5P_IRQ_VIC2(18)
+#define IRQ_AC97                S5P_IRQ_VIC2(19)
+#define IRQ_PCM0                S5P_IRQ_VIC2(20)
+#define IRQ_PCM1                S5P_IRQ_VIC2(21)
+#define IRQ_SPDIF               S5P_IRQ_VIC2(22)
+#define IRQ_ADC                 S5P_IRQ_VIC2(23)
+#define IRQ_PENDN               S5P_IRQ_VIC2(24)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
+#define IRQ_CG                  S5P_IRQ_VIC2(26)
+#define IRQ_SEC                 S5P_IRQ_VIC2(27)
+#define IRQ_SECRX               S5P_IRQ_VIC2(28)
+#define IRQ_SECTX               S5P_IRQ_VIC2(29)
+#define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
+#define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
+#define IRQ_VIC_END             S5P_IRQ_VIC2(31)
+
+#define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
+#define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
+
+#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
+
+/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
+#define NR_IRQS         (S3C_IRQ_GPIO(320) + 1)
+
+/* Compatibility */
 #define IRQ_LCD_FIFO            IRQ_LCD0
 #define IRQ_LCD_VSYNC           IRQ_LCD1
 #define IRQ_LCD_SYSTEM          IRQ_LCD2
 
-#endif /* __ASM_ARCH_IRQ_H */
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe8bef6..cadae4305688 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -3,9 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * Based on mach-s3c6400/include/mach/map.h
- *
- * S5PC1XX - Memory map definitions
+ * S5PC100 - Memory map definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,6 +14,7 @@
 #define __ASM_ARCH_MAP_H __FILE__
 
 #include <plat/map-base.h>
+#include <plat/map-s5p.h>
 
 /*
  * map-base.h has already defined virtual memory address
@@ -31,25 +30,21 @@
  *
  */
 
+#define S5PC100_PA_ONENAND_BUF  (0xB0000000)
+#define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
+
 /* Chip ID */
+
 #define S5PC100_PA_CHIPID       (0xE0000000)
-#define S5PC1XX_PA_CHIPID       S5PC100_PA_CHIPID
-#define S5PC1XX_VA_CHIPID       S3C_VA_SYS
-
-/* System */
-#define S5PC100_PA_CLK          (0xE0100000)
-#define S5PC100_PA_CLK_OTHER    (0xE0200000)
-#define S5PC100_PA_PWR          (0xE0108000)
-#define S5PC1XX_PA_CLK          S5PC100_PA_CLK
-#define S5PC1XX_PA_PWR          S5PC100_PA_PWR
-#define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
-#define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
-#define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
-#define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
-
-/* GPIO */
-#define S5PC100_PA_GPIO         (0xE0300000)
-#define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
+#define S5P_PA_CHIPID           S5PC100_PA_CHIPID
+
+#define S5PC100_PA_SYSCON       (0xE0100000)
+#define S5P_PA_SYSCON           S5PC100_PA_SYSCON
+
+#define S5PC100_PA_OTHERS       (0xE0200000)
+#define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
+
+#define S5P_PA_GPIO             (0xE0300000)
 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 
 /* Interrupt */
@@ -59,6 +54,12 @@
 #define S5PC100_VA_VIC_OFFSET   0x10000
 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+#define S5P_PA_VIC0             S5PC1XX_PA_VIC(0)
+#define S5P_PA_VIC1             S5PC1XX_PA_VIC(1)
+#define S5P_PA_VIC2             S5PC1XX_PA_VIC(2)
+
+
+#define S5PC100_PA_ONENAND      (0xE7100000)
 
 /* DMA */
 #define S5PC100_PA_MDMA         (0xE8100000)
@@ -67,84 +68,71 @@
 
 /* Timer */
 #define S5PC100_PA_TIMER        (0xEA000000)
-#define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
-#define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+#define S5P_PA_TIMER            S5PC100_PA_TIMER
 
-/* RTC */
-#define S5PC100_PA_RTC          (0xEA300000)
+#define S5PC100_PA_SYSTIMER     (0xEA100000)
 
-/* UART */
 #define S5PC100_PA_UART         (0xEC000000)
-#define S5PC1XX_PA_UART         S5PC100_PA_UART
-#define S5PC1XX_VA_UART         S3C_VA_UART
 
-/* I2C */
-#define S5PC100_PA_I2C          (0xEC100000)
-#define S5PC100_PA_I2C1         (0xEC200000)
+#define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
+#define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
+#define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
+#define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
+#define S5P_SZ_UART             SZ_256
+
+#define S5PC100_PA_IIC0         (0xEC100000)
+#define S5PC100_PA_IIC1         (0xEC200000)
+
+/* SPI */
+#define S5PC100_PA_SPI0         0xEC300000
+#define S5PC100_PA_SPI1         0xEC400000
+#define S5PC100_PA_SPI2         0xEC500000
 
 /* USB HS OTG */
 #define S5PC100_PA_USB_HSOTG    (0xED200000)
 #define S5PC100_PA_USB_HSPHY    (0xED300000)
 
-/* SD/MMC */
-#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
-#define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
-#define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
-#define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
-
-/* LCD */
 #define S5PC100_PA_FB           (0xEE000000)
 
-/* Multimedia */
-#define S5PC100_PA_G2D          (0xEE800000)
-#define S5PC100_PA_JPEG         (0xEE500000)
-#define S5PC100_PA_ROTATOR      (0xEE100000)
-#define S5PC100_PA_G3D          (0xEF000000)
-
-/* I2S */
 #define S5PC100_PA_I2S0         (0xF2000000)
 #define S5PC100_PA_I2S1         (0xF2100000)
 #define S5PC100_PA_I2S2         (0xF2200000)
 
+#define S5PC100_PA_AC97         0xF2300000
+
+/* PCM */
+#define S5PC100_PA_PCM0         0xF2400000
+#define S5PC100_PA_PCM1         0xF2500000
+
 /* KEYPAD */
 #define S5PC100_PA_KEYPAD       (0xF3100000)
 
-/* ADC & TouchScreen */
-#define S5PC100_PA_TSADC        (0xF3000000)
+#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
-/* ETC */
 #define S5PC100_PA_SDRAM        (0x20000000)
-#define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
+#define S5P_PA_SDRAM            S5PC100_PA_SDRAM
 
-/* compatibility defines. */
-#define S3C_PA_RTC              S5PC100_PA_RTC
+/* compatibiltiy defines. */
 #define S3C_PA_UART             S5PC100_PA_UART
-#define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
-#define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
-#define S3C_PA_UART2            (S5PC100_PA_UART + 0x800)
-#define S3C_PA_UART3            (S5PC100_PA_UART + 0xC00)
-#define S3C_VA_UART0            (S3C_VA_UART + 0x0)
-#define S3C_VA_UART1            (S3C_VA_UART + 0x400)
-#define S3C_VA_UART2            (S3C_VA_UART + 0x800)
-#define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
-#define S3C_UART_OFFSET         0x400
-#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S3C_PA_IIC              S5PC100_PA_IIC0
+#define S3C_PA_IIC1             S5PC100_PA_IIC1
 #define S3C_PA_FB               S5PC100_PA_FB
 #define S3C_PA_G2D              S5PC100_PA_G2D
 #define S3C_PA_G3D              S5PC100_PA_G3D
 #define S3C_PA_JPEG             S5PC100_PA_JPEG
 #define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
-#define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
-#define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
-#define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
-#define S3C_PA_IIC              S5PC100_PA_I2C
-#define S3C_PA_IIC1             S5PC100_PA_I2C1
+#define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
+#define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
+#define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
 #define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
-#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
-#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
-#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
+#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
 #define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
 #define S3C_PA_TSADC            S5PC100_PA_TSADC
+#define S3C_PA_ONENAND          S5PC100_PA_ONENAND
+#define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
+#define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
 
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
new file mode 100644
index 000000000000..5d27d286d504
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -0,0 +1,77 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PC100 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
+
+#define S5PC100_REG_OTHERS(x)   (S5PC100_VA_OTHERS + (x))
+
+#define S5P_APLL_LOCK           S5P_CLKREG(0x00)
+#define S5P_MPLL_LOCK           S5P_CLKREG(0x04)
+#define S5P_EPLL_LOCK           S5P_CLKREG(0x08)
+#define S5P_HPLL_LOCK           S5P_CLKREG(0x0C)
+
+#define S5P_APLL_CON            S5P_CLKREG(0x100)
+#define S5P_MPLL_CON            S5P_CLKREG(0x104)
+#define S5P_EPLL_CON            S5P_CLKREG(0x108)
+#define S5P_HPLL_CON            S5P_CLKREG(0x10C)
+
+#define S5P_CLK_SRC0            S5P_CLKREG(0x200)
+#define S5P_CLK_SRC1            S5P_CLKREG(0x204)
+#define S5P_CLK_SRC2            S5P_CLKREG(0x208)
+#define S5P_CLK_SRC3            S5P_CLKREG(0x20C)
+
+#define S5P_CLK_DIV0            S5P_CLKREG(0x300)
+#define S5P_CLK_DIV1            S5P_CLKREG(0x304)
+#define S5P_CLK_DIV2            S5P_CLKREG(0x308)
+#define S5P_CLK_DIV3            S5P_CLKREG(0x30C)
+#define S5P_CLK_DIV4            S5P_CLKREG(0x310)
+
+#define S5P_CLK_OUT             S5P_CLKREG(0x400)
+
+#define S5P_CLKGATE_D00         S5P_CLKREG(0x500)
+#define S5P_CLKGATE_D01         S5P_CLKREG(0x504)
+#define S5P_CLKGATE_D02         S5P_CLKREG(0x508)
+
+#define S5P_CLKGATE_D10         S5P_CLKREG(0x520)
+#define S5P_CLKGATE_D11         S5P_CLKREG(0x524)
+#define S5P_CLKGATE_D12         S5P_CLKREG(0x528)
+#define S5P_CLKGATE_D13         S5P_CLKREG(0x52C)
+#define S5P_CLKGATE_D14         S5P_CLKREG(0x530)
+#define S5P_CLKGATE_D15         S5P_CLKREG(0x534)
+
+#define S5P_CLKGATE_D20         S5P_CLKREG(0x540)
+
+#define S5P_CLKGATE_SCLK0       S5P_CLKREG(0x560)
+#define S5P_CLKGATE_SCLK1       S5P_CLKREG(0x564)
+
+/* CLKDIV0 */
+#define S5P_CLKDIV0_D0_MASK             (0x7<<8)
+#define S5P_CLKDIV0_D0_SHIFT            (8)
+#define S5P_CLKDIV0_PCLKD0_MASK         (0x7<<12)
+#define S5P_CLKDIV0_PCLKD0_SHIFT        (12)
+
+/* CLKDIV1 */
+#define S5P_CLKDIV1_D1_MASK             (0x7<<12)
+#define S5P_CLKDIV1_D1_SHIFT            (12)
+#define S5P_CLKDIV1_PCLKD1_MASK         (0x7<<16)
+#define S5P_CLKDIV1_PCLKD1_SHIFT        (16)
+
+#define S5PC100_SWRESET         S5PC100_REG_OTHERS(0x000)
+
+#define S5PC100_SWRESET_RESETVAL        0xc100
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..dd6295e1251d
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -0,0 +1,75 @@
+/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO register definitions
+ */
+
+#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
+#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* S5PC100 */
+#define S5PC100_GPIO_BASE       S5P_VA_GPIO
+#define S5PC100_GPA0_BASE       (S5PC100_GPIO_BASE + 0x0000)
+#define S5PC100_GPA1_BASE       (S5PC100_GPIO_BASE + 0x0020)
+#define S5PC100_GPB_BASE        (S5PC100_GPIO_BASE + 0x0040)
+#define S5PC100_GPC_BASE        (S5PC100_GPIO_BASE + 0x0060)
+#define S5PC100_GPD_BASE        (S5PC100_GPIO_BASE + 0x0080)
+#define S5PC100_GPE0_BASE       (S5PC100_GPIO_BASE + 0x00A0)
+#define S5PC100_GPE1_BASE       (S5PC100_GPIO_BASE + 0x00C0)
+#define S5PC100_GPF0_BASE       (S5PC100_GPIO_BASE + 0x00E0)
+#define S5PC100_GPF1_BASE       (S5PC100_GPIO_BASE + 0x0100)
+#define S5PC100_GPF2_BASE       (S5PC100_GPIO_BASE + 0x0120)
+#define S5PC100_GPF3_BASE       (S5PC100_GPIO_BASE + 0x0140)
+#define S5PC100_GPG0_BASE       (S5PC100_GPIO_BASE + 0x0160)
+#define S5PC100_GPG1_BASE       (S5PC100_GPIO_BASE + 0x0180)
+#define S5PC100_GPG2_BASE       (S5PC100_GPIO_BASE + 0x01A0)
+#define S5PC100_GPG3_BASE       (S5PC100_GPIO_BASE + 0x01C0)
+#define S5PC100_GPH0_BASE       (S5PC100_GPIO_BASE + 0x0C00)
+#define S5PC100_GPH1_BASE       (S5PC100_GPIO_BASE + 0x0C20)
+#define S5PC100_GPH2_BASE       (S5PC100_GPIO_BASE + 0x0C40)
+#define S5PC100_GPH3_BASE       (S5PC100_GPIO_BASE + 0x0C60)
+#define S5PC100_GPI_BASE        (S5PC100_GPIO_BASE + 0x01E0)
+#define S5PC100_GPJ0_BASE       (S5PC100_GPIO_BASE + 0x0200)
+#define S5PC100_GPJ1_BASE       (S5PC100_GPIO_BASE + 0x0220)
+#define S5PC100_GPJ2_BASE       (S5PC100_GPIO_BASE + 0x0240)
+#define S5PC100_GPJ3_BASE       (S5PC100_GPIO_BASE + 0x0260)
+#define S5PC100_GPJ4_BASE       (S5PC100_GPIO_BASE + 0x0280)
+#define S5PC100_GPK0_BASE       (S5PC100_GPIO_BASE + 0x02A0)
+#define S5PC100_GPK1_BASE       (S5PC100_GPIO_BASE + 0x02C0)
+#define S5PC100_GPK2_BASE       (S5PC100_GPIO_BASE + 0x02E0)
+#define S5PC100_GPK3_BASE       (S5PC100_GPIO_BASE + 0x0300)
+#define S5PC100_GPL0_BASE       (S5PC100_GPIO_BASE + 0x0320)
+#define S5PC100_GPL1_BASE       (S5PC100_GPIO_BASE + 0x0340)
+#define S5PC100_GPL2_BASE       (S5PC100_GPIO_BASE + 0x0360)
+#define S5PC100_GPL3_BASE       (S5PC100_GPIO_BASE + 0x0380)
+#define S5PC100_GPL4_BASE       (S5PC100_GPIO_BASE + 0x03A0)
+
+#define S5PC100EINT30CON                (S5P_VA_GPIO + 0xE00)
+#define S5P_EINT_CON(x)                 (S5PC100EINT30CON + ((x) * 0x4))
+
+#define S5PC100EINT30FLTCON0            (S5P_VA_GPIO + 0xE80)
+#define S5P_EINT_FLTCON(x)              (S5PC100EINT30FLTCON0 + ((x) * 0x4))
+
+#define S5PC100EINT30MASK               (S5P_VA_GPIO + 0xF00)
+#define S5P_EINT_MASK(x)                (S5PC100EINT30MASK + ((x) * 0x4))
+
+#define S5PC100EINT30PEND               (S5P_VA_GPIO + 0xF40)
+#define S5P_EINT_PEND(x)                (S5PC100EINT30PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
+
+/* values for S5P_EXTINT0 */
+#define S5P_EXTINT_LOWLEV               (0x00)
+#define S5P_EXTINT_HILEV                (0x01)
+#define S5P_EXTINT_FALLEDGE             (0x02)
+#define S5P_EXTINT_RISEEDGE             (0x03)
+#define S5P_EXTINT_BOTHEDGE             (0x04)
+
+#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
+
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 751ac15438c8..4d9036d0f288 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - IRQ register definitions
+ * S5PC100 - IRQ register definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,9 +16,4 @@
 #include <mach/map.h>
 #include <asm/hardware/vic.h>
 
-/* interrupt controller */
-#define S5PC1XX_VIC0REG(x)                      ((x) + S5PC1XX_VA_VIC(0))
-#define S5PC1XX_VIC1REG(x)                      ((x) + S5PC1XX_VA_VIC(1))
-#define S5PC1XX_VIC2REG(x)                      ((x) + S5PC1XX_VA_VIC(2))
-
 #endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..65e426370bb2
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S5PC100_PLAT_SPI_CLKS_H
+#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
+
+#define S5PC100_SPI_SRCCLK_PCLK         0
+#define S5PC100_SPI_SRCCLK_48M          1
+#define S5PC100_SPI_SRCCLK_SPIBUS       2
+
+#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index f0d31a2a598c..681f626a9ae1 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -3,7 +3,7 @@
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
- * S5PC1XX - system implementation
+ * S5PC100 - system implementation
  *
  * Based on mach-s3c6400/include/mach/system.h
  */
@@ -13,14 +13,11 @@
 
 #include <linux/io.h>
 #include <mach/map.h>
-#include <plat/regs-clock.h>
-
-void (*s5pc1xx_idle)(void);
+#include <mach/regs-clock.h>
 
 static void arch_idle(void)
 {
-        if (s5pc1xx_idle)
-                s5pc1xx_idle();
+        /* nothing here yet */
 }
 
 static void arch_reset(char mode, const char *cmd)
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index f338c9eec717..20f68730ed18 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -20,8 +20,8 @@
  */
 static inline u32 s3c24xx_ostimer_pending(void)
 {
-        u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
-        return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0));
+        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
+        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
 }
 
 #define TICK_MAX        (0xffffffff)
diff --git a/arch/arm/mach-s5pc100/init.c b/arch/arm/mach-s5pc100/init.c
new file mode 100644
index 000000000000..19d7b523c137
--- /dev/null
+++ b/arch/arm/mach-s5pc100/init.c
@@ -0,0 +1,24 @@
+/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5pc100.h>
+
+/* uart registration process */
+void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
new file mode 100644
index 000000000000..2bf86c18bc73
--- /dev/null
+++ b/arch/arm/mach-s5pc100/irq-gpio.c
@@ -0,0 +1,266 @@
+/*
+ * arch/arm/mach-s5pc100/irq-gpio.c
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+
+#define S5P_GPIOREG(x)          (S5P_VA_GPIO + (x))
+
+#define CON_OFFSET                      0x700
+#define MASK_OFFSET                     0x900
+#define PEND_OFFSET                     0xA00
+#define CON_OFFSET_2                    0xE00
+#define MASK_OFFSET_2                   0xF00
+#define PEND_OFFSET_2                   0xF40
+
+#define GPIOINT_LEVEL_LOW               0x0
+#define GPIOINT_LEVEL_HIGH              0x1
+#define GPIOINT_EDGE_FALLING            0x2
+#define GPIOINT_EDGE_RISING             0x3
+#define GPIOINT_EDGE_BOTH               0x4
+
+static int group_to_con_offset(int group)
+{
+        return group << 2;
+}
+
+static int group_to_mask_offset(int group)
+{
+        return group << 2;
+}
+
+static int group_to_pend_offset(int group)
+{
+        return group << 2;
+}
+
+static int s5pc100_get_start(unsigned int group)
+{
+        switch (group) {
+        case 0: return S5PC100_GPIO_A0_START;
+        case 1: return S5PC100_GPIO_A1_START;
+        case 2: return S5PC100_GPIO_B_START;
+        case 3: return S5PC100_GPIO_C_START;
+        case 4: return S5PC100_GPIO_D_START;
+        case 5: return S5PC100_GPIO_E0_START;
+        case 6: return S5PC100_GPIO_E1_START;
+        case 7: return S5PC100_GPIO_F0_START;
+        case 8: return S5PC100_GPIO_F1_START;
+        case 9: return S5PC100_GPIO_F2_START;
+        case 10: return S5PC100_GPIO_F3_START;
+        case 11: return S5PC100_GPIO_G0_START;
+        case 12: return S5PC100_GPIO_G1_START;
+        case 13: return S5PC100_GPIO_G2_START;
+        case 14: return S5PC100_GPIO_G3_START;
+        case 15: return S5PC100_GPIO_I_START;
+        case 16: return S5PC100_GPIO_J0_START;
+        case 17: return S5PC100_GPIO_J1_START;
+        case 18: return S5PC100_GPIO_J2_START;
+        case 19: return S5PC100_GPIO_J3_START;
+        case 20: return S5PC100_GPIO_J4_START;
+        default:
+                BUG();
+        }
+
+        return -EINVAL;
+}
+
+static int s5pc100_get_group(unsigned int irq)
+{
+        irq -= S3C_IRQ_GPIO(0);
+
+        switch (irq) {
+        case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
+                return 0;
+        case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
+                return 1;
+        case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
+                return 2;
+        case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
+                return 3;
+        case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
+                return 4;
+        case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
+                return 5;
+        case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
+                return 6;
+        case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
+                return 7;
+        case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
+                return 8;
+        case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
+                return 9;
+        case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
+                return 10;
+        case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
+                return 11;
+        case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
+                return 12;
+        case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
+                return 13;
+        case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
+                return 14;
+        case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
+                return 15;
+        case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
+                return 16;
+        case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
+                return 17;
+        case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
+                return 18;
+        case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
+                return 19;
+        case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
+                return 20;
+        default:
+                BUG();
+        }
+
+        return -EINVAL;
+}
+
+static int s5pc100_get_offset(unsigned int irq)
+{
+        struct gpio_chip *chip = get_irq_data(irq);
+        return irq - S3C_IRQ_GPIO(chip->base);
+}
+
+static void s5pc100_gpioint_ack(unsigned int irq)
+{
+        int group, offset, pend_offset;
+        unsigned int value;
+
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
+        pend_offset = group_to_pend_offset(group);
+
+        value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
+}
+
+static void s5pc100_gpioint_mask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+
+        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+
+static void s5pc100_gpioint_unmask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+
+        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
+        value &= ~(1 << offset);
+        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+
+static void s5pc100_gpioint_mask_ack(unsigned int irq)
+{
+        s5pc100_gpioint_mask(irq);
+        s5pc100_gpioint_ack(irq);
+}
+
+static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+        int group, offset, con_offset;
+        unsigned int value;
+
+        group = s5pc100_get_group(irq);
+        offset = s5pc100_get_offset(irq);
+        con_offset = group_to_con_offset(group);
+
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No irq type\n");
+                return -EINVAL;
+        case IRQ_TYPE_EDGE_RISING:
+                type = GPIOINT_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type = GPIOINT_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                type = GPIOINT_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                type = GPIOINT_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                type = GPIOINT_LEVEL_LOW;
+                break;
+        default:
+                BUG();
+        }
+
+
+        value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
+        value &= ~(0xf << (offset * 0x4));
+        value |= (type << (offset * 0x4));
+        __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
+
+        return 0;
+}
+
+struct irq_chip s5pc100_gpioint = {
+        .name           = "GPIO",
+        .ack            = s5pc100_gpioint_ack,
+        .mask           = s5pc100_gpioint_mask,
+        .mask_ack       = s5pc100_gpioint_mask_ack,
+        .unmask         = s5pc100_gpioint_unmask,
+        .set_type       = s5pc100_gpioint_set_type,
+};
+
+void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int group, offset, pend_offset, mask_offset;
+        int real_irq, group_end;
+        unsigned int pend, mask;
+
+        group_end = 21;
+
+        for (group = 0; group < group_end; group++) {
+                pend_offset = group_to_pend_offset(group);
+                pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
+                if (!pend)
+                        continue;
+
+                mask_offset = group_to_mask_offset(group);
+                mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
+                pend &= ~mask;
+
+                for (offset = 0; offset < 8; offset++) {
+                        if (pend & (1 << offset)) {
+                                real_irq = s5pc100_get_start(group) + offset;
+                                generic_handle_irq(S3C_IRQ_GPIO(real_irq));
+                        }
+                }
+        }
+}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index ae3c52cd0ebb..af22f8202a07 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -35,7 +35,6 @@
 
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-gpio.h>
 
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -44,38 +43,48 @@
 #include <plat/fb.h>
 #include <plat/iic.h>
 
-#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
-#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
-#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define S5PC100_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define S5PC100_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define S5PC100_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                 S3C2440_UFCON_RXTRIG8 |        \
+                                 S3C2440_UFCON_TXTRIG16)
 
 static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
         [0] = {
                 .hwport      = 0,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [1] = {
                 .hwport      = 1,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [2] = {
                 .hwport      = 2,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
         [3] = {
                 .hwport      = 3,
                 .flags       = 0,
-                .ucon        = 0x3c5,
-                .ulcon       = 0x03,
-                .ufcon       = 0x51,
+                .ucon        = S5PC100_UCON_DEFAULT,
+                .ulcon       = S5PC100_ULCON_DEFAULT,
+                .ufcon       = S5PC100_UFCON_DEFAULT,
         },
 };
 
@@ -119,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = {
 static struct s3c_fb_pd_win smdkc100_fb_win0 = {
         /* this is to ensure we use win0 */
         .win_mode       = {
-                .refresh        = 70,
-                .pixclock       = (8+13+3+800)*(7+5+1+480),
+                .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80),
                 .left_margin    = 8,
                 .right_margin   = 13,
                 .upper_margin   = 7,
@@ -141,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
         .setup_gpio     = s5pc100_fb_gpio_setup_24bpp,
 };
 
-static struct map_desc smdkc100_iodesc[] = {};
-
 static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_i2c0,
         &s3c_device_i2c1,
@@ -151,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
         &smdkc100_lcd_powerdev,
+        &s5pc100_device_iis0,
+        &s5pc100_device_ac97,
 };
 
 static void __init smdkc100_map_io(void)
 {
-        s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
 }
@@ -179,10 +187,9 @@ static void __init smdkc100_machine_init(void)
 
 MACHINE_START(SMDKC100, "SMDKC100")
         /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .phys_io        = S5PC100_PA_UART & 0xfff00000,
-        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = S5PC100_PA_SDRAM + 0x100,
-
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P_PA_SDRAM + 0x100,
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
new file mode 100644
index 000000000000..6eba6cb8e2f4
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
@@ -0,0 +1,48 @@
+/*
+ * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC100 setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+#define DISR_OFFSET     0x7008
+
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+        unsigned int gpio = 0;
+
+        for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
new file mode 100644
index 000000000000..dd3174e6ecc5
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC100 I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
new file mode 100644
index 000000000000..d1fec26b69ee
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -0,0 +1,30 @@
+/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC100 I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..7769c760c9ef
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
+ *
+ * Copyright 2009 Samsung Eletronics
+ *
+ * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+
+void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        unsigned int num;
+
+        num = width;
+        /* In case of 8 width, we should decrease the 2 */
+        if (width == 8)
+                num = width - 2;
+
+        end = S5PC100_GPG0(2 + num);
+
+        /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
+        for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        if (width == 8) {
+                for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        }
+
+        s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+}
+
+void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+
+        end = S5PC100_GPG2(2 + width);
+
+        /* Set all the necessary GPG2 pins to special-function 2 */
+        for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+}
+
+void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+
+        end = S5PC100_GPG3(2 + width);
+
+        /* Set all the necessary GPG3 pins to special-function 2 */
+        for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+
+        s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+}