diff options
Diffstat (limited to 'arch/arm/mach-s5pc100/setup-ide.c')
-rw-r--r-- | arch/arm/mach-s5pc100/setup-ide.c | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c new file mode 100644 index 000000000000..83575671fb59 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-ide.c | |||
@@ -0,0 +1,70 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-ide.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5PC100 setup information for IDE | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/gpio.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #include <mach/regs-clock.h> | ||
18 | #include <plat/gpio-cfg.h> | ||
19 | |||
20 | void s5pc100_ide_setup_gpio(void) | ||
21 | { | ||
22 | u32 reg; | ||
23 | u32 gpio = 0; | ||
24 | |||
25 | /* Independent CF interface, CF chip select configuration */ | ||
26 | reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); | ||
27 | writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); | ||
28 | |||
29 | /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ | ||
30 | for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) { | ||
31 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); | ||
32 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
33 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
34 | } | ||
35 | |||
36 | /*CF_Data[0 - 7] */ | ||
37 | for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) { | ||
38 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); | ||
39 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
40 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
41 | } | ||
42 | |||
43 | /* CF_Data[8 - 15] */ | ||
44 | for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) { | ||
45 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); | ||
46 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
47 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
48 | } | ||
49 | |||
50 | /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ | ||
51 | for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) { | ||
52 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); | ||
53 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
54 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
55 | } | ||
56 | |||
57 | /* EBI_OE, EBI_WE */ | ||
58 | for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++) | ||
59 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); | ||
60 | |||
61 | /* CF_OE, CF_WE */ | ||
62 | for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) { | ||
63 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
64 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
65 | } | ||
66 | |||
67 | /* CF_CD */ | ||
68 | s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); | ||
69 | s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE); | ||
70 | } | ||