diff options
Diffstat (limited to 'arch/arm/mach-s5pc100/mach-smdkc100.c')
-rw-r--r-- | arch/arm/mach-s5pc100/mach-smdkc100.c | 56 |
1 files changed, 32 insertions, 24 deletions
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index bfe67db34f04..af22f8202a07 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
@@ -43,38 +43,48 @@ | |||
43 | #include <plat/fb.h> | 43 | #include <plat/fb.h> |
44 | #include <plat/iic.h> | 44 | #include <plat/iic.h> |
45 | 45 | ||
46 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) | 46 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | 47 | #define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
48 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | 48 | S3C2410_UCON_RXILEVEL | \ |
49 | S3C2410_UCON_TXIRQMODE | \ | ||
50 | S3C2410_UCON_RXIRQMODE | \ | ||
51 | S3C2410_UCON_RXFIFO_TOI | \ | ||
52 | S3C2443_UCON_RXERR_IRQEN) | ||
53 | |||
54 | #define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
55 | |||
56 | #define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
57 | S3C2440_UFCON_RXTRIG8 | \ | ||
58 | S3C2440_UFCON_TXTRIG16) | ||
49 | 59 | ||
50 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | 60 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { |
51 | [0] = { | 61 | [0] = { |
52 | .hwport = 0, | 62 | .hwport = 0, |
53 | .flags = 0, | 63 | .flags = 0, |
54 | .ucon = 0x3c5, | 64 | .ucon = S5PC100_UCON_DEFAULT, |
55 | .ulcon = 0x03, | 65 | .ulcon = S5PC100_ULCON_DEFAULT, |
56 | .ufcon = 0x51, | 66 | .ufcon = S5PC100_UFCON_DEFAULT, |
57 | }, | 67 | }, |
58 | [1] = { | 68 | [1] = { |
59 | .hwport = 1, | 69 | .hwport = 1, |
60 | .flags = 0, | 70 | .flags = 0, |
61 | .ucon = 0x3c5, | 71 | .ucon = S5PC100_UCON_DEFAULT, |
62 | .ulcon = 0x03, | 72 | .ulcon = S5PC100_ULCON_DEFAULT, |
63 | .ufcon = 0x51, | 73 | .ufcon = S5PC100_UFCON_DEFAULT, |
64 | }, | 74 | }, |
65 | [2] = { | 75 | [2] = { |
66 | .hwport = 2, | 76 | .hwport = 2, |
67 | .flags = 0, | 77 | .flags = 0, |
68 | .ucon = 0x3c5, | 78 | .ucon = S5PC100_UCON_DEFAULT, |
69 | .ulcon = 0x03, | 79 | .ulcon = S5PC100_ULCON_DEFAULT, |
70 | .ufcon = 0x51, | 80 | .ufcon = S5PC100_UFCON_DEFAULT, |
71 | }, | 81 | }, |
72 | [3] = { | 82 | [3] = { |
73 | .hwport = 3, | 83 | .hwport = 3, |
74 | .flags = 0, | 84 | .flags = 0, |
75 | .ucon = 0x3c5, | 85 | .ucon = S5PC100_UCON_DEFAULT, |
76 | .ulcon = 0x03, | 86 | .ulcon = S5PC100_ULCON_DEFAULT, |
77 | .ufcon = 0x51, | 87 | .ufcon = S5PC100_UFCON_DEFAULT, |
78 | }, | 88 | }, |
79 | }; | 89 | }; |
80 | 90 | ||
@@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = { | |||
118 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { | 128 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { |
119 | /* this is to ensure we use win0 */ | 129 | /* this is to ensure we use win0 */ |
120 | .win_mode = { | 130 | .win_mode = { |
121 | .refresh = 70, | 131 | .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80), |
122 | .pixclock = (8+13+3+800)*(7+5+1+480), | ||
123 | .left_margin = 8, | 132 | .left_margin = 8, |
124 | .right_margin = 13, | 133 | .right_margin = 13, |
125 | .upper_margin = 7, | 134 | .upper_margin = 7, |
@@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { | |||
140 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, | 149 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, |
141 | }; | 150 | }; |
142 | 151 | ||
143 | static struct map_desc smdkc100_iodesc[] = {}; | ||
144 | |||
145 | static struct platform_device *smdkc100_devices[] __initdata = { | 152 | static struct platform_device *smdkc100_devices[] __initdata = { |
146 | &s3c_device_i2c0, | 153 | &s3c_device_i2c0, |
147 | &s3c_device_i2c1, | 154 | &s3c_device_i2c1, |
@@ -150,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = { | |||
150 | &s3c_device_hsmmc1, | 157 | &s3c_device_hsmmc1, |
151 | &s3c_device_hsmmc2, | 158 | &s3c_device_hsmmc2, |
152 | &smdkc100_lcd_powerdev, | 159 | &smdkc100_lcd_powerdev, |
160 | &s5pc100_device_iis0, | ||
161 | &s5pc100_device_ac97, | ||
153 | }; | 162 | }; |
154 | 163 | ||
155 | static void __init smdkc100_map_io(void) | 164 | static void __init smdkc100_map_io(void) |
156 | { | 165 | { |
157 | s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); | 166 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
158 | s3c24xx_init_clocks(12000000); | 167 | s3c24xx_init_clocks(12000000); |
159 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); | 168 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); |
160 | } | 169 | } |
@@ -178,10 +187,9 @@ static void __init smdkc100_machine_init(void) | |||
178 | 187 | ||
179 | MACHINE_START(SMDKC100, "SMDKC100") | 188 | MACHINE_START(SMDKC100, "SMDKC100") |
180 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ | 189 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ |
181 | .phys_io = S5PC100_PA_UART & 0xfff00000, | 190 | .phys_io = S3C_PA_UART & 0xfff00000, |
182 | .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, | 191 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, |
183 | .boot_params = S5PC100_PA_SDRAM + 0x100, | 192 | .boot_params = S5P_PA_SDRAM + 0x100, |
184 | |||
185 | .init_irq = s5pc100_init_irq, | 193 | .init_irq = s5pc100_init_irq, |
186 | .map_io = smdkc100_map_io, | 194 | .map_io = smdkc100_map_io, |
187 | .init_machine = smdkc100_machine_init, | 195 | .init_machine = smdkc100_machine_init, |