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-rw-r--r--arch/arm/mach-s5pc100/clock.c163
1 files changed, 40 insertions, 123 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b8282d..cd248e681377 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -31,7 +31,6 @@
31 31
32static struct clk s5p_clk_otgphy = { 32static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy", 33 .name = "otg_phy",
34 .id = -1,
35}; 34};
36 35
37static struct clk *clk_src_mout_href_list[] = { 36static struct clk *clk_src_mout_href_list[] = {
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
47static struct clksrc_clk clk_mout_href = { 46static struct clksrc_clk clk_mout_href = {
48 .clk = { 47 .clk = {
49 .name = "mout_href", 48 .name = "mout_href",
50 .id = -1,
51 }, 49 },
52 .sources = &clk_src_mout_href, 50 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
66static struct clksrc_clk clk_mout_48m = { 64static struct clksrc_clk clk_mout_48m = {
67 .clk = { 65 .clk = {
68 .name = "mout_48m", 66 .name = "mout_48m",
69 .id = -1,
70 }, 67 },
71 .sources = &clk_src_mout_48m, 68 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, 69 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
75static struct clksrc_clk clk_mout_mpll = { 72static struct clksrc_clk clk_mout_mpll = {
76 .clk = { 73 .clk = {
77 .name = "mout_mpll", 74 .name = "mout_mpll",
78 .id = -1,
79 }, 75 },
80 .sources = &clk_src_mpll, 76 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
85static struct clksrc_clk clk_mout_apll = { 81static struct clksrc_clk clk_mout_apll = {
86 .clk = { 82 .clk = {
87 .name = "mout_apll", 83 .name = "mout_apll",
88 .id = -1,
89 }, 84 },
90 .sources = &clk_src_apll, 85 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 86 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
94static struct clksrc_clk clk_mout_epll = { 89static struct clksrc_clk clk_mout_epll = {
95 .clk = { 90 .clk = {
96 .name = "mout_epll", 91 .name = "mout_epll",
97 .id = -1,
98 }, 92 },
99 .sources = &clk_src_epll, 93 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 94 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
112static struct clksrc_clk clk_mout_hpll = { 106static struct clksrc_clk clk_mout_hpll = {
113 .clk = { 107 .clk = {
114 .name = "mout_hpll", 108 .name = "mout_hpll",
115 .id = -1,
116 }, 109 },
117 .sources = &clk_src_mout_hpll, 110 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 111 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
121static struct clksrc_clk clk_div_apll = { 114static struct clksrc_clk clk_div_apll = {
122 .clk = { 115 .clk = {
123 .name = "div_apll", 116 .name = "div_apll",
124 .id = -1,
125 .parent = &clk_mout_apll.clk, 117 .parent = &clk_mout_apll.clk,
126 }, 118 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, 119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
130static struct clksrc_clk clk_div_arm = { 122static struct clksrc_clk clk_div_arm = {
131 .clk = { 123 .clk = {
132 .name = "div_arm", 124 .name = "div_arm",
133 .id = -1,
134 .parent = &clk_div_apll.clk, 125 .parent = &clk_div_apll.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
139static struct clksrc_clk clk_div_d0_bus = { 130static struct clksrc_clk clk_div_d0_bus = {
140 .clk = { 131 .clk = {
141 .name = "div_d0_bus", 132 .name = "div_d0_bus",
142 .id = -1,
143 .parent = &clk_div_arm.clk, 133 .parent = &clk_div_arm.clk,
144 }, 134 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
148static struct clksrc_clk clk_div_pclkd0 = { 138static struct clksrc_clk clk_div_pclkd0 = {
149 .clk = { 139 .clk = {
150 .name = "div_pclkd0", 140 .name = "div_pclkd0",
151 .id = -1,
152 .parent = &clk_div_d0_bus.clk, 141 .parent = &clk_div_d0_bus.clk,
153 }, 142 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 143 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
157static struct clksrc_clk clk_div_secss = { 146static struct clksrc_clk clk_div_secss = {
158 .clk = { 147 .clk = {
159 .name = "div_secss", 148 .name = "div_secss",
160 .id = -1,
161 .parent = &clk_div_d0_bus.clk, 149 .parent = &clk_div_d0_bus.clk,
162 }, 150 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, 151 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
166static struct clksrc_clk clk_div_apll2 = { 154static struct clksrc_clk clk_div_apll2 = {
167 .clk = { 155 .clk = {
168 .name = "div_apll2", 156 .name = "div_apll2",
169 .id = -1,
170 .parent = &clk_mout_apll.clk, 157 .parent = &clk_mout_apll.clk,
171 }, 158 },
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, 159 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
185static struct clksrc_clk clk_mout_am = { 172static struct clksrc_clk clk_mout_am = {
186 .clk = { 173 .clk = {
187 .name = "mout_am", 174 .name = "mout_am",
188 .id = -1,
189 }, 175 },
190 .sources = &clk_src_mout_am, 176 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 177 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
194static struct clksrc_clk clk_div_d1_bus = { 180static struct clksrc_clk clk_div_d1_bus = {
195 .clk = { 181 .clk = {
196 .name = "div_d1_bus", 182 .name = "div_d1_bus",
197 .id = -1,
198 .parent = &clk_mout_am.clk, 183 .parent = &clk_mout_am.clk,
199 }, 184 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, 185 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
203static struct clksrc_clk clk_div_mpll2 = { 188static struct clksrc_clk clk_div_mpll2 = {
204 .clk = { 189 .clk = {
205 .name = "div_mpll2", 190 .name = "div_mpll2",
206 .id = -1,
207 .parent = &clk_mout_am.clk, 191 .parent = &clk_mout_am.clk,
208 }, 192 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, 193 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
212static struct clksrc_clk clk_div_mpll = { 196static struct clksrc_clk clk_div_mpll = {
213 .clk = { 197 .clk = {
214 .name = "div_mpll", 198 .name = "div_mpll",
215 .id = -1,
216 .parent = &clk_mout_am.clk, 199 .parent = &clk_mout_am.clk,
217 }, 200 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, 201 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
231static struct clksrc_clk clk_mout_onenand = { 214static struct clksrc_clk clk_mout_onenand = {
232 .clk = { 215 .clk = {
233 .name = "mout_onenand", 216 .name = "mout_onenand",
234 .id = -1,
235 }, 217 },
236 .sources = &clk_src_mout_onenand, 218 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 219 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
240static struct clksrc_clk clk_div_onenand = { 222static struct clksrc_clk clk_div_onenand = {
241 .clk = { 223 .clk = {
242 .name = "div_onenand", 224 .name = "div_onenand",
243 .id = -1,
244 .parent = &clk_mout_onenand.clk, 225 .parent = &clk_mout_onenand.clk,
245 }, 226 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, 227 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
249static struct clksrc_clk clk_div_pclkd1 = { 230static struct clksrc_clk clk_div_pclkd1 = {
250 .clk = { 231 .clk = {
251 .name = "div_pclkd1", 232 .name = "div_pclkd1",
252 .id = -1,
253 .parent = &clk_div_d1_bus.clk, 233 .parent = &clk_div_d1_bus.clk,
254 }, 234 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, 235 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
258static struct clksrc_clk clk_div_cam = { 238static struct clksrc_clk clk_div_cam = {
259 .clk = { 239 .clk = {
260 .name = "div_cam", 240 .name = "div_cam",
261 .id = -1,
262 .parent = &clk_div_mpll2.clk, 241 .parent = &clk_div_mpll2.clk,
263 }, 242 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, 243 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
267static struct clksrc_clk clk_div_hdmi = { 246static struct clksrc_clk clk_div_hdmi = {
268 .clk = { 247 .clk = {
269 .name = "div_hdmi", 248 .name = "div_hdmi",
270 .id = -1,
271 .parent = &clk_mout_hpll.clk, 249 .parent = &clk_mout_hpll.clk,
272 }, 250 },
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, 251 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
399static struct clk init_clocks_off[] = { 377static struct clk init_clocks_off[] = {
400 { 378 {
401 .name = "cssys", 379 .name = "cssys",
402 .id = -1,
403 .parent = &clk_div_d0_bus.clk, 380 .parent = &clk_div_d0_bus.clk,
404 .enable = s5pc100_d0_0_ctrl, 381 .enable = s5pc100_d0_0_ctrl,
405 .ctrlbit = (1 << 6), 382 .ctrlbit = (1 << 6),
406 }, { 383 }, {
407 .name = "secss", 384 .name = "secss",
408 .id = -1,
409 .parent = &clk_div_d0_bus.clk, 385 .parent = &clk_div_d0_bus.clk,
410 .enable = s5pc100_d0_0_ctrl, 386 .enable = s5pc100_d0_0_ctrl,
411 .ctrlbit = (1 << 5), 387 .ctrlbit = (1 << 5),
412 }, { 388 }, {
413 .name = "g2d", 389 .name = "g2d",
414 .id = -1,
415 .parent = &clk_div_d0_bus.clk, 390 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_0_ctrl, 391 .enable = s5pc100_d0_0_ctrl,
417 .ctrlbit = (1 << 4), 392 .ctrlbit = (1 << 4),
418 }, { 393 }, {
419 .name = "mdma", 394 .name = "mdma",
420 .id = -1,
421 .parent = &clk_div_d0_bus.clk, 395 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_0_ctrl, 396 .enable = s5pc100_d0_0_ctrl,
423 .ctrlbit = (1 << 3), 397 .ctrlbit = (1 << 3),
424 }, { 398 }, {
425 .name = "cfcon", 399 .name = "cfcon",
426 .id = -1,
427 .parent = &clk_div_d0_bus.clk, 400 .parent = &clk_div_d0_bus.clk,
428 .enable = s5pc100_d0_0_ctrl, 401 .enable = s5pc100_d0_0_ctrl,
429 .ctrlbit = (1 << 2), 402 .ctrlbit = (1 << 2),
430 }, { 403 }, {
431 .name = "nfcon", 404 .name = "nfcon",
432 .id = -1,
433 .parent = &clk_div_d0_bus.clk, 405 .parent = &clk_div_d0_bus.clk,
434 .enable = s5pc100_d0_1_ctrl, 406 .enable = s5pc100_d0_1_ctrl,
435 .ctrlbit = (1 << 3), 407 .ctrlbit = (1 << 3),
436 }, { 408 }, {
437 .name = "onenandc", 409 .name = "onenandc",
438 .id = -1,
439 .parent = &clk_div_d0_bus.clk, 410 .parent = &clk_div_d0_bus.clk,
440 .enable = s5pc100_d0_1_ctrl, 411 .enable = s5pc100_d0_1_ctrl,
441 .ctrlbit = (1 << 2), 412 .ctrlbit = (1 << 2),
442 }, { 413 }, {
443 .name = "sdm", 414 .name = "sdm",
444 .id = -1,
445 .parent = &clk_div_d0_bus.clk, 415 .parent = &clk_div_d0_bus.clk,
446 .enable = s5pc100_d0_2_ctrl, 416 .enable = s5pc100_d0_2_ctrl,
447 .ctrlbit = (1 << 2), 417 .ctrlbit = (1 << 2),
448 }, { 418 }, {
449 .name = "seckey", 419 .name = "seckey",
450 .id = -1,
451 .parent = &clk_div_d0_bus.clk, 420 .parent = &clk_div_d0_bus.clk,
452 .enable = s5pc100_d0_2_ctrl, 421 .enable = s5pc100_d0_2_ctrl,
453 .ctrlbit = (1 << 1), 422 .ctrlbit = (1 << 1),
454 }, { 423 }, {
455 .name = "hsmmc", 424 .name = "hsmmc",
456 .id = 2, 425 .devname = "s3c-sdhci.2",
457 .parent = &clk_div_d1_bus.clk, 426 .parent = &clk_div_d1_bus.clk,
458 .enable = s5pc100_d1_0_ctrl, 427 .enable = s5pc100_d1_0_ctrl,
459 .ctrlbit = (1 << 7), 428 .ctrlbit = (1 << 7),
460 }, { 429 }, {
461 .name = "hsmmc", 430 .name = "hsmmc",
462 .id = 1, 431 .devname = "s3c-sdhci.1",
463 .parent = &clk_div_d1_bus.clk, 432 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_0_ctrl, 433 .enable = s5pc100_d1_0_ctrl,
465 .ctrlbit = (1 << 6), 434 .ctrlbit = (1 << 6),
466 }, { 435 }, {
467 .name = "hsmmc", 436 .name = "hsmmc",
468 .id = 0, 437 .devname = "s3c-sdhci.0",
469 .parent = &clk_div_d1_bus.clk, 438 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_0_ctrl, 439 .enable = s5pc100_d1_0_ctrl,
471 .ctrlbit = (1 << 5), 440 .ctrlbit = (1 << 5),
472 }, { 441 }, {
473 .name = "modemif", 442 .name = "modemif",
474 .id = -1,
475 .parent = &clk_div_d1_bus.clk, 443 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_0_ctrl, 444 .enable = s5pc100_d1_0_ctrl,
477 .ctrlbit = (1 << 4), 445 .ctrlbit = (1 << 4),
478 }, { 446 }, {
479 .name = "otg", 447 .name = "otg",
480 .id = -1,
481 .parent = &clk_div_d1_bus.clk, 448 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_0_ctrl, 449 .enable = s5pc100_d1_0_ctrl,
483 .ctrlbit = (1 << 3), 450 .ctrlbit = (1 << 3),
484 }, { 451 }, {
485 .name = "usbhost", 452 .name = "usbhost",
486 .id = -1,
487 .parent = &clk_div_d1_bus.clk, 453 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_0_ctrl, 454 .enable = s5pc100_d1_0_ctrl,
489 .ctrlbit = (1 << 2), 455 .ctrlbit = (1 << 2),
490 }, { 456 }, {
491 .name = "pdma", 457 .name = "pdma",
492 .id = 1, 458 .devname = "s3c-pl330.1",
493 .parent = &clk_div_d1_bus.clk, 459 .parent = &clk_div_d1_bus.clk,
494 .enable = s5pc100_d1_0_ctrl, 460 .enable = s5pc100_d1_0_ctrl,
495 .ctrlbit = (1 << 1), 461 .ctrlbit = (1 << 1),
496 }, { 462 }, {
497 .name = "pdma", 463 .name = "pdma",
498 .id = 0, 464 .devname = "s3c-pl330.0",
499 .parent = &clk_div_d1_bus.clk, 465 .parent = &clk_div_d1_bus.clk,
500 .enable = s5pc100_d1_0_ctrl, 466 .enable = s5pc100_d1_0_ctrl,
501 .ctrlbit = (1 << 0), 467 .ctrlbit = (1 << 0),
502 }, { 468 }, {
503 .name = "lcd", 469 .name = "lcd",
504 .id = -1,
505 .parent = &clk_div_d1_bus.clk, 470 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_1_ctrl, 471 .enable = s5pc100_d1_1_ctrl,
507 .ctrlbit = (1 << 0), 472 .ctrlbit = (1 << 0),
508 }, { 473 }, {
509 .name = "rotator", 474 .name = "rotator",
510 .id = -1,
511 .parent = &clk_div_d1_bus.clk, 475 .parent = &clk_div_d1_bus.clk,
512 .enable = s5pc100_d1_1_ctrl, 476 .enable = s5pc100_d1_1_ctrl,
513 .ctrlbit = (1 << 1), 477 .ctrlbit = (1 << 1),
514 }, { 478 }, {
515 .name = "fimc", 479 .name = "fimc",
516 .id = 0, 480 .devname = "s5p-fimc.0",
517 .parent = &clk_div_d1_bus.clk, 481 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_1_ctrl, 482 .enable = s5pc100_d1_1_ctrl,
519 .ctrlbit = (1 << 2), 483 .ctrlbit = (1 << 2),
520 }, { 484 }, {
521 .name = "fimc", 485 .name = "fimc",
522 .id = 1, 486 .devname = "s5p-fimc.1",
523 .parent = &clk_div_d1_bus.clk, 487 .parent = &clk_div_d1_bus.clk,
524 .enable = s5pc100_d1_1_ctrl, 488 .enable = s5pc100_d1_1_ctrl,
525 .ctrlbit = (1 << 3), 489 .ctrlbit = (1 << 3),
526 }, { 490 }, {
527 .name = "fimc", 491 .name = "fimc",
528 .id = 2, 492 .devname = "s5p-fimc.2",
529 .parent = &clk_div_d1_bus.clk,
530 .enable = s5pc100_d1_1_ctrl, 493 .enable = s5pc100_d1_1_ctrl,
531 .ctrlbit = (1 << 4), 494 .ctrlbit = (1 << 4),
532 }, { 495 }, {
533 .name = "jpeg", 496 .name = "jpeg",
534 .id = -1,
535 .parent = &clk_div_d1_bus.clk, 497 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_1_ctrl, 498 .enable = s5pc100_d1_1_ctrl,
537 .ctrlbit = (1 << 5), 499 .ctrlbit = (1 << 5),
538 }, { 500 }, {
539 .name = "mipi-dsim", 501 .name = "mipi-dsim",
540 .id = -1,
541 .parent = &clk_div_d1_bus.clk, 502 .parent = &clk_div_d1_bus.clk,
542 .enable = s5pc100_d1_1_ctrl, 503 .enable = s5pc100_d1_1_ctrl,
543 .ctrlbit = (1 << 6), 504 .ctrlbit = (1 << 6),
544 }, { 505 }, {
545 .name = "mipi-csis", 506 .name = "mipi-csis",
546 .id = -1,
547 .parent = &clk_div_d1_bus.clk, 507 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_1_ctrl, 508 .enable = s5pc100_d1_1_ctrl,
549 .ctrlbit = (1 << 7), 509 .ctrlbit = (1 << 7),
550 }, { 510 }, {
551 .name = "g3d", 511 .name = "g3d",
552 .id = 0,
553 .parent = &clk_div_d1_bus.clk, 512 .parent = &clk_div_d1_bus.clk,
554 .enable = s5pc100_d1_0_ctrl, 513 .enable = s5pc100_d1_0_ctrl,
555 .ctrlbit = (1 << 8), 514 .ctrlbit = (1 << 8),
556 }, { 515 }, {
557 .name = "tv", 516 .name = "tv",
558 .id = -1,
559 .parent = &clk_div_d1_bus.clk, 517 .parent = &clk_div_d1_bus.clk,
560 .enable = s5pc100_d1_2_ctrl, 518 .enable = s5pc100_d1_2_ctrl,
561 .ctrlbit = (1 << 0), 519 .ctrlbit = (1 << 0),
562 }, { 520 }, {
563 .name = "vp", 521 .name = "vp",
564 .id = -1,
565 .parent = &clk_div_d1_bus.clk, 522 .parent = &clk_div_d1_bus.clk,
566 .enable = s5pc100_d1_2_ctrl, 523 .enable = s5pc100_d1_2_ctrl,
567 .ctrlbit = (1 << 1), 524 .ctrlbit = (1 << 1),
568 }, { 525 }, {
569 .name = "mixer", 526 .name = "mixer",
570 .id = -1,
571 .parent = &clk_div_d1_bus.clk, 527 .parent = &clk_div_d1_bus.clk,
572 .enable = s5pc100_d1_2_ctrl, 528 .enable = s5pc100_d1_2_ctrl,
573 .ctrlbit = (1 << 2), 529 .ctrlbit = (1 << 2),
574 }, { 530 }, {
575 .name = "hdmi", 531 .name = "hdmi",
576 .id = -1,
577 .parent = &clk_div_d1_bus.clk, 532 .parent = &clk_div_d1_bus.clk,
578 .enable = s5pc100_d1_2_ctrl, 533 .enable = s5pc100_d1_2_ctrl,
579 .ctrlbit = (1 << 3), 534 .ctrlbit = (1 << 3),
580 }, { 535 }, {
581 .name = "mfc", 536 .name = "mfc",
582 .id = -1,
583 .parent = &clk_div_d1_bus.clk, 537 .parent = &clk_div_d1_bus.clk,
584 .enable = s5pc100_d1_2_ctrl, 538 .enable = s5pc100_d1_2_ctrl,
585 .ctrlbit = (1 << 4), 539 .ctrlbit = (1 << 4),
586 }, { 540 }, {
587 .name = "apc", 541 .name = "apc",
588 .id = -1,
589 .parent = &clk_div_d1_bus.clk, 542 .parent = &clk_div_d1_bus.clk,
590 .enable = s5pc100_d1_3_ctrl, 543 .enable = s5pc100_d1_3_ctrl,
591 .ctrlbit = (1 << 2), 544 .ctrlbit = (1 << 2),
592 }, { 545 }, {
593 .name = "iec", 546 .name = "iec",
594 .id = -1,
595 .parent = &clk_div_d1_bus.clk, 547 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_3_ctrl, 548 .enable = s5pc100_d1_3_ctrl,
597 .ctrlbit = (1 << 3), 549 .ctrlbit = (1 << 3),
598 }, { 550 }, {
599 .name = "systimer", 551 .name = "systimer",
600 .id = -1,
601 .parent = &clk_div_d1_bus.clk, 552 .parent = &clk_div_d1_bus.clk,
602 .enable = s5pc100_d1_3_ctrl, 553 .enable = s5pc100_d1_3_ctrl,
603 .ctrlbit = (1 << 7), 554 .ctrlbit = (1 << 7),
604 }, { 555 }, {
605 .name = "watchdog", 556 .name = "watchdog",
606 .id = -1,
607 .parent = &clk_div_d1_bus.clk, 557 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_3_ctrl, 558 .enable = s5pc100_d1_3_ctrl,
609 .ctrlbit = (1 << 8), 559 .ctrlbit = (1 << 8),
610 }, { 560 }, {
611 .name = "rtc", 561 .name = "rtc",
612 .id = -1,
613 .parent = &clk_div_d1_bus.clk, 562 .parent = &clk_div_d1_bus.clk,
614 .enable = s5pc100_d1_3_ctrl, 563 .enable = s5pc100_d1_3_ctrl,
615 .ctrlbit = (1 << 9), 564 .ctrlbit = (1 << 9),
616 }, { 565 }, {
617 .name = "i2c", 566 .name = "i2c",
618 .id = 0, 567 .devname = "s3c2440-i2c.0",
619 .parent = &clk_div_d1_bus.clk, 568 .parent = &clk_div_d1_bus.clk,
620 .enable = s5pc100_d1_4_ctrl, 569 .enable = s5pc100_d1_4_ctrl,
621 .ctrlbit = (1 << 4), 570 .ctrlbit = (1 << 4),
622 }, { 571 }, {
623 .name = "i2c", 572 .name = "i2c",
624 .id = 1, 573 .devname = "s3c2440-i2c.1",
625 .parent = &clk_div_d1_bus.clk, 574 .parent = &clk_div_d1_bus.clk,
626 .enable = s5pc100_d1_4_ctrl, 575 .enable = s5pc100_d1_4_ctrl,
627 .ctrlbit = (1 << 5), 576 .ctrlbit = (1 << 5),
628 }, { 577 }, {
629 .name = "spi", 578 .name = "spi",
630 .id = 0, 579 .devname = "s3c64xx-spi.0",
631 .parent = &clk_div_d1_bus.clk, 580 .parent = &clk_div_d1_bus.clk,
632 .enable = s5pc100_d1_4_ctrl, 581 .enable = s5pc100_d1_4_ctrl,
633 .ctrlbit = (1 << 6), 582 .ctrlbit = (1 << 6),
634 }, { 583 }, {
635 .name = "spi", 584 .name = "spi",
636 .id = 1, 585 .devname = "s3c64xx-spi.1",
637 .parent = &clk_div_d1_bus.clk, 586 .parent = &clk_div_d1_bus.clk,
638 .enable = s5pc100_d1_4_ctrl, 587 .enable = s5pc100_d1_4_ctrl,
639 .ctrlbit = (1 << 7), 588 .ctrlbit = (1 << 7),
640 }, { 589 }, {
641 .name = "spi", 590 .name = "spi",
642 .id = 2, 591 .devname = "s3c64xx-spi.2",
643 .parent = &clk_div_d1_bus.clk, 592 .parent = &clk_div_d1_bus.clk,
644 .enable = s5pc100_d1_4_ctrl, 593 .enable = s5pc100_d1_4_ctrl,
645 .ctrlbit = (1 << 8), 594 .ctrlbit = (1 << 8),
646 }, { 595 }, {
647 .name = "irda", 596 .name = "irda",
648 .id = -1,
649 .parent = &clk_div_d1_bus.clk, 597 .parent = &clk_div_d1_bus.clk,
650 .enable = s5pc100_d1_4_ctrl, 598 .enable = s5pc100_d1_4_ctrl,
651 .ctrlbit = (1 << 9), 599 .ctrlbit = (1 << 9),
652 }, { 600 }, {
653 .name = "ccan", 601 .name = "ccan",
654 .id = 0,
655 .parent = &clk_div_d1_bus.clk, 602 .parent = &clk_div_d1_bus.clk,
656 .enable = s5pc100_d1_4_ctrl, 603 .enable = s5pc100_d1_4_ctrl,
657 .ctrlbit = (1 << 10), 604 .ctrlbit = (1 << 10),
658 }, { 605 }, {
659 .name = "ccan", 606 .name = "ccan",
660 .id = 1,
661 .parent = &clk_div_d1_bus.clk, 607 .parent = &clk_div_d1_bus.clk,
662 .enable = s5pc100_d1_4_ctrl, 608 .enable = s5pc100_d1_4_ctrl,
663 .ctrlbit = (1 << 11), 609 .ctrlbit = (1 << 11),
664 }, { 610 }, {
665 .name = "hsitx", 611 .name = "hsitx",
666 .id = -1,
667 .parent = &clk_div_d1_bus.clk, 612 .parent = &clk_div_d1_bus.clk,
668 .enable = s5pc100_d1_4_ctrl, 613 .enable = s5pc100_d1_4_ctrl,
669 .ctrlbit = (1 << 12), 614 .ctrlbit = (1 << 12),
670 }, { 615 }, {
671 .name = "hsirx", 616 .name = "hsirx",
672 .id = -1,
673 .parent = &clk_div_d1_bus.clk, 617 .parent = &clk_div_d1_bus.clk,
674 .enable = s5pc100_d1_4_ctrl, 618 .enable = s5pc100_d1_4_ctrl,
675 .ctrlbit = (1 << 13), 619 .ctrlbit = (1 << 13),
676 }, { 620 }, {
677 .name = "iis", 621 .name = "iis",
678 .id = 0, 622 .devname = "samsung-i2s.0",
679 .parent = &clk_div_pclkd1.clk, 623 .parent = &clk_div_pclkd1.clk,
680 .enable = s5pc100_d1_5_ctrl, 624 .enable = s5pc100_d1_5_ctrl,
681 .ctrlbit = (1 << 0), 625 .ctrlbit = (1 << 0),
682 }, { 626 }, {
683 .name = "iis", 627 .name = "iis",
684 .id = 1, 628 .devname = "samsung-i2s.1",
685 .parent = &clk_div_pclkd1.clk, 629 .parent = &clk_div_pclkd1.clk,
686 .enable = s5pc100_d1_5_ctrl, 630 .enable = s5pc100_d1_5_ctrl,
687 .ctrlbit = (1 << 1), 631 .ctrlbit = (1 << 1),
688 }, { 632 }, {
689 .name = "iis", 633 .name = "iis",
690 .id = 2, 634 .devname = "samsung-i2s.2",
691 .parent = &clk_div_pclkd1.clk, 635 .parent = &clk_div_pclkd1.clk,
692 .enable = s5pc100_d1_5_ctrl, 636 .enable = s5pc100_d1_5_ctrl,
693 .ctrlbit = (1 << 2), 637 .ctrlbit = (1 << 2),
694 }, { 638 }, {
695 .name = "ac97", 639 .name = "ac97",
696 .id = -1,
697 .parent = &clk_div_pclkd1.clk, 640 .parent = &clk_div_pclkd1.clk,
698 .enable = s5pc100_d1_5_ctrl, 641 .enable = s5pc100_d1_5_ctrl,
699 .ctrlbit = (1 << 3), 642 .ctrlbit = (1 << 3),
700 }, { 643 }, {
701 .name = "pcm", 644 .name = "pcm",
702 .id = 0, 645 .devname = "samsung-pcm.0",
703 .parent = &clk_div_pclkd1.clk, 646 .parent = &clk_div_pclkd1.clk,
704 .enable = s5pc100_d1_5_ctrl, 647 .enable = s5pc100_d1_5_ctrl,
705 .ctrlbit = (1 << 4), 648 .ctrlbit = (1 << 4),
706 }, { 649 }, {
707 .name = "pcm", 650 .name = "pcm",
708 .id = 1, 651 .devname = "samsung-pcm.1",
709 .parent = &clk_div_pclkd1.clk, 652 .parent = &clk_div_pclkd1.clk,
710 .enable = s5pc100_d1_5_ctrl, 653 .enable = s5pc100_d1_5_ctrl,
711 .ctrlbit = (1 << 5), 654 .ctrlbit = (1 << 5),
712 }, { 655 }, {
713 .name = "spdif", 656 .name = "spdif",
714 .id = -1,
715 .parent = &clk_div_pclkd1.clk, 657 .parent = &clk_div_pclkd1.clk,
716 .enable = s5pc100_d1_5_ctrl, 658 .enable = s5pc100_d1_5_ctrl,
717 .ctrlbit = (1 << 6), 659 .ctrlbit = (1 << 6),
718 }, { 660 }, {
719 .name = "adc", 661 .name = "adc",
720 .id = -1,
721 .parent = &clk_div_pclkd1.clk, 662 .parent = &clk_div_pclkd1.clk,
722 .enable = s5pc100_d1_5_ctrl, 663 .enable = s5pc100_d1_5_ctrl,
723 .ctrlbit = (1 << 7), 664 .ctrlbit = (1 << 7),
724 }, { 665 }, {
725 .name = "keypad", 666 .name = "keypad",
726 .id = -1,
727 .parent = &clk_div_pclkd1.clk, 667 .parent = &clk_div_pclkd1.clk,
728 .enable = s5pc100_d1_5_ctrl, 668 .enable = s5pc100_d1_5_ctrl,
729 .ctrlbit = (1 << 8), 669 .ctrlbit = (1 << 8),
730 }, { 670 }, {
731 .name = "spi_48m", 671 .name = "spi_48m",
732 .id = 0, 672 .devname = "s3c64xx-spi.0",
733 .parent = &clk_mout_48m.clk, 673 .parent = &clk_mout_48m.clk,
734 .enable = s5pc100_sclk0_ctrl, 674 .enable = s5pc100_sclk0_ctrl,
735 .ctrlbit = (1 << 7), 675 .ctrlbit = (1 << 7),
736 }, { 676 }, {
737 .name = "spi_48m", 677 .name = "spi_48m",
738 .id = 1, 678 .devname = "s3c64xx-spi.1",
739 .parent = &clk_mout_48m.clk, 679 .parent = &clk_mout_48m.clk,
740 .enable = s5pc100_sclk0_ctrl, 680 .enable = s5pc100_sclk0_ctrl,
741 .ctrlbit = (1 << 8), 681 .ctrlbit = (1 << 8),
742 }, { 682 }, {
743 .name = "spi_48m", 683 .name = "spi_48m",
744 .id = 2, 684 .devname = "s3c64xx-spi.2",
745 .parent = &clk_mout_48m.clk, 685 .parent = &clk_mout_48m.clk,
746 .enable = s5pc100_sclk0_ctrl, 686 .enable = s5pc100_sclk0_ctrl,
747 .ctrlbit = (1 << 9), 687 .ctrlbit = (1 << 9),
748 }, { 688 }, {
749 .name = "mmc_48m", 689 .name = "mmc_48m",
750 .id = 0, 690 .devname = "s3c-sdhci.0",
751 .parent = &clk_mout_48m.clk, 691 .parent = &clk_mout_48m.clk,
752 .enable = s5pc100_sclk0_ctrl, 692 .enable = s5pc100_sclk0_ctrl,
753 .ctrlbit = (1 << 15), 693 .ctrlbit = (1 << 15),
754 }, { 694 }, {
755 .name = "mmc_48m", 695 .name = "mmc_48m",
756 .id = 1, 696 .devname = "s3c-sdhci.1",
757 .parent = &clk_mout_48m.clk, 697 .parent = &clk_mout_48m.clk,
758 .enable = s5pc100_sclk0_ctrl, 698 .enable = s5pc100_sclk0_ctrl,
759 .ctrlbit = (1 << 16), 699 .ctrlbit = (1 << 16),
760 }, { 700 }, {
761 .name = "mmc_48m", 701 .name = "mmc_48m",
762 .id = 2, 702 .devname = "s3c-sdhci.2",
763 .parent = &clk_mout_48m.clk, 703 .parent = &clk_mout_48m.clk,
764 .enable = s5pc100_sclk0_ctrl, 704 .enable = s5pc100_sclk0_ctrl,
765 .ctrlbit = (1 << 17), 705 .ctrlbit = (1 << 17),
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
768 708
769static struct clk clk_vclk54m = { 709static struct clk clk_vclk54m = {
770 .name = "vclk_54m", 710 .name = "vclk_54m",
771 .id = -1,
772 .rate = 54000000, 711 .rate = 54000000,
773}; 712};
774 713
775static struct clk clk_i2scdclk0 = { 714static struct clk clk_i2scdclk0 = {
776 .name = "i2s_cdclk0", 715 .name = "i2s_cdclk0",
777 .id = -1,
778}; 716};
779 717
780static struct clk clk_i2scdclk1 = { 718static struct clk clk_i2scdclk1 = {
781 .name = "i2s_cdclk1", 719 .name = "i2s_cdclk1",
782 .id = -1,
783}; 720};
784 721
785static struct clk clk_i2scdclk2 = { 722static struct clk clk_i2scdclk2 = {
786 .name = "i2s_cdclk2", 723 .name = "i2s_cdclk2",
787 .id = -1,
788}; 724};
789 725
790static struct clk clk_pcmcdclk0 = { 726static struct clk clk_pcmcdclk0 = {
791 .name = "pcm_cdclk0", 727 .name = "pcm_cdclk0",
792 .id = -1,
793}; 728};
794 729
795static struct clk clk_pcmcdclk1 = { 730static struct clk clk_pcmcdclk1 = {
796 .name = "pcm_cdclk1", 731 .name = "pcm_cdclk1",
797 .id = -1,
798}; 732};
799 733
800static struct clk *clk_src_group1_list[] = { 734static struct clk *clk_src_group1_list[] = {
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
836static struct clksrc_clk clk_sclk_audio0 = { 770static struct clksrc_clk clk_sclk_audio0 = {
837 .clk = { 771 .clk = {
838 .name = "sclk_audio", 772 .name = "sclk_audio",
839 .id = 0, 773 .devname = "samsung-pcm.0",
840 .ctrlbit = (1 << 8), 774 .ctrlbit = (1 << 8),
841 .enable = s5pc100_sclk1_ctrl, 775 .enable = s5pc100_sclk1_ctrl,
842 }, 776 },
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
862static struct clksrc_clk clk_sclk_audio1 = { 796static struct clksrc_clk clk_sclk_audio1 = {
863 .clk = { 797 .clk = {
864 .name = "sclk_audio", 798 .name = "sclk_audio",
865 .id = 1, 799 .devname = "samsung-pcm.1",
866 .ctrlbit = (1 << 9), 800 .ctrlbit = (1 << 9),
867 .enable = s5pc100_sclk1_ctrl, 801 .enable = s5pc100_sclk1_ctrl,
868 }, 802 },
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
887static struct clksrc_clk clk_sclk_audio2 = { 821static struct clksrc_clk clk_sclk_audio2 = {
888 .clk = { 822 .clk = {
889 .name = "sclk_audio", 823 .name = "sclk_audio",
890 .id = 2, 824 .devname = "samsung-pcm.2",
891 .ctrlbit = (1 << 10), 825 .ctrlbit = (1 << 10),
892 .enable = s5pc100_sclk1_ctrl, 826 .enable = s5pc100_sclk1_ctrl,
893 }, 827 },
@@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
1014static struct clksrc_clk clk_sclk_spdif = { 948static struct clksrc_clk clk_sclk_spdif = {
1015 .clk = { 949 .clk = {
1016 .name = "sclk_spdif", 950 .name = "sclk_spdif",
1017 .id = -1,
1018 .ctrlbit = (1 << 11), 951 .ctrlbit = (1 << 11),
1019 .enable = s5pc100_sclk1_ctrl, 952 .enable = s5pc100_sclk1_ctrl,
1020 .ops = &s5pc100_sclk_spdif_ops, 953 .ops = &s5pc100_sclk_spdif_ops,
@@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
1027 { 960 {
1028 .clk = { 961 .clk = {
1029 .name = "sclk_spi", 962 .name = "sclk_spi",
1030 .id = 0, 963 .devname = "s3c64xx-spi.0",
1031 .ctrlbit = (1 << 4), 964 .ctrlbit = (1 << 4),
1032 .enable = s5pc100_sclk0_ctrl, 965 .enable = s5pc100_sclk0_ctrl,
1033 966
@@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
1038 }, { 971 }, {
1039 .clk = { 972 .clk = {
1040 .name = "sclk_spi", 973 .name = "sclk_spi",
1041 .id = 1, 974 .devname = "s3c64xx-spi.1",
1042 .ctrlbit = (1 << 5), 975 .ctrlbit = (1 << 5),
1043 .enable = s5pc100_sclk0_ctrl, 976 .enable = s5pc100_sclk0_ctrl,
1044 977
@@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
1049 }, { 982 }, {
1050 .clk = { 983 .clk = {
1051 .name = "sclk_spi", 984 .name = "sclk_spi",
1052 .id = 2, 985 .devname = "s3c64xx-spi.2",
1053 .ctrlbit = (1 << 6), 986 .ctrlbit = (1 << 6),
1054 .enable = s5pc100_sclk0_ctrl, 987 .enable = s5pc100_sclk0_ctrl,
1055 988
@@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
1060 }, { 993 }, {
1061 .clk = { 994 .clk = {
1062 .name = "uclk1", 995 .name = "uclk1",
1063 .id = -1,
1064 .ctrlbit = (1 << 3), 996 .ctrlbit = (1 << 3),
1065 .enable = s5pc100_sclk0_ctrl, 997 .enable = s5pc100_sclk0_ctrl,
1066 998
@@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
1071 }, { 1003 }, {
1072 .clk = { 1004 .clk = {
1073 .name = "sclk_mixer", 1005 .name = "sclk_mixer",
1074 .id = -1,
1075 .ctrlbit = (1 << 6), 1006 .ctrlbit = (1 << 6),
1076 .enable = s5pc100_sclk0_ctrl, 1007 .enable = s5pc100_sclk0_ctrl,
1077 1008
@@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
1081 }, { 1012 }, {
1082 .clk = { 1013 .clk = {
1083 .name = "sclk_lcd", 1014 .name = "sclk_lcd",
1084 .id = -1,
1085 .ctrlbit = (1 << 0), 1015 .ctrlbit = (1 << 0),
1086 .enable = s5pc100_sclk1_ctrl, 1016 .enable = s5pc100_sclk1_ctrl,
1087 1017
@@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
1092 }, { 1022 }, {
1093 .clk = { 1023 .clk = {
1094 .name = "sclk_fimc", 1024 .name = "sclk_fimc",
1095 .id = 0, 1025 .devname = "s5p-fimc.0",
1096 .ctrlbit = (1 << 1), 1026 .ctrlbit = (1 << 1),
1097 .enable = s5pc100_sclk1_ctrl, 1027 .enable = s5pc100_sclk1_ctrl,
1098 1028
@@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
1103 }, { 1033 }, {
1104 .clk = { 1034 .clk = {
1105 .name = "sclk_fimc", 1035 .name = "sclk_fimc",
1106 .id = 1, 1036 .devname = "s5p-fimc.1",
1107 .ctrlbit = (1 << 2), 1037 .ctrlbit = (1 << 2),
1108 .enable = s5pc100_sclk1_ctrl, 1038 .enable = s5pc100_sclk1_ctrl,
1109 1039
@@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
1114 }, { 1044 }, {
1115 .clk = { 1045 .clk = {
1116 .name = "sclk_fimc", 1046 .name = "sclk_fimc",
1117 .id = 2, 1047 .devname = "s5p-fimc.2",
1118 .ctrlbit = (1 << 3), 1048 .ctrlbit = (1 << 3),
1119 .enable = s5pc100_sclk1_ctrl, 1049 .enable = s5pc100_sclk1_ctrl,
1120 1050
@@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
1125 }, { 1055 }, {
1126 .clk = { 1056 .clk = {
1127 .name = "sclk_mmc", 1057 .name = "sclk_mmc",
1128 .id = 0, 1058 .devname = "s3c-sdhci.0",
1129 .ctrlbit = (1 << 12), 1059 .ctrlbit = (1 << 12),
1130 .enable = s5pc100_sclk1_ctrl, 1060 .enable = s5pc100_sclk1_ctrl,
1131 1061
@@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
1136 }, { 1066 }, {
1137 .clk = { 1067 .clk = {
1138 .name = "sclk_mmc", 1068 .name = "sclk_mmc",
1139 .id = 1, 1069 .devname = "s3c-sdhci.1",
1140 .ctrlbit = (1 << 13), 1070 .ctrlbit = (1 << 13),
1141 .enable = s5pc100_sclk1_ctrl, 1071 .enable = s5pc100_sclk1_ctrl,
1142 1072
@@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
1147 }, { 1077 }, {
1148 .clk = { 1078 .clk = {
1149 .name = "sclk_mmc", 1079 .name = "sclk_mmc",
1150 .id = 2, 1080 .devname = "s3c-sdhci.2",
1151 .ctrlbit = (1 << 14), 1081 .ctrlbit = (1 << 14),
1152 .enable = s5pc100_sclk1_ctrl, 1082 .enable = s5pc100_sclk1_ctrl,
1153 1083
@@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
1158 }, { 1088 }, {
1159 .clk = { 1089 .clk = {
1160 .name = "sclk_irda", 1090 .name = "sclk_irda",
1161 .id = 2,
1162 .ctrlbit = (1 << 10), 1091 .ctrlbit = (1 << 10),
1163 .enable = s5pc100_sclk0_ctrl, 1092 .enable = s5pc100_sclk0_ctrl,
1164 1093
@@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
1169 }, { 1098 }, {
1170 .clk = { 1099 .clk = {
1171 .name = "sclk_irda", 1100 .name = "sclk_irda",
1172 .id = -1,
1173 .ctrlbit = (1 << 10), 1101 .ctrlbit = (1 << 10),
1174 .enable = s5pc100_sclk0_ctrl, 1102 .enable = s5pc100_sclk0_ctrl,
1175 1103
@@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
1180 }, { 1108 }, {
1181 .clk = { 1109 .clk = {
1182 .name = "sclk_pwi", 1110 .name = "sclk_pwi",
1183 .id = -1,
1184 .ctrlbit = (1 << 1), 1111 .ctrlbit = (1 << 1),
1185 .enable = s5pc100_sclk0_ctrl, 1112 .enable = s5pc100_sclk0_ctrl,
1186 1113
@@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
1191 }, { 1118 }, {
1192 .clk = { 1119 .clk = {
1193 .name = "sclk_uhost", 1120 .name = "sclk_uhost",
1194 .id = -1,
1195 .ctrlbit = (1 << 11), 1121 .ctrlbit = (1 << 11),
1196 .enable = s5pc100_sclk0_ctrl, 1122 .enable = s5pc100_sclk0_ctrl,
1197 1123
@@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1291static struct clk init_clocks[] = { 1217static struct clk init_clocks[] = {
1292 { 1218 {
1293 .name = "tzic", 1219 .name = "tzic",
1294 .id = -1,
1295 .parent = &clk_div_d0_bus.clk, 1220 .parent = &clk_div_d0_bus.clk,
1296 .enable = s5pc100_d0_0_ctrl, 1221 .enable = s5pc100_d0_0_ctrl,
1297 .ctrlbit = (1 << 1), 1222 .ctrlbit = (1 << 1),
1298 }, { 1223 }, {
1299 .name = "intc", 1224 .name = "intc",
1300 .id = -1,
1301 .parent = &clk_div_d0_bus.clk, 1225 .parent = &clk_div_d0_bus.clk,
1302 .enable = s5pc100_d0_0_ctrl, 1226 .enable = s5pc100_d0_0_ctrl,
1303 .ctrlbit = (1 << 0), 1227 .ctrlbit = (1 << 0),
1304 }, { 1228 }, {
1305 .name = "ebi", 1229 .name = "ebi",
1306 .id = -1,
1307 .parent = &clk_div_d0_bus.clk, 1230 .parent = &clk_div_d0_bus.clk,
1308 .enable = s5pc100_d0_1_ctrl, 1231 .enable = s5pc100_d0_1_ctrl,
1309 .ctrlbit = (1 << 5), 1232 .ctrlbit = (1 << 5),
1310 }, { 1233 }, {
1311 .name = "intmem", 1234 .name = "intmem",
1312 .id = -1,
1313 .parent = &clk_div_d0_bus.clk, 1235 .parent = &clk_div_d0_bus.clk,
1314 .enable = s5pc100_d0_1_ctrl, 1236 .enable = s5pc100_d0_1_ctrl,
1315 .ctrlbit = (1 << 4), 1237 .ctrlbit = (1 << 4),
1316 }, { 1238 }, {
1317 .name = "sromc", 1239 .name = "sromc",
1318 .id = -1,
1319 .parent = &clk_div_d0_bus.clk, 1240 .parent = &clk_div_d0_bus.clk,
1320 .enable = s5pc100_d0_1_ctrl, 1241 .enable = s5pc100_d0_1_ctrl,
1321 .ctrlbit = (1 << 1), 1242 .ctrlbit = (1 << 1),
1322 }, { 1243 }, {
1323 .name = "dmc", 1244 .name = "dmc",
1324 .id = -1,
1325 .parent = &clk_div_d0_bus.clk, 1245 .parent = &clk_div_d0_bus.clk,
1326 .enable = s5pc100_d0_1_ctrl, 1246 .enable = s5pc100_d0_1_ctrl,
1327 .ctrlbit = (1 << 0), 1247 .ctrlbit = (1 << 0),
1328 }, { 1248 }, {
1329 .name = "chipid", 1249 .name = "chipid",
1330 .id = -1,
1331 .parent = &clk_div_d0_bus.clk, 1250 .parent = &clk_div_d0_bus.clk,
1332 .enable = s5pc100_d0_1_ctrl, 1251 .enable = s5pc100_d0_1_ctrl,
1333 .ctrlbit = (1 << 0), 1252 .ctrlbit = (1 << 0),
1334 }, { 1253 }, {
1335 .name = "gpio", 1254 .name = "gpio",
1336 .id = -1,
1337 .parent = &clk_div_d1_bus.clk, 1255 .parent = &clk_div_d1_bus.clk,
1338 .enable = s5pc100_d1_3_ctrl, 1256 .enable = s5pc100_d1_3_ctrl,
1339 .ctrlbit = (1 << 1), 1257 .ctrlbit = (1 << 1),
1340 }, { 1258 }, {
1341 .name = "uart", 1259 .name = "uart",
1342 .id = 0, 1260 .devname = "s3c6400-uart.0",
1343 .parent = &clk_div_d1_bus.clk, 1261 .parent = &clk_div_d1_bus.clk,
1344 .enable = s5pc100_d1_4_ctrl, 1262 .enable = s5pc100_d1_4_ctrl,
1345 .ctrlbit = (1 << 0), 1263 .ctrlbit = (1 << 0),
1346 }, { 1264 }, {
1347 .name = "uart", 1265 .name = "uart",
1348 .id = 1, 1266 .devname = "s3c6400-uart.1",
1349 .parent = &clk_div_d1_bus.clk, 1267 .parent = &clk_div_d1_bus.clk,
1350 .enable = s5pc100_d1_4_ctrl, 1268 .enable = s5pc100_d1_4_ctrl,
1351 .ctrlbit = (1 << 1), 1269 .ctrlbit = (1 << 1),
1352 }, { 1270 }, {
1353 .name = "uart", 1271 .name = "uart",
1354 .id = 2, 1272 .devname = "s3c6400-uart.2",
1355 .parent = &clk_div_d1_bus.clk, 1273 .parent = &clk_div_d1_bus.clk,
1356 .enable = s5pc100_d1_4_ctrl, 1274 .enable = s5pc100_d1_4_ctrl,
1357 .ctrlbit = (1 << 2), 1275 .ctrlbit = (1 << 2),
1358 }, { 1276 }, {
1359 .name = "uart", 1277 .name = "uart",
1360 .id = 3, 1278 .devname = "s3c6400-uart.3",
1361 .parent = &clk_div_d1_bus.clk, 1279 .parent = &clk_div_d1_bus.clk,
1362 .enable = s5pc100_d1_4_ctrl, 1280 .enable = s5pc100_d1_4_ctrl,
1363 .ctrlbit = (1 << 3), 1281 .ctrlbit = (1 << 3),
1364 }, { 1282 }, {
1365 .name = "timers", 1283 .name = "timers",
1366 .id = -1,
1367 .parent = &clk_div_d1_bus.clk, 1284 .parent = &clk_div_d1_bus.clk,
1368 .enable = s5pc100_d1_3_ctrl, 1285 .enable = s5pc100_d1_3_ctrl,
1369 .ctrlbit = (1 << 6), 1286 .ctrlbit = (1 << 6),
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 04:39:32 -0500