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-rw-r--r--arch/arm/mach-s5pc100/clock.c290
1 files changed, 177 insertions, 113 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709da713..247194dd366c 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -27,7 +27,8 @@
27#include <plat/pll.h> 27#include <plat/pll.h>
28#include <plat/s5p-clock.h> 28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h> 29#include <plat/clock-clksrc.h>
30#include <plat/s5pc100.h> 30
31#include "common.h"
31 32
32static struct clk s5p_clk_otgphy = { 33static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy", 34 .name = "otg_phy",
@@ -426,24 +427,6 @@ static struct clk init_clocks_off[] = {
426 .enable = s5pc100_d0_2_ctrl, 427 .enable = s5pc100_d0_2_ctrl,
427 .ctrlbit = (1 << 1), 428 .ctrlbit = (1 << 1),
428 }, { 429 }, {
429 .name = "hsmmc",
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 7),
434 }, {
435 .name = "hsmmc",
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
439 .ctrlbit = (1 << 6),
440 }, {
441 .name = "hsmmc",
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 5),
446 }, {
447 .name = "modemif", 430 .name = "modemif",
448 .parent = &clk_div_d1_bus.clk, 431 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl, 432 .enable = s5pc100_d1_0_ctrl,
@@ -673,24 +656,6 @@ static struct clk init_clocks_off[] = {
673 .enable = s5pc100_d1_5_ctrl, 656 .enable = s5pc100_d1_5_ctrl,
674 .ctrlbit = (1 << 8), 657 .ctrlbit = (1 << 8),
675 }, { 658 }, {
676 .name = "spi_48m",
677 .devname = "s3c64xx-spi.0",
678 .parent = &clk_mout_48m.clk,
679 .enable = s5pc100_sclk0_ctrl,
680 .ctrlbit = (1 << 7),
681 }, {
682 .name = "spi_48m",
683 .devname = "s3c64xx-spi.1",
684 .parent = &clk_mout_48m.clk,
685 .enable = s5pc100_sclk0_ctrl,
686 .ctrlbit = (1 << 8),
687 }, {
688 .name = "spi_48m",
689 .devname = "s3c64xx-spi.2",
690 .parent = &clk_mout_48m.clk,
691 .enable = s5pc100_sclk0_ctrl,
692 .ctrlbit = (1 << 9),
693 }, {
694 .name = "mmc_48m", 659 .name = "mmc_48m",
695 .devname = "s3c-sdhci.0", 660 .devname = "s3c-sdhci.0",
696 .parent = &clk_mout_48m.clk, 661 .parent = &clk_mout_48m.clk,
@@ -711,6 +676,54 @@ static struct clk init_clocks_off[] = {
711 }, 676 },
712}; 677};
713 678
679static struct clk clk_hsmmc2 = {
680 .name = "hsmmc",
681 .devname = "s3c-sdhci.2",
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_0_ctrl,
684 .ctrlbit = (1 << 7),
685};
686
687static struct clk clk_hsmmc1 = {
688 .name = "hsmmc",
689 .devname = "s3c-sdhci.1",
690 .parent = &clk_div_d1_bus.clk,
691 .enable = s5pc100_d1_0_ctrl,
692 .ctrlbit = (1 << 6),
693};
694
695static struct clk clk_hsmmc0 = {
696 .name = "hsmmc",
697 .devname = "s3c-sdhci.0",
698 .parent = &clk_div_d1_bus.clk,
699 .enable = s5pc100_d1_0_ctrl,
700 .ctrlbit = (1 << 5),
701};
702
703static struct clk clk_48m_spi0 = {
704 .name = "spi_48m",
705 .devname = "s3c64xx-spi.0",
706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl,
708 .ctrlbit = (1 << 7),
709};
710
711static struct clk clk_48m_spi1 = {
712 .name = "spi_48m",
713 .devname = "s3c64xx-spi.1",
714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl,
716 .ctrlbit = (1 << 8),
717};
718
719static struct clk clk_48m_spi2 = {
720 .name = "spi_48m",
721 .devname = "s3c64xx-spi.2",
722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl,
724 .ctrlbit = (1 << 9),
725};
726
714static struct clk clk_vclk54m = { 727static struct clk clk_vclk54m = {
715 .name = "vclk_54m", 728 .name = "vclk_54m",
716 .rate = 54000000, 729 .rate = 54000000,
@@ -929,49 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = {
929static struct clksrc_clk clksrcs[] = { 942static struct clksrc_clk clksrcs[] = {
930 { 943 {
931 .clk = { 944 .clk = {
932 .name = "sclk_spi",
933 .devname = "s3c64xx-spi.0",
934 .ctrlbit = (1 << 4),
935 .enable = s5pc100_sclk0_ctrl,
936
937 },
938 .sources = &clk_src_group1,
939 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
940 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
941 }, {
942 .clk = {
943 .name = "sclk_spi",
944 .devname = "s3c64xx-spi.1",
945 .ctrlbit = (1 << 5),
946 .enable = s5pc100_sclk0_ctrl,
947
948 },
949 .sources = &clk_src_group1,
950 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
951 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
952 }, {
953 .clk = {
954 .name = "sclk_spi",
955 .devname = "s3c64xx-spi.2",
956 .ctrlbit = (1 << 6),
957 .enable = s5pc100_sclk0_ctrl,
958
959 },
960 .sources = &clk_src_group1,
961 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
963 }, {
964 .clk = {
965 .name = "uclk1",
966 .ctrlbit = (1 << 3),
967 .enable = s5pc100_sclk0_ctrl,
968
969 },
970 .sources = &clk_src_group2,
971 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
972 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
973 }, {
974 .clk = {
975 .name = "sclk_mixer", 945 .name = "sclk_mixer",
976 .ctrlbit = (1 << 6), 946 .ctrlbit = (1 << 6),
977 .enable = s5pc100_sclk0_ctrl, 947 .enable = s5pc100_sclk0_ctrl,
@@ -1024,39 +994,6 @@ static struct clksrc_clk clksrcs[] = {
1024 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 994 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1025 }, { 995 }, {
1026 .clk = { 996 .clk = {
1027 .name = "sclk_mmc",
1028 .devname = "s3c-sdhci.0",
1029 .ctrlbit = (1 << 12),
1030 .enable = s5pc100_sclk1_ctrl,
1031
1032 },
1033 .sources = &clk_src_mmc0,
1034 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1035 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1036 }, {
1037 .clk = {
1038 .name = "sclk_mmc",
1039 .devname = "s3c-sdhci.1",
1040 .ctrlbit = (1 << 13),
1041 .enable = s5pc100_sclk1_ctrl,
1042
1043 },
1044 .sources = &clk_src_mmc12,
1045 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1046 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1047 }, {
1048 .clk = {
1049 .name = "sclk_mmc",
1050 .devname = "s3c-sdhci.2",
1051 .ctrlbit = (1 << 14),
1052 .enable = s5pc100_sclk1_ctrl,
1053
1054 },
1055 .sources = &clk_src_mmc12,
1056 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1057 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1058 }, {
1059 .clk = {
1060 .name = "sclk_irda", 997 .name = "sclk_irda",
1061 .ctrlbit = (1 << 10), 998 .ctrlbit = (1 << 10),
1062 .enable = s5pc100_sclk0_ctrl, 999 .enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1035,89 @@ static struct clksrc_clk clksrcs[] = {
1098 }, 1035 },
1099}; 1036};
1100 1037
1038static struct clksrc_clk clk_sclk_uart = {
1039 .clk = {
1040 .name = "uclk1",
1041 .ctrlbit = (1 << 3),
1042 .enable = s5pc100_sclk0_ctrl,
1043 },
1044 .sources = &clk_src_group2,
1045 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1046 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1047};
1048
1049static struct clksrc_clk clk_sclk_mmc0 = {
1050 .clk = {
1051 .name = "sclk_mmc",
1052 .devname = "s3c-sdhci.0",
1053 .ctrlbit = (1 << 12),
1054 .enable = s5pc100_sclk1_ctrl,
1055 },
1056 .sources = &clk_src_mmc0,
1057 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1058 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1059};
1060
1061static struct clksrc_clk clk_sclk_mmc1 = {
1062 .clk = {
1063 .name = "sclk_mmc",
1064 .devname = "s3c-sdhci.1",
1065 .ctrlbit = (1 << 13),
1066 .enable = s5pc100_sclk1_ctrl,
1067 },
1068 .sources = &clk_src_mmc12,
1069 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1070 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1071};
1072
1073static struct clksrc_clk clk_sclk_mmc2 = {
1074 .clk = {
1075 .name = "sclk_mmc",
1076 .devname = "s3c-sdhci.2",
1077 .ctrlbit = (1 << 14),
1078 .enable = s5pc100_sclk1_ctrl,
1079 },
1080 .sources = &clk_src_mmc12,
1081 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1082 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1083};
1084
1085static struct clksrc_clk clk_sclk_spi0 = {
1086 .clk = {
1087 .name = "sclk_spi",
1088 .devname = "s3c64xx-spi.0",
1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl,
1091 },
1092 .sources = &clk_src_group1,
1093 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1094 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1095};
1096
1097static struct clksrc_clk clk_sclk_spi1 = {
1098 .clk = {
1099 .name = "sclk_spi",
1100 .devname = "s3c64xx-spi.1",
1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl,
1103 },
1104 .sources = &clk_src_group1,
1105 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1106 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1107};
1108
1109static struct clksrc_clk clk_sclk_spi2 = {
1110 .clk = {
1111 .name = "sclk_spi",
1112 .devname = "s3c64xx-spi.2",
1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl,
1115 },
1116 .sources = &clk_src_group1,
1117 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1118 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1119};
1120
1101/* Clock initialisation code */ 1121/* Clock initialisation code */
1102static struct clksrc_clk *sysclks[] = { 1122static struct clksrc_clk *sysclks[] = {
1103 &clk_mout_apll, 1123 &clk_mout_apll,
@@ -1127,6 +1147,25 @@ static struct clksrc_clk *sysclks[] = {
1127 &clk_sclk_spdif, 1147 &clk_sclk_spdif,
1128}; 1148};
1129 1149
1150static struct clk *clk_cdev[] = {
1151 &clk_hsmmc0,
1152 &clk_hsmmc1,
1153 &clk_hsmmc2,
1154 &clk_48m_spi0,
1155 &clk_48m_spi1,
1156 &clk_48m_spi2,
1157};
1158
1159static struct clksrc_clk *clksrc_cdev[] = {
1160 &clk_sclk_uart,
1161 &clk_sclk_mmc0,
1162 &clk_sclk_mmc1,
1163 &clk_sclk_mmc2,
1164 &clk_sclk_spi0,
1165 &clk_sclk_spi1,
1166 &clk_sclk_spi2,
1167};
1168
1130void __init_or_cpufreq s5pc100_setup_clocks(void) 1169void __init_or_cpufreq s5pc100_setup_clocks(void)
1131{ 1170{
1132 unsigned long xtal; 1171 unsigned long xtal;
@@ -1266,6 +1305,24 @@ static struct clk *clks[] __initdata = {
1266 &clk_pcmcdclk1, 1305 &clk_pcmcdclk1,
1267}; 1306};
1268 1307
1308static struct clk_lookup s5pc100_clk_lookup[] = {
1309 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1310 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1311 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1312 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1313 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1314 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1324};
1325
1269void __init s5pc100_register_clocks(void) 1326void __init s5pc100_register_clocks(void)
1270{ 1327{
1271 int ptr; 1328 int ptr;
@@ -1277,9 +1334,16 @@ void __init s5pc100_register_clocks(void)
1277 1334
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1335 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1336 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1337 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1338 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1280 1339
1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1340 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1341 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1342 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1343
1344 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346 s3c_disable_clocks(clk_cdev[ptr], 1);
1283 1347
1284 s3c24xx_register_clock(&dummy_apb_pclk); 1348 s3c24xx_register_clock(&dummy_apb_pclk);
1285 1349
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 21:52:00 -0500