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Diffstat (limited to 'arch/arm/mach-s5pc100/clock.c')
-rw-r--r--arch/arm/mach-s5pc100/clock.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4ea2010..926219791f0d 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
564 .ctrlbit = (1 << 5), 564 .ctrlbit = (1 << 5),
565 }, { 565 }, {
566 .name = "spi", 566 .name = "spi",
567 .devname = "s3c64xx-spi.0", 567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk, 568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl, 569 .enable = s5pc100_d1_4_ctrl,
570 .ctrlbit = (1 << 6), 570 .ctrlbit = (1 << 6),
571 }, { 571 }, {
572 .name = "spi", 572 .name = "spi",
573 .devname = "s3c64xx-spi.1", 573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk, 574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl, 575 .enable = s5pc100_d1_4_ctrl,
576 .ctrlbit = (1 << 7), 576 .ctrlbit = (1 << 7),
577 }, { 577 }, {
578 .name = "spi", 578 .name = "spi",
579 .devname = "s3c64xx-spi.2", 579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk, 580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl, 581 .enable = s5pc100_d1_4_ctrl,
582 .ctrlbit = (1 << 8), 582 .ctrlbit = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
702 702
703static struct clk clk_48m_spi0 = { 703static struct clk clk_48m_spi0 = {
704 .name = "spi_48m", 704 .name = "spi_48m",
705 .devname = "s3c64xx-spi.0", 705 .devname = "s5pc100-spi.0",
706 .parent = &clk_mout_48m.clk, 706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl, 707 .enable = s5pc100_sclk0_ctrl,
708 .ctrlbit = (1 << 7), 708 .ctrlbit = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
710 710
711static struct clk clk_48m_spi1 = { 711static struct clk clk_48m_spi1 = {
712 .name = "spi_48m", 712 .name = "spi_48m",
713 .devname = "s3c64xx-spi.1", 713 .devname = "s5pc100-spi.1",
714 .parent = &clk_mout_48m.clk, 714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl, 715 .enable = s5pc100_sclk0_ctrl,
716 .ctrlbit = (1 << 8), 716 .ctrlbit = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
718 718
719static struct clk clk_48m_spi2 = { 719static struct clk clk_48m_spi2 = {
720 .name = "spi_48m", 720 .name = "spi_48m",
721 .devname = "s3c64xx-spi.2", 721 .devname = "s5pc100-spi.2",
722 .parent = &clk_mout_48m.clk, 722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl, 723 .enable = s5pc100_sclk0_ctrl,
724 .ctrlbit = (1 << 9), 724 .ctrlbit = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
1085static struct clksrc_clk clk_sclk_spi0 = { 1085static struct clksrc_clk clk_sclk_spi0 = {
1086 .clk = { 1086 .clk = {
1087 .name = "sclk_spi", 1087 .name = "sclk_spi",
1088 .devname = "s3c64xx-spi.0", 1088 .devname = "s5pc100-spi.0",
1089 .ctrlbit = (1 << 4), 1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl, 1090 .enable = s5pc100_sclk0_ctrl,
1091 }, 1091 },
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
1097static struct clksrc_clk clk_sclk_spi1 = { 1097static struct clksrc_clk clk_sclk_spi1 = {
1098 .clk = { 1098 .clk = {
1099 .name = "sclk_spi", 1099 .name = "sclk_spi",
1100 .devname = "s3c64xx-spi.1", 1100 .devname = "s5pc100-spi.1",
1101 .ctrlbit = (1 << 5), 1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl, 1102 .enable = s5pc100_sclk0_ctrl,
1103 }, 1103 },
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
1109static struct clksrc_clk clk_sclk_spi2 = { 1109static struct clksrc_clk clk_sclk_spi2 = {
1110 .clk = { 1110 .clk = {
1111 .name = "sclk_spi", 1111 .name = "sclk_spi",
1112 .devname = "s3c64xx-spi.2", 1112 .devname = "s5pc100-spi.2",
1113 .ctrlbit = (1 << 6), 1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl, 1114 .enable = s5pc100_sclk0_ctrl,
1115 }, 1115 },
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), 1318 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), 1319 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), 1320 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), 1321 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), 1322 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), 1323 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1324}; 1324};
1325 1325
1326void __init s5pc100_register_clocks(void) 1326void __init s5pc100_register_clocks(void)