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-rw-r--r--arch/arm/mach-s5pc100/clock.c1358
1 files changed, 1358 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
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1/* linux/arch/arm/mach-s5pc100/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22
23#include <plat/cpu-freq.h>
24#include <mach/regs-clock.h>
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/pll.h>
28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h>
30#include <plat/s5pc100.h>
31
32static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy",
34 .id = -1,
35};
36
37static struct clk *clk_src_mout_href_list[] = {
38 [0] = &s5p_clk_27m,
39 [1] = &clk_fin_hpll,
40};
41
42static struct clksrc_sources clk_src_mout_href = {
43 .sources = clk_src_mout_href_list,
44 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
45};
46
47static struct clksrc_clk clk_mout_href = {
48 .clk = {
49 .name = "mout_href",
50 .id = -1,
51 },
52 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
54};
55
56static struct clk *clk_src_mout_48m_list[] = {
57 [0] = &clk_xusbxti,
58 [1] = &s5p_clk_otgphy,
59};
60
61static struct clksrc_sources clk_src_mout_48m = {
62 .sources = clk_src_mout_48m_list,
63 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
64};
65
66static struct clksrc_clk clk_mout_48m = {
67 .clk = {
68 .name = "mout_48m",
69 .id = -1,
70 },
71 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
73};
74
75static struct clksrc_clk clk_mout_mpll = {
76 .clk = {
77 .name = "mout_mpll",
78 .id = -1,
79 },
80 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
82};
83
84
85static struct clksrc_clk clk_mout_apll = {
86 .clk = {
87 .name = "mout_apll",
88 .id = -1,
89 },
90 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
92};
93
94static struct clksrc_clk clk_mout_epll = {
95 .clk = {
96 .name = "mout_epll",
97 .id = -1,
98 },
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
101};
102
103static struct clk *clk_src_mout_hpll_list[] = {
104 [0] = &s5p_clk_27m,
105};
106
107static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
110};
111
112static struct clksrc_clk clk_mout_hpll = {
113 .clk = {
114 .name = "mout_hpll",
115 .id = -1,
116 },
117 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
119};
120
121static struct clksrc_clk clk_div_apll = {
122 .clk = {
123 .name = "div_apll",
124 .id = -1,
125 .parent = &clk_mout_apll.clk,
126 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
128};
129
130static struct clksrc_clk clk_div_arm = {
131 .clk = {
132 .name = "div_arm",
133 .id = -1,
134 .parent = &clk_div_apll.clk,
135 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
137};
138
139static struct clksrc_clk clk_div_d0_bus = {
140 .clk = {
141 .name = "div_d0_bus",
142 .id = -1,
143 .parent = &clk_div_arm.clk,
144 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
146};
147
148static struct clksrc_clk clk_div_pclkd0 = {
149 .clk = {
150 .name = "div_pclkd0",
151 .id = -1,
152 .parent = &clk_div_d0_bus.clk,
153 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
155};
156
157static struct clksrc_clk clk_div_secss = {
158 .clk = {
159 .name = "div_secss",
160 .id = -1,
161 .parent = &clk_div_d0_bus.clk,
162 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
164};
165
166static struct clksrc_clk clk_div_apll2 = {
167 .clk = {
168 .name = "div_apll2",
169 .id = -1,
170 .parent = &clk_mout_apll.clk,
171 },
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
173};
174
175static struct clk *clk_src_mout_am_list[] = {
176 [0] = &clk_mout_mpll.clk,
177 [1] = &clk_div_apll2.clk,
178};
179
180struct clksrc_sources clk_src_mout_am = {
181 .sources = clk_src_mout_am_list,
182 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
183};
184
185static struct clksrc_clk clk_mout_am = {
186 .clk = {
187 .name = "mout_am",
188 .id = -1,
189 },
190 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
192};
193
194static struct clksrc_clk clk_div_d1_bus = {
195 .clk = {
196 .name = "div_d1_bus",
197 .id = -1,
198 .parent = &clk_mout_am.clk,
199 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
201};
202
203static struct clksrc_clk clk_div_mpll2 = {
204 .clk = {
205 .name = "div_mpll2",
206 .id = -1,
207 .parent = &clk_mout_am.clk,
208 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
210};
211
212static struct clksrc_clk clk_div_mpll = {
213 .clk = {
214 .name = "div_mpll",
215 .id = -1,
216 .parent = &clk_mout_am.clk,
217 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
219};
220
221static struct clk *clk_src_mout_onenand_list[] = {
222 [0] = &clk_div_d0_bus.clk,
223 [1] = &clk_div_d1_bus.clk,
224};
225
226struct clksrc_sources clk_src_mout_onenand = {
227 .sources = clk_src_mout_onenand_list,
228 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
229};
230
231static struct clksrc_clk clk_mout_onenand = {
232 .clk = {
233 .name = "mout_onenand",
234 .id = -1,
235 },
236 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
238};
239
240static struct clksrc_clk clk_div_onenand = {
241 .clk = {
242 .name = "div_onenand",
243 .id = -1,
244 .parent = &clk_mout_onenand.clk,
245 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
247};
248
249static struct clksrc_clk clk_div_pclkd1 = {
250 .clk = {
251 .name = "div_pclkd1",
252 .id = -1,
253 .parent = &clk_div_d1_bus.clk,
254 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
256};
257
258static struct clksrc_clk clk_div_cam = {
259 .clk = {
260 .name = "div_cam",
261 .id = -1,
262 .parent = &clk_div_mpll2.clk,
263 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
265};
266
267static struct clksrc_clk clk_div_hdmi = {
268 .clk = {
269 .name = "div_hdmi",
270 .id = -1,
271 .parent = &clk_mout_hpll.clk,
272 },
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
274};
275
276static int s5pc100_epll_enable(struct clk *clk, int enable)
277{
278 unsigned int ctrlbit = clk->ctrlbit;
279 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
280
281 if (enable)
282 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
283 else
284 __raw_writel(epll_con, S5P_EPLL_CON);
285
286 return 0;
287}
288
289static unsigned long s5pc100_epll_get_rate(struct clk *clk)
290{
291 return clk->rate;
292}
293
294static u32 epll_div[][4] = {
295 { 32750000, 131, 3, 4 },
296 { 32768000, 131, 3, 4 },
297 { 36000000, 72, 3, 3 },
298 { 45000000, 90, 3, 3 },
299 { 45158000, 90, 3, 3 },
300 { 45158400, 90, 3, 3 },
301 { 48000000, 96, 3, 3 },
302 { 49125000, 131, 4, 3 },
303 { 49152000, 131, 4, 3 },
304 { 60000000, 120, 3, 3 },
305 { 67737600, 226, 5, 3 },
306 { 67738000, 226, 5, 3 },
307 { 73800000, 246, 5, 3 },
308 { 73728000, 246, 5, 3 },
309 { 72000000, 144, 3, 3 },
310 { 84000000, 168, 3, 3 },
311 { 96000000, 96, 3, 2 },
312 { 144000000, 144, 3, 2 },
313 { 192000000, 96, 3, 1 }
314};
315
316static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
317{
318 unsigned int epll_con;
319 unsigned int i;
320
321 if (clk->rate == rate) /* Return if nothing changed */
322 return 0;
323
324 epll_con = __raw_readl(S5P_EPLL_CON);
325
326 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
327
328 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
329 if (epll_div[i][0] == rate) {
330 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
331 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
332 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
333 break;
334 }
335 }
336
337 if (i == ARRAY_SIZE(epll_div)) {
338 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
339 return -EINVAL;
340 }
341
342 __raw_writel(epll_con, S5P_EPLL_CON);
343
344 clk->rate = rate;
345
346 return 0;
347}
348
349static struct clk_ops s5pc100_epll_ops = {
350 .get_rate = s5pc100_epll_get_rate,
351 .set_rate = s5pc100_epll_set_rate,
352};
353
354static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
355{
356 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
357}
358
359static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
360{
361 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
362}
363
364static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
365{
366 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
367}
368
369static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
370{
371 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
372}
373
374static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
375{
376 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
377}
378
379static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
380{
381 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
382}
383
384static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
385{
386 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
387}
388
389static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
390{
391 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
392}
393
394static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
395{
396 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
397}
398
399static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
400{
401 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
402}
403
404static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
405{
406 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
407}
408
409/*
410 * The following clocks will be disabled during clock initialization. It is
411 * recommended to keep the following clocks disabled until the driver requests
412 * for enabling the clock.
413 */
414static struct clk init_clocks_disable[] = {
415 {
416 .name = "cssys",
417 .id = -1,
418 .parent = &clk_div_d0_bus.clk,
419 .enable = s5pc100_d0_0_ctrl,
420 .ctrlbit = (1 << 6),
421 }, {
422 .name = "secss",
423 .id = -1,
424 .parent = &clk_div_d0_bus.clk,
425 .enable = s5pc100_d0_0_ctrl,
426 .ctrlbit = (1 << 5),
427 }, {
428 .name = "g2d",
429 .id = -1,
430 .parent = &clk_div_d0_bus.clk,
431 .enable = s5pc100_d0_0_ctrl,
432 .ctrlbit = (1 << 4),
433 }, {
434 .name = "mdma",
435 .id = -1,
436 .parent = &clk_div_d0_bus.clk,
437 .enable = s5pc100_d0_0_ctrl,
438 .ctrlbit = (1 << 3),
439 }, {
440 .name = "cfcon",
441 .id = -1,
442 .parent = &clk_div_d0_bus.clk,
443 .enable = s5pc100_d0_0_ctrl,
444 .ctrlbit = (1 << 2),
445 }, {
446 .name = "nfcon",
447 .id = -1,
448 .parent = &clk_div_d0_bus.clk,
449 .enable = s5pc100_d0_1_ctrl,
450 .ctrlbit = (1 << 3),
451 }, {
452 .name = "onenandc",
453 .id = -1,
454 .parent = &clk_div_d0_bus.clk,
455 .enable = s5pc100_d0_1_ctrl,
456 .ctrlbit = (1 << 2),
457 }, {
458 .name = "sdm",
459 .id = -1,
460 .parent = &clk_div_d0_bus.clk,
461 .enable = s5pc100_d0_2_ctrl,
462 .ctrlbit = (1 << 2),
463 }, {
464 .name = "seckey",
465 .id = -1,
466 .parent = &clk_div_d0_bus.clk,
467 .enable = s5pc100_d0_2_ctrl,
468 .ctrlbit = (1 << 1),
469 }, {
470 .name = "hsmmc",
471 .id = 2,
472 .parent = &clk_div_d1_bus.clk,
473 .enable = s5pc100_d1_0_ctrl,
474 .ctrlbit = (1 << 7),
475 }, {
476 .name = "hsmmc",
477 .id = 1,
478 .parent = &clk_div_d1_bus.clk,
479 .enable = s5pc100_d1_0_ctrl,
480 .ctrlbit = (1 << 6),
481 }, {
482 .name = "hsmmc",
483 .id = 0,
484 .parent = &clk_div_d1_bus.clk,
485 .enable = s5pc100_d1_0_ctrl,
486 .ctrlbit = (1 << 5),
487 }, {
488 .name = "modemif",
489 .id = -1,
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_0_ctrl,
492 .ctrlbit = (1 << 4),
493 }, {
494 .name = "otg",
495 .id = -1,
496 .parent = &clk_div_d1_bus.clk,
497 .enable = s5pc100_d1_0_ctrl,
498 .ctrlbit = (1 << 3),
499 }, {
500 .name = "usbhost",
501 .id = -1,
502 .parent = &clk_div_d1_bus.clk,
503 .enable = s5pc100_d1_0_ctrl,
504 .ctrlbit = (1 << 2),
505 }, {
506 .name = "pdma",
507 .id = 1,
508 .parent = &clk_div_d1_bus.clk,
509 .enable = s5pc100_d1_0_ctrl,
510 .ctrlbit = (1 << 1),
511 }, {
512 .name = "pdma",
513 .id = 0,
514 .parent = &clk_div_d1_bus.clk,
515 .enable = s5pc100_d1_0_ctrl,
516 .ctrlbit = (1 << 0),
517 }, {
518 .name = "lcd",
519 .id = -1,
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_1_ctrl,
522 .ctrlbit = (1 << 0),
523 }, {
524 .name = "rotator",
525 .id = -1,
526 .parent = &clk_div_d1_bus.clk,
527 .enable = s5pc100_d1_1_ctrl,
528 .ctrlbit = (1 << 1),
529 }, {
530 .name = "fimc",
531 .id = 0,
532 .parent = &clk_div_d1_bus.clk,
533 .enable = s5pc100_d1_1_ctrl,
534 .ctrlbit = (1 << 2),
535 }, {
536 .name = "fimc",
537 .id = 1,
538 .parent = &clk_div_d1_bus.clk,
539 .enable = s5pc100_d1_1_ctrl,
540 .ctrlbit = (1 << 3),
541 }, {
542 .name = "fimc",
543 .id = 2,
544 .parent = &clk_div_d1_bus.clk,
545 .enable = s5pc100_d1_1_ctrl,
546 .ctrlbit = (1 << 4),
547 }, {
548 .name = "jpeg",
549 .id = -1,
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_1_ctrl,
552 .ctrlbit = (1 << 5),
553 }, {
554 .name = "mipi-dsim",
555 .id = -1,
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_1_ctrl,
558 .ctrlbit = (1 << 6),
559 }, {
560 .name = "mipi-csis",
561 .id = -1,
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_1_ctrl,
564 .ctrlbit = (1 << 7),
565 }, {
566 .name = "g3d",
567 .id = 0,
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_0_ctrl,
570 .ctrlbit = (1 << 8),
571 }, {
572 .name = "tv",
573 .id = -1,
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_2_ctrl,
576 .ctrlbit = (1 << 0),
577 }, {
578 .name = "vp",
579 .id = -1,
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_2_ctrl,
582 .ctrlbit = (1 << 1),
583 }, {
584 .name = "mixer",
585 .id = -1,
586 .parent = &clk_div_d1_bus.clk,
587 .enable = s5pc100_d1_2_ctrl,
588 .ctrlbit = (1 << 2),
589 }, {
590 .name = "hdmi",
591 .id = -1,
592 .parent = &clk_div_d1_bus.clk,
593 .enable = s5pc100_d1_2_ctrl,
594 .ctrlbit = (1 << 3),
595 }, {
596 .name = "mfc",
597 .id = -1,
598 .parent = &clk_div_d1_bus.clk,
599 .enable = s5pc100_d1_2_ctrl,
600 .ctrlbit = (1 << 4),
601 }, {
602 .name = "apc",
603 .id = -1,
604 .parent = &clk_div_d1_bus.clk,
605 .enable = s5pc100_d1_3_ctrl,
606 .ctrlbit = (1 << 2),
607 }, {
608 .name = "iec",
609 .id = -1,
610 .parent = &clk_div_d1_bus.clk,
611 .enable = s5pc100_d1_3_ctrl,
612 .ctrlbit = (1 << 3),
613 }, {
614 .name = "systimer",
615 .id = -1,
616 .parent = &clk_div_d1_bus.clk,
617 .enable = s5pc100_d1_3_ctrl,
618 .ctrlbit = (1 << 7),
619 }, {
620 .name = "watchdog",
621 .id = -1,
622 .parent = &clk_div_d1_bus.clk,
623 .enable = s5pc100_d1_3_ctrl,
624 .ctrlbit = (1 << 8),
625 }, {
626 .name = "rtc",
627 .id = -1,
628 .parent = &clk_div_d1_bus.clk,
629 .enable = s5pc100_d1_3_ctrl,
630 .ctrlbit = (1 << 9),
631 }, {
632 .name = "i2c",
633 .id = 0,
634 .parent = &clk_div_d1_bus.clk,
635 .enable = s5pc100_d1_4_ctrl,
636 .ctrlbit = (1 << 4),
637 }, {
638 .name = "i2c",
639 .id = 1,
640 .parent = &clk_div_d1_bus.clk,
641 .enable = s5pc100_d1_4_ctrl,
642 .ctrlbit = (1 << 5),
643 }, {
644 .name = "spi",
645 .id = 0,
646 .parent = &clk_div_d1_bus.clk,
647 .enable = s5pc100_d1_4_ctrl,
648 .ctrlbit = (1 << 6),
649 }, {
650 .name = "spi",
651 .id = 1,
652 .parent = &clk_div_d1_bus.clk,
653 .enable = s5pc100_d1_4_ctrl,
654 .ctrlbit = (1 << 7),
655 }, {
656 .name = "spi",
657 .id = 2,
658 .parent = &clk_div_d1_bus.clk,
659 .enable = s5pc100_d1_4_ctrl,
660 .ctrlbit = (1 << 8),
661 }, {
662 .name = "irda",
663 .id = -1,
664 .parent = &clk_div_d1_bus.clk,
665 .enable = s5pc100_d1_4_ctrl,
666 .ctrlbit = (1 << 9),
667 }, {
668 .name = "ccan",
669 .id = 0,
670 .parent = &clk_div_d1_bus.clk,
671 .enable = s5pc100_d1_4_ctrl,
672 .ctrlbit = (1 << 10),
673 }, {
674 .name = "ccan",
675 .id = 1,
676 .parent = &clk_div_d1_bus.clk,
677 .enable = s5pc100_d1_4_ctrl,
678 .ctrlbit = (1 << 11),
679 }, {
680 .name = "hsitx",
681 .id = -1,
682 .parent = &clk_div_d1_bus.clk,
683 .enable = s5pc100_d1_4_ctrl,
684 .ctrlbit = (1 << 12),
685 }, {
686 .name = "hsirx",
687 .id = -1,
688 .parent = &clk_div_d1_bus.clk,
689 .enable = s5pc100_d1_4_ctrl,
690 .ctrlbit = (1 << 13),
691 }, {
692 .name = "iis",
693 .id = 0,
694 .parent = &clk_div_d1_bus.clk,
695 .enable = s5pc100_d1_5_ctrl,
696 .ctrlbit = (1 << 0),
697 }, {
698 .name = "iis",
699 .id = 1,
700 .parent = &clk_div_d1_bus.clk,
701 .enable = s5pc100_d1_5_ctrl,
702 .ctrlbit = (1 << 1),
703 }, {
704 .name = "iis",
705 .id = 2,
706 .parent = &clk_div_d1_bus.clk,
707 .enable = s5pc100_d1_5_ctrl,
708 .ctrlbit = (1 << 2),
709 }, {
710 .name = "ac97",
711 .id = -1,
712 .parent = &clk_div_d1_bus.clk,
713 .enable = s5pc100_d1_5_ctrl,
714 .ctrlbit = (1 << 3),
715 }, {
716 .name = "pcm",
717 .id = 0,
718 .parent = &clk_div_d1_bus.clk,
719 .enable = s5pc100_d1_5_ctrl,
720 .ctrlbit = (1 << 4),
721 }, {
722 .name = "pcm",
723 .id = 1,
724 .parent = &clk_div_d1_bus.clk,
725 .enable = s5pc100_d1_5_ctrl,
726 .ctrlbit = (1 << 5),
727 }, {
728 .name = "spdif",
729 .id = -1,
730 .parent = &clk_div_d1_bus.clk,
731 .enable = s5pc100_d1_5_ctrl,
732 .ctrlbit = (1 << 6),
733 }, {
734 .name = "adc",
735 .id = -1,
736 .parent = &clk_div_d1_bus.clk,
737 .enable = s5pc100_d1_5_ctrl,
738 .ctrlbit = (1 << 7),
739 }, {
740 .name = "keyif",
741 .id = -1,
742 .parent = &clk_div_d1_bus.clk,
743 .enable = s5pc100_d1_5_ctrl,
744 .ctrlbit = (1 << 8),
745 }, {
746 .name = "spi_48m",
747 .id = 0,
748 .parent = &clk_mout_48m.clk,
749 .enable = s5pc100_sclk0_ctrl,
750 .ctrlbit = (1 << 7),
751 }, {
752 .name = "spi_48m",
753 .id = 1,
754 .parent = &clk_mout_48m.clk,
755 .enable = s5pc100_sclk0_ctrl,
756 .ctrlbit = (1 << 8),
757 }, {
758 .name = "spi_48m",
759 .id = 2,
760 .parent = &clk_mout_48m.clk,
761 .enable = s5pc100_sclk0_ctrl,
762 .ctrlbit = (1 << 9),
763 }, {
764 .name = "mmc_48m",
765 .id = 0,
766 .parent = &clk_mout_48m.clk,
767 .enable = s5pc100_sclk0_ctrl,
768 .ctrlbit = (1 << 15),
769 }, {
770 .name = "mmc_48m",
771 .id = 1,
772 .parent = &clk_mout_48m.clk,
773 .enable = s5pc100_sclk0_ctrl,
774 .ctrlbit = (1 << 16),
775 }, {
776 .name = "mmc_48m",
777 .id = 2,
778 .parent = &clk_mout_48m.clk,
779 .enable = s5pc100_sclk0_ctrl,
780 .ctrlbit = (1 << 17),
781 },
782};
783
784static struct clk clk_vclk54m = {
785 .name = "vclk_54m",
786 .id = -1,
787 .rate = 54000000,
788};
789
790static struct clk clk_i2scdclk0 = {
791 .name = "i2s_cdclk0",
792 .id = -1,
793};
794
795static struct clk clk_i2scdclk1 = {
796 .name = "i2s_cdclk1",
797 .id = -1,
798};
799
800static struct clk clk_i2scdclk2 = {
801 .name = "i2s_cdclk2",
802 .id = -1,
803};
804
805static struct clk clk_pcmcdclk0 = {
806 .name = "pcm_cdclk0",
807 .id = -1,
808};
809
810static struct clk clk_pcmcdclk1 = {
811 .name = "pcm_cdclk1",
812 .id = -1,
813};
814
815static struct clk *clk_src_group1_list[] = {
816 [0] = &clk_mout_epll.clk,
817 [1] = &clk_div_mpll2.clk,
818 [2] = &clk_fin_epll,
819 [3] = &clk_mout_hpll.clk,
820};
821
822struct clksrc_sources clk_src_group1 = {
823 .sources = clk_src_group1_list,
824 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
825};
826
827static struct clk *clk_src_group2_list[] = {
828 [0] = &clk_mout_epll.clk,
829 [1] = &clk_div_mpll.clk,
830};
831
832struct clksrc_sources clk_src_group2 = {
833 .sources = clk_src_group2_list,
834 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
835};
836
837static struct clk *clk_src_group3_list[] = {
838 [0] = &clk_mout_epll.clk,
839 [1] = &clk_div_mpll.clk,
840 [2] = &clk_fin_epll,
841 [3] = &clk_i2scdclk0,
842 [4] = &clk_pcmcdclk0,
843 [5] = &clk_mout_hpll.clk,
844};
845
846struct clksrc_sources clk_src_group3 = {
847 .sources = clk_src_group3_list,
848 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
849};
850
851static struct clk *clk_src_group4_list[] = {
852 [0] = &clk_mout_epll.clk,
853 [1] = &clk_div_mpll.clk,
854 [2] = &clk_fin_epll,
855 [3] = &clk_i2scdclk1,
856 [4] = &clk_pcmcdclk1,
857 [5] = &clk_mout_hpll.clk,
858};
859
860struct clksrc_sources clk_src_group4 = {
861 .sources = clk_src_group4_list,
862 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
863};
864
865static struct clk *clk_src_group5_list[] = {
866 [0] = &clk_mout_epll.clk,
867 [1] = &clk_div_mpll.clk,
868 [2] = &clk_fin_epll,
869 [3] = &clk_i2scdclk2,
870 [4] = &clk_mout_hpll.clk,
871};
872
873struct clksrc_sources clk_src_group5 = {
874 .sources = clk_src_group5_list,
875 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
876};
877
878static struct clk *clk_src_group6_list[] = {
879 [0] = &s5p_clk_27m,
880 [1] = &clk_vclk54m,
881 [2] = &clk_div_hdmi.clk,
882};
883
884struct clksrc_sources clk_src_group6 = {
885 .sources = clk_src_group6_list,
886 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
887};
888
889static struct clk *clk_src_group7_list[] = {
890 [0] = &clk_mout_epll.clk,
891 [1] = &clk_div_mpll.clk,
892 [2] = &clk_mout_hpll.clk,
893 [3] = &clk_vclk54m,
894};
895
896struct clksrc_sources clk_src_group7 = {
897 .sources = clk_src_group7_list,
898 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
899};
900
901static struct clk *clk_src_mmc0_list[] = {
902 [0] = &clk_mout_epll.clk,
903 [1] = &clk_div_mpll.clk,
904 [2] = &clk_fin_epll,
905};
906
907struct clksrc_sources clk_src_mmc0 = {
908 .sources = clk_src_mmc0_list,
909 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
910};
911
912static struct clk *clk_src_mmc12_list[] = {
913 [0] = &clk_mout_epll.clk,
914 [1] = &clk_div_mpll.clk,
915 [2] = &clk_fin_epll,
916 [3] = &clk_mout_hpll.clk,
917};
918
919struct clksrc_sources clk_src_mmc12 = {
920 .sources = clk_src_mmc12_list,
921 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
922};
923
924static struct clk *clk_src_irda_usb_list[] = {
925 [0] = &clk_mout_epll.clk,
926 [1] = &clk_div_mpll.clk,
927 [2] = &clk_fin_epll,
928 [3] = &clk_mout_hpll.clk,
929};
930
931struct clksrc_sources clk_src_irda_usb = {
932 .sources = clk_src_irda_usb_list,
933 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
934};
935
936static struct clk *clk_src_pwi_list[] = {
937 [0] = &clk_fin_epll,
938 [1] = &clk_mout_epll.clk,
939 [2] = &clk_div_mpll.clk,
940};
941
942struct clksrc_sources clk_src_pwi = {
943 .sources = clk_src_pwi_list,
944 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
945};
946
947static struct clksrc_clk clksrcs[] = {
948 {
949 .clk = {
950 .name = "sclk_spi",
951 .id = 0,
952 .ctrlbit = (1 << 4),
953 .enable = s5pc100_sclk0_ctrl,
954
955 },
956 .sources = &clk_src_group1,
957 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
958 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
959 }, {
960 .clk = {
961 .name = "sclk_spi",
962 .id = 1,
963 .ctrlbit = (1 << 5),
964 .enable = s5pc100_sclk0_ctrl,
965
966 },
967 .sources = &clk_src_group1,
968 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
969 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
970 }, {
971 .clk = {
972 .name = "sclk_spi",
973 .id = 2,
974 .ctrlbit = (1 << 6),
975 .enable = s5pc100_sclk0_ctrl,
976
977 },
978 .sources = &clk_src_group1,
979 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
980 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
981 }, {
982 .clk = {
983 .name = "uclk1",
984 .id = -1,
985 .ctrlbit = (1 << 3),
986 .enable = s5pc100_sclk0_ctrl,
987
988 },
989 .sources = &clk_src_group2,
990 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
991 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
992 }, {
993 .clk = {
994 .name = "sclk_mixer",
995 .id = -1,
996 .ctrlbit = (1 << 6),
997 .enable = s5pc100_sclk0_ctrl,
998
999 },
1000 .sources = &clk_src_group6,
1001 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
1002 }, {
1003 .clk = {
1004 .name = "sclk_audio",
1005 .id = 0,
1006 .ctrlbit = (1 << 8),
1007 .enable = s5pc100_sclk1_ctrl,
1008
1009 },
1010 .sources = &clk_src_group3,
1011 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
1012 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1013 }, {
1014 .clk = {
1015 .name = "sclk_audio",
1016 .id = 1,
1017 .ctrlbit = (1 << 9),
1018 .enable = s5pc100_sclk1_ctrl,
1019
1020 },
1021 .sources = &clk_src_group4,
1022 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
1023 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
1024 }, {
1025 .clk = {
1026 .name = "sclk_audio",
1027 .id = 2,
1028 .ctrlbit = (1 << 10),
1029 .enable = s5pc100_sclk1_ctrl,
1030
1031 },
1032 .sources = &clk_src_group5,
1033 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
1034 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
1035 }, {
1036 .clk = {
1037 .name = "sclk_lcd",
1038 .id = -1,
1039 .ctrlbit = (1 << 0),
1040 .enable = s5pc100_sclk1_ctrl,
1041
1042 },
1043 .sources = &clk_src_group7,
1044 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
1045 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
1046 }, {
1047 .clk = {
1048 .name = "sclk_fimc",
1049 .id = 0,
1050 .ctrlbit = (1 << 1),
1051 .enable = s5pc100_sclk1_ctrl,
1052
1053 },
1054 .sources = &clk_src_group7,
1055 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1056 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1057 }, {
1058 .clk = {
1059 .name = "sclk_fimc",
1060 .id = 1,
1061 .ctrlbit = (1 << 2),
1062 .enable = s5pc100_sclk1_ctrl,
1063
1064 },
1065 .sources = &clk_src_group7,
1066 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1067 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1068 }, {
1069 .clk = {
1070 .name = "sclk_fimc",
1071 .id = 2,
1072 .ctrlbit = (1 << 3),
1073 .enable = s5pc100_sclk1_ctrl,
1074
1075 },
1076 .sources = &clk_src_group7,
1077 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1078 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1079 }, {
1080 .clk = {
1081 .name = "mmc_bus",
1082 .id = 0,
1083 .ctrlbit = (1 << 12),
1084 .enable = s5pc100_sclk1_ctrl,
1085
1086 },
1087 .sources = &clk_src_mmc0,
1088 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1089 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1090 }, {
1091 .clk = {
1092 .name = "mmc_bus",
1093 .id = 1,
1094 .ctrlbit = (1 << 13),
1095 .enable = s5pc100_sclk1_ctrl,
1096
1097 },
1098 .sources = &clk_src_mmc12,
1099 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1100 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1101 }, {
1102 .clk = {
1103 .name = "mmc_bus",
1104 .id = 2,
1105 .ctrlbit = (1 << 14),
1106 .enable = s5pc100_sclk1_ctrl,
1107
1108 },
1109 .sources = &clk_src_mmc12,
1110 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1111 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1112 }, {
1113 .clk = {
1114 .name = "sclk_irda",
1115 .id = 2,
1116 .ctrlbit = (1 << 10),
1117 .enable = s5pc100_sclk0_ctrl,
1118
1119 },
1120 .sources = &clk_src_irda_usb,
1121 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1122 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1123 }, {
1124 .clk = {
1125 .name = "sclk_irda",
1126 .id = -1,
1127 .ctrlbit = (1 << 10),
1128 .enable = s5pc100_sclk0_ctrl,
1129
1130 },
1131 .sources = &clk_src_mmc12,
1132 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1133 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1134 }, {
1135 .clk = {
1136 .name = "sclk_pwi",
1137 .id = -1,
1138 .ctrlbit = (1 << 1),
1139 .enable = s5pc100_sclk0_ctrl,
1140
1141 },
1142 .sources = &clk_src_pwi,
1143 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1144 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1145 }, {
1146 .clk = {
1147 .name = "sclk_uhost",
1148 .id = -1,
1149 .ctrlbit = (1 << 11),
1150 .enable = s5pc100_sclk0_ctrl,
1151
1152 },
1153 .sources = &clk_src_irda_usb,
1154 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1155 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1156 },
1157};
1158
1159/* Clock initialisation code */
1160static struct clksrc_clk *sysclks[] = {
1161 &clk_mout_apll,
1162 &clk_mout_epll,
1163 &clk_mout_mpll,
1164 &clk_mout_hpll,
1165 &clk_mout_href,
1166 &clk_mout_48m,
1167 &clk_div_apll,
1168 &clk_div_arm,
1169 &clk_div_d0_bus,
1170 &clk_div_pclkd0,
1171 &clk_div_secss,
1172 &clk_div_apll2,
1173 &clk_mout_am,
1174 &clk_div_d1_bus,
1175 &clk_div_mpll2,
1176 &clk_div_mpll,
1177 &clk_mout_onenand,
1178 &clk_div_onenand,
1179 &clk_div_pclkd1,
1180 &clk_div_cam,
1181 &clk_div_hdmi,
1182};
1183
1184void __init_or_cpufreq s5pc100_setup_clocks(void)
1185{
1186 unsigned long xtal;
1187 unsigned long arm;
1188 unsigned long hclkd0;
1189 unsigned long hclkd1;
1190 unsigned long pclkd0;
1191 unsigned long pclkd1;
1192 unsigned long apll;
1193 unsigned long mpll;
1194 unsigned long epll;
1195 unsigned long hpll;
1196 unsigned int ptr;
1197
1198 /* Set S5PC100 functions for clk_fout_epll */
1199 clk_fout_epll.enable = s5pc100_epll_enable;
1200 clk_fout_epll.ops = &s5pc100_epll_ops;
1201
1202 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1203
1204 xtal = clk_get_rate(&clk_xtal);
1205
1206 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1207
1208 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1209 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1210 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1211 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1212
1213 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1214 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1215
1216 clk_fout_apll.rate = apll;
1217 clk_fout_mpll.rate = mpll;
1218 clk_fout_epll.rate = epll;
1219 clk_mout_hpll.clk.rate = hpll;
1220
1221 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1222 s3c_set_clksrc(&clksrcs[ptr], true);
1223
1224 arm = clk_get_rate(&clk_div_arm.clk);
1225 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1226 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1227 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1228 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1229
1230 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1231 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1232
1233 clk_f.rate = arm;
1234 clk_h.rate = hclkd1;
1235 clk_p.rate = pclkd1;
1236}
1237
1238/*
1239 * The following clocks will be enabled during clock initialization.
1240 */
1241static struct clk init_clocks[] = {
1242 {
1243 .name = "tzic",
1244 .id = -1,
1245 .parent = &clk_div_d0_bus.clk,
1246 .enable = s5pc100_d0_0_ctrl,
1247 .ctrlbit = (1 << 1),
1248 }, {
1249 .name = "intc",
1250 .id = -1,
1251 .parent = &clk_div_d0_bus.clk,
1252 .enable = s5pc100_d0_0_ctrl,
1253 .ctrlbit = (1 << 0),
1254 }, {
1255 .name = "ebi",
1256 .id = -1,
1257 .parent = &clk_div_d0_bus.clk,
1258 .enable = s5pc100_d0_1_ctrl,
1259 .ctrlbit = (1 << 5),
1260 }, {
1261 .name = "intmem",
1262 .id = -1,
1263 .parent = &clk_div_d0_bus.clk,
1264 .enable = s5pc100_d0_1_ctrl,
1265 .ctrlbit = (1 << 4),
1266 }, {
1267 .name = "sromc",
1268 .id = -1,
1269 .parent = &clk_div_d0_bus.clk,
1270 .enable = s5pc100_d0_1_ctrl,
1271 .ctrlbit = (1 << 1),
1272 }, {
1273 .name = "dmc",
1274 .id = -1,
1275 .parent = &clk_div_d0_bus.clk,
1276 .enable = s5pc100_d0_1_ctrl,
1277 .ctrlbit = (1 << 0),
1278 }, {
1279 .name = "chipid",
1280 .id = -1,
1281 .parent = &clk_div_d0_bus.clk,
1282 .enable = s5pc100_d0_1_ctrl,
1283 .ctrlbit = (1 << 0),
1284 }, {
1285 .name = "gpio",
1286 .id = -1,
1287 .parent = &clk_div_d1_bus.clk,
1288 .enable = s5pc100_d1_3_ctrl,
1289 .ctrlbit = (1 << 1),
1290 }, {
1291 .name = "uart",
1292 .id = 0,
1293 .parent = &clk_div_d1_bus.clk,
1294 .enable = s5pc100_d1_4_ctrl,
1295 .ctrlbit = (1 << 0),
1296 }, {
1297 .name = "uart",
1298 .id = 1,
1299 .parent = &clk_div_d1_bus.clk,
1300 .enable = s5pc100_d1_4_ctrl,
1301 .ctrlbit = (1 << 1),
1302 }, {
1303 .name = "uart",
1304 .id = 2,
1305 .parent = &clk_div_d1_bus.clk,
1306 .enable = s5pc100_d1_4_ctrl,
1307 .ctrlbit = (1 << 2),
1308 }, {
1309 .name = "uart",
1310 .id = 3,
1311 .parent = &clk_div_d1_bus.clk,
1312 .enable = s5pc100_d1_4_ctrl,
1313 .ctrlbit = (1 << 3),
1314 }, {
1315 .name = "timers",
1316 .id = -1,
1317 .parent = &clk_div_d1_bus.clk,
1318 .enable = s5pc100_d1_3_ctrl,
1319 .ctrlbit = (1 << 6),
1320 },
1321};
1322
1323static struct clk *clks[] __initdata = {
1324 &clk_ext,
1325 &clk_i2scdclk0,
1326 &clk_i2scdclk1,
1327 &clk_i2scdclk2,
1328 &clk_pcmcdclk0,
1329 &clk_pcmcdclk1,
1330};
1331
1332void __init s5pc100_register_clocks(void)
1333{
1334 struct clk *clkp;
1335 int ret;
1336 int ptr;
1337
1338 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1339
1340 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1341 s3c_register_clksrc(sysclks[ptr], 1);
1342
1343 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1344 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1345
1346 clkp = init_clocks_disable;
1347 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1348
1349 ret = s3c24xx_register_clock(clkp);
1350 if (ret < 0) {
1351 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1352 clkp->name, ret);
1353 }
1354 (clkp->enable)(clkp, 0);
1355 }
1356
1357 s3c_pwmclk_init();
1358}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 14:34:19 -0500