37 files changed, 4328 insertions, 0 deletions

diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
new file mode 100644
index 000000000000..fbcae9352022
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -0,0 +1,57 @@
+# arch/arm/mach-s5p64x0/Kconfig
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+if ARCH_S5P64X0
+
+config CPU_S5P6440
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6440 CPU support
+
+config CPU_S5P6450
+        bool
+        select PLAT_S5P
+        select S3C_PL330_DMA
+        help
+          Enable S5P6450 CPU support
+
+config S5P64X0_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+
+# machine support
+
+config MACH_SMDK6440
+        bool "SMDK6440"
+        select CPU_S5P6440
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6440
+
+config MACH_SMDK6450
+        bool "SMDK6450"
+        select CPU_S5P6450
+        select S3C_DEV_I2C1
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C64XX_DEV_SPI
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDK6450
+
+endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
new file mode 100644
index 000000000000..2655829e6bf8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -0,0 +1,30 @@
+# arch/arm/mach-s5p64x0/Makefile
+#
+# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# Core support for S5P64X0 system
+
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
+obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o
+obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o gpio.o
+obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
+obj-$(CONFIG_MACH_SMDK6450)     += mach-smdk6450.o
+
+# device support
+
+obj-y                           += dev-audio.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+
+obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
new file mode 100644
index 000000000000..ff90aa13bd67
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y   := 0x20008000
+params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
new file mode 100644
index 000000000000..f93dcd8b4d6a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -0,0 +1,626 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6440 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+
+static u32 epll_div[][5] = {
+        { 36000000,     0,      48, 1, 4 },
+        { 48000000,     0,      32, 1, 3 },
+        { 60000000,     0,      40, 1, 3 },
+        { 72000000,     0,      48, 1, 3 },
+        { 84000000,     0,      28, 1, 2 },
+        { 96000000,     0,      32, 1, 2 },
+        { 32768000,     45264,  43, 1, 4 },
+        { 45158000,     6903,   30, 1, 3 },
+        { 49152000,     50332,  32, 1, 3 },
+        { 67738000,     10398,  45, 1, 3 },
+        { 73728000,     9961,   49, 1, 3 }
+};
+
+static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6440_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6440_epll_set_rate,
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+                .parent         = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_mem_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "post",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 5)
+        }, {
+                .name           = "2d",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20)
+        }, {
+                .name           = "irom",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "hclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "tsi",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "pcm",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "gps",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "i2s_v40",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "dsim",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "etm",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }, {
+                .name           = "pclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 31),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "mmc_48m",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        },
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk clk_iis_cd_v40 = {
+        .name           = "iis_cdclk_v40",
+        .id             = -1,
+};
+
+static struct clk clk_pcm_cd = {
+        .name           = "pcm_cdclk",
+        .id             = -1,
+};
+
+static struct clk *clkset_group1_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+};
+
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_audio_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio = {
+        .sources        = clkset_audio_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "mmc_bus",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_post",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimgvg",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio2",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_audio,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+};
+
+void __init_or_cpufreq s5p6440_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned int ptr;
+
+        /* Set S5P6440 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6440_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+
+        printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+void __init s5p6440_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
new file mode 100644
index 000000000000..f9afb05b217c
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -0,0 +1,655 @@
+/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P6450 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/s5p64x0-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6450.h>
+
+static struct clksrc_clk clk_mout_dpll = {
+        .clk    = {
+                .name           = "mout_dpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_dpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
+};
+
+static u32 epll_div[][5] = {
+        { 133000000,    27307,  55, 2, 2 },
+        { 100000000,    43691,  41, 2, 2 },
+        { 480000000,    0,      80, 2, 0 },
+};
+
+static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        if (clk->rate == rate)  /* Return if nothing changed */
+                return 0;
+
+        epll_con = __raw_readl(S5P64X0_EPLL_CON);
+        epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
+
+        epll_con_k &= ~(PLL90XX_KDIV_MASK);
+        epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                 if (epll_div[i][0] == rate) {
+                        epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
+                        epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
+                                    (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
+                                    (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P64X0_EPLL_CON);
+        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5p6450_epll_ops = {
+        .get_rate = s5p64x0_epll_get_rate,
+        .set_rate = s5p6450_epll_set_rate,
+};
+
+static struct clksrc_clk clk_dout_epll = {
+        .clk    = {
+                .name           = "dout_epll",
+                .id             = -1,
+                .parent         = &clk_mout_epll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
+};
+
+static struct clksrc_clk clk_mout_hclk_sel = {
+        .clk    = {
+                .name           = "mout_hclk_sel",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
+};
+
+static struct clk *clkset_hclk_list[] = {
+        &clk_mout_hclk_sel.clk,
+        &clk_armclk.clk,
+};
+
+static struct clksrc_sources clkset_hclk = {
+        .sources        = clkset_hclk_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
+};
+
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name           = "clk_hclk",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name           = "clk_pclk",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+        },
+        .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_dout_pwm_ratio0 = {
+        .clk    = {
+                .name           = "clk_dout_pwm_ratio0",
+                .id             = -1,
+                .parent         = &clk_mout_hclk_sel.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_to_wdt_pwm = {
+        .clk    = {
+                .name           = "clk_pclk_to_wdt_pwm",
+                .id             = -1,
+                .parent         = &clk_dout_pwm_ratio0.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
+};
+
+static struct clksrc_clk clk_hclk_low = {
+        .clk    = {
+                .name           = "clk_hclk_low",
+                .id             = -1,
+        },
+        .sources        = &clkset_hclk_low,
+        .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name           = "clk_pclk_low",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
+};
+
+/*
+ * The following clocks will be disabled during clock initialization. It is
+ * recommended to keep the following clocks disabled until the driver requests
+ * for enabling the clock.
+ */
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "usbhost",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "usbotg",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5p64x0_hclk1_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "iis",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }
+};
+
+/*
+ * The following clocks will be enabled during clock initialization.
+ */
+static struct clk init_clocks[] = {
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_pclk_to_wdt_pwm.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p64x0_pclk_ctrl,
+                .ctrlbit        = (1 << 18),
+        },
+};
+
+static struct clk *clkset_uart_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_mali_list[] = {
+        &clk_mout_epll.clk,
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_mali = {
+        .sources        = clkset_mali_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mali_list),
+};
+
+static struct clk *clkset_group2_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+};
+
+static struct clksrc_sources clkset_group2 = {
+        .sources        = clkset_group2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group2_list),
+};
+
+static struct clk *clkset_dispcon_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &clk_mout_dpll.clk,
+};
+
+static struct clksrc_sources clkset_dispcon = {
+        .sources        = clkset_dispcon_list,
+        .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
+};
+
+static struct clk *clkset_hsmmc44_list[] = {
+        &clk_dout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_ext_xtal_mux,
+        &s5p_clk_27m,
+        &clk_48m,
+};
+
+static struct clksrc_sources clkset_hsmmc44 = {
+        .sources        = clkset_hsmmc44_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
+};
+
+static struct clk *clkset_sclk_audio0_list[] = {
+        [0] = &clk_dout_epll.clk,
+        [1] = &clk_dout_mpll.clk,
+        [2] = &clk_ext_xtal_mux,
+        [3] = NULL,
+        [4] = NULL,
+};
+
+static struct clksrc_sources clkset_sclk_audio0 = {
+        .sources        = clkset_sclk_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk clk_sclk_audio0 = {
+        .clk            = {
+                .name           = "audio-bus",
+                .id             = -1,
+                .enable         = s5p64x0_sclk_ctrl,
+                .ctrlbit        = (1 << 8),
+                .parent         = &clk_dout_epll.clk,
+        },
+        .sources        = &clkset_sclk_audio0,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 24),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 25),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mmc",
+                        .id             = 2,
+                        .ctrlbit        = (1 << 26),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "uclk1",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 5),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_uart,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .ctrlbit        = (1 << 20),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .ctrlbit        = (1 << 21),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "aclk_mali",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_2d",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 12),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_mali,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_usi",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 7),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_camif",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 6),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_group2,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p64x0_sclk1_ctrl,
+                },
+                .sources = &clkset_dispcon,
+                .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_hsmmc44",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 30),
+                        .enable         = s5p64x0_sclk_ctrl,
+                },
+                .sources = &clkset_hsmmc44,
+                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
+                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
+        },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_dout_epll,
+        &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_mout_hclk_sel,
+        &clk_dout_pwm_ratio0,
+        &clk_pclk_to_wdt_pwm,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
+        &clk_sclk_audio0,
+};
+
+void __init_or_cpufreq s5p6450_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+
+        unsigned long xtal;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long hclk_low;
+        unsigned long pclk;
+        unsigned long pclk_low;
+
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long epll;
+        unsigned long dpll;
+        unsigned int ptr;
+
+        /* Set S5P6450 functions for clk_fout_epll */
+
+        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.ops = &s5p6450_epll_ops;
+
+        clk_48m.enable = s5p64x0_clk48m_ctrl;
+
+        xtal_clk = clk_get(NULL, "ext_xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
+        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
+        epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
+                                __raw_readl(S5P64X0_EPLL_CON_K));
+        dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
+                                __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
+
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_dpll.rate = dpll;
+
+        printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
+                        " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
+                        print_mhz(apll), print_mhz(mpll), print_mhz(epll),
+                        print_mhz(dpll));
+
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
+
+        printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
+                        " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
+                        print_mhz(hclk), print_mhz(hclk_low),
+                        print_mhz(pclk), print_mhz(pclk_low));
+
+        clk_f.rate = fclk;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+void __init s5p6450_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
new file mode 100644
index 000000000000..523ba8039ac2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -0,0 +1,253 @@
+/* linux/arch/arm/mach-s5p64x0/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+
+struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_apll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_mpll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
+};
+
+struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .sources        = &clk_src_epll,
+        .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
+};
+
+enum perf_level {
+        L0 = 532*1000,
+        L1 = 266*1000,
+        L2 = 133*1000,
+};
+
+static const u32 clock_table[][3] = {
+        /*{ARM_CLK, DIVarm, DIVhclk}*/
+        {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+        {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
+};
+
+int s5p64x0_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P64X0_EPLL_CON);
+
+        return 0;
+}
+
+unsigned long s5p64x0_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv;
+
+        /* divisor mask starts at bit0, so no need to shift */
+        clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
+
+        return rate / (clkdiv + 1);
+}
+
+unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 iter;
+
+        for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (rate > clock_table[iter][0])
+                        return clock_table[iter-1][0];
+        }
+
+        return clock_table[ARRAY_SIZE(clock_table) - 1][0];
+}
+
+int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 round_tmp;
+        u32 iter;
+        u32 clk_div0_tmp;
+        u32 cur_rate = clk->ops->get_rate(clk);
+        unsigned long flags;
+
+        round_tmp = clk->ops->round_rate(clk, rate);
+        if (round_tmp == cur_rate)
+                return 0;
+
+
+        for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
+                if (round_tmp == clock_table[iter][0])
+                        break;
+        }
+
+        if (iter >= ARRAY_SIZE(clock_table))
+                iter = ARRAY_SIZE(clock_table) - 1;
+
+        local_irq_save(flags);
+        if (cur_rate > round_tmp) {
+                /* Frequency Down */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+
+        } else {
+                /* Frequency Up */
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
+                                ~(S5P64X0_CLKDIV0_HCLK_MASK);
+                clk_div0_tmp |= clock_table[iter][2];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+
+                clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
+                clk_div0_tmp |= clock_table[iter][1];
+                __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
+        }
+        local_irq_restore(flags);
+
+        clk->rate = clock_table[iter][0];
+
+        return 0;
+}
+
+struct clk_ops s5p64x0_clkarm_ops = {
+        .get_rate       = s5p64x0_armclk_get_rate,
+        .set_rate       = s5p64x0_armclk_set_rate,
+        .round_rate     = s5p64x0_armclk_round_rate,
+};
+
+struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .id             = 1,
+                .parent         = &clk_mout_apll.clk,
+                .ops            = &s5p64x0_clkarm_ops,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
+};
+
+struct clksrc_clk clk_dout_mpll = {
+        .clk    = {
+                .name           = "dout_mpll",
+                .id             = -1,
+                .parent         = &clk_mout_mpll.clk,
+        },
+        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
+};
+
+struct clk *clkset_hclk_low_list[] = {
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+struct clksrc_sources clkset_hclk_low = {
+        .sources        = clkset_hclk_low_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclk_low_list),
+};
+
+int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
+}
+
+int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
+}
+
+int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
+}
+
+int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
+}
+
+int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
+}
+
+int s5p64x0_mem_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
+}
+
+int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+
+        val = __raw_readl(S5P64X0_OTHERS);
+        if (enable)
+                val |= S5P64X0_OTHERS_USB_SIG_MASK;
+        else
+                val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
+
+        __raw_writel(val, S5P64X0_OTHERS);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
new file mode 100644
index 000000000000..b8d02eb4cf30
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -0,0 +1,209 @@
+/* linux/arch/arm/mach-s5p64x0/cpu.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/adc-core.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s5p64x0_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc s5p6450_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void s5p64x0_idle(void)
+{
+        unsigned long val;
+
+        if (!need_resched()) {
+                val = __raw_readl(S5P64X0_PWR_CFG);
+                val &= ~(0x3 << 5);
+                val |= (0x1 << 5);
+                __raw_writel(val, S5P64X0_PWR_CFG);
+
+                cpu_do_idle();
+        }
+        local_irq_enable();
+}
+
+/*
+ * s5p64x0_map_io
+ *
+ * register the standard CPU IO areas
+ */
+
+void __init s5p6440_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+void __init s5p6450_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+}
+
+/*
+ * s5p64x0_init_clocks
+ *
+ * register and setup the CPU clocks
+ */
+
+void __init s5p6440_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6440_register_clocks();
+        s5p6440_setup_clocks();
+}
+
+void __init s5p6450_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6450_register_clocks();
+        s5p6450_setup_clocks();
+}
+
+/*
+ * s5p64x0_init_irq
+ *
+ * register the CPU interrupts
+ */
+
+void __init s5p6440_init_irq(void)
+{
+        /* S5P6440 supports 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
+         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
+         */
+        vic[0] = 0xff800ae7;
+        vic[1] = 0xffbf23e5;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+void __init s5p6450_init_irq(void)
+{
+        /* S5P6450 supports only 2 VIC */
+        u32 vic[2];
+
+        /*
+         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
+         * VIC1 is missing IRQ VIC1[12, 14, 23]
+         */
+        vic[0] = 0xff9f1fff;
+        vic[1] = 0xff7fafff;
+
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+
+struct sysdev_class s5p64x0_sysclass = {
+        .name   = "s5p64x0-core",
+};
+
+static struct sys_device s5p64x0_sysdev = {
+        .cls    = &s5p64x0_sysclass,
+};
+
+static int __init s5p64x0_core_init(void)
+{
+        return sysdev_class_register(&s5p64x0_sysclass);
+}
+core_initcall(s5p64x0_core_init);
+
+int __init s5p64x0_init(void)
+{
+        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
+
+        /* set idle function */
+        pm_idle = s5p64x0_idle;
+
+        return sysdev_register(&s5p64x0_sysdev);
+}
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
new file mode 100644
index 000000000000..fa097bd68ca4
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -0,0 +1,164 @@
+/* linux/arch/arm/mach-s5p64x0/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5p6440_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_i2s_pdata = {
+        .cfg_gpio = s5p6440_cfg_i2s,
+};
+
+static struct s3c_audio_pdata s5p6450_i2s_pdata = {
+        .cfg_gpio = s5p6450_cfg_i2s,
+};
+
+static struct resource s5p64x0_iis0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_I2S,
+                .end    = S5P64X0_PA_I2S + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_I2S0_TX,
+                .end    = DMACH_I2S0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_I2S0_RX,
+                .end    = DMACH_I2S0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_iis = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6440_i2s_pdata,
+        },
+};
+
+struct platform_device s5p6450_device_iis0 = {
+        .name           = "s3c64xx-iis-v4",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_iis0_resource),
+        .resource       = s5p64x0_iis0_resource,
+        .dev = {
+                .platform_data = &s5p6450_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s5p6440_pcm_pdata = {
+        .cfg_gpio = s5p6440_pcm_cfg_gpio,
+};
+
+static struct resource s5p6440_pcm0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_PCM,
+                .end    = S5P64X0_PA_PCM + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_PCM0_TX,
+                .end    = DMACH_PCM0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_PCM0_RX,
+                .end    = DMACH_PCM0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_pcm = {
+        .name           = "samsung-pcm",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p6440_pcm0_resource),
+        .resource       = s5p6440_pcm0_resource,
+        .dev = {
+                .platform_data = &s5p6440_pcm_pdata,
+        },
+};
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
new file mode 100644
index 000000000000..5b69ec4c8af3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -0,0 +1,232 @@
+/* linux/arch/arm/mach-s5p64x0/dev-spi.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/regs-clock.h>
+#include <mach/spi-clocks.h>
+
+#include <plat/s3c64xx-spi.h>
+#include <plat/gpio-cfg.h>
+
+static char *s5p64x0_spi_src_clks[] = {
+        [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
+        [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
+};
+
+/* SPI Controller platform_devices */
+
+/* Since we emulate multi-cs capability, we do not touch the CS.
+ * The emulated CS is toggled by board specific mechanism, as it can
+ * be either some immediate GPIO or some signal out of some other
+ * chip in between ... or some yet another way.
+ * We simply do not assume anything about CS.
+ */
+static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
+                break;
+
+        case 1:
+                s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
+                s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
+                break;
+
+        default:
+                dev_err(&pdev->dev, "Invalid SPI Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct resource s5p64x0_spi0_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI0,
+                .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI0_TX,
+                .end    = DMACH_SPI0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI0_RX,
+                .end    = DMACH_SPI0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI0,
+                .end    = IRQ_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p64x0_device_spi0 = {
+        .name           = "s3c64xx-spi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
+        .resource       = s5p64x0_spi0_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource s5p64x0_spi1_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_SPI1,
+                .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPI1_TX,
+                .end    = DMACH_SPI1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMACH_SPI1_RX,
+                .end    = DMACH_SPI1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = IRQ_SPI1,
+                .end    = IRQ_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
+        .cfg_gpio       = s5p6440_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
+        .cfg_gpio       = s5p6450_spi_cfg_gpio,
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+};
+
+struct platform_device s5p64x0_device_spi1 = {
+        .name           = "s3c64xx-spi",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
+        .resource       = s5p64x0_spi1_resource,
+        .dev = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
+{
+        unsigned int id;
+        struct s3c64xx_spi_info *pd;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        /* Reject invalid configuration */
+        if (!num_cs || src_clk_nr < 0
+                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
+                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
+                return;
+        }
+
+        switch (cntrlr) {
+        case 0:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi0_pdata;
+                else
+                        pd = &s5p6440_spi0_pdata;
+
+                s5p64x0_device_spi0.dev.platform_data = pd;
+                break;
+        case 1:
+                if (id == 0x50000)
+                        pd = &s5p6450_spi1_pdata;
+                else
+                        pd = &s5p6440_spi1_pdata;
+
+                s5p64x0_device_spi1.dev.platform_data = pd;
+                break;
+        default:
+                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
+                                                        __func__, cntrlr);
+                return;
+        }
+
+        pd->num_cs = num_cs;
+        pd->src_clk_nr = src_clk_nr;
+        pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
+}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
new file mode 100644
index 000000000000..29a8c2410049
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -0,0 +1,149 @@
+/* linux/arch/arm/mach-s5p64x0/dma.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/regs-clock.h>
+
+#include <plat/devs.h>
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5p64x0_pdma_resource[] = {
+        [0] = {
+                .start  = S5P64X0_PA_PDMA,
+                .end    = S5P64X0_PA_PDMA + SZ_4K,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DMA0,
+                .end    = IRQ_DMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_MAX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_MAX,
+                [17] = DMACH_MAX,
+                [18] = DMACH_MAX,
+                [19] = DMACH_MAX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_MAX,
+                [23] = DMACH_MAX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_MAX,
+                [26] = DMACH_MAX,
+                [27] = DMACH_MAX,
+                [28] = DMACH_MAX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_UART4_RX,
+                [9] = DMACH_UART4_TX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_PCM1_TX,
+                [17] = DMACH_PCM1_RX,
+                [18] = DMACH_PCM2_TX,
+                [19] = DMACH_PCM2_RX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_USI_TX,
+                [23] = DMACH_USI_RX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_I2S1_TX,
+                [26] = DMACH_I2S1_RX,
+                [27] = DMACH_I2S2_TX,
+                [28] = DMACH_I2S2_RX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_UART5_RX,
+                [31] = DMACH_UART5_TX,
+        },
+};
+
+static struct platform_device s5p64x0_device_pdma = {
+        .name           = "s3c-pl330",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p64x0_pdma_resource),
+        .resource       = s5p64x0_pdma_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static int __init s5p64x0_dma_init(void)
+{
+        unsigned int id;
+
+        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
+
+        if (id == 0x50000)
+                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
+        else
+                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+
+        platform_device_register(&s5p64x0_device_pdma);
+
+        return 0;
+}
+arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p64x0/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
new file mode 100644
index 000000000000..39159dd5a29a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -0,0 +1,342 @@
+/* linux/arch/arm/mach-s5p64x0/gpio.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+/* To be implemented S5P6450 GPIO */
+
+/*
+ * S5P6440 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   SlpCon  ExtInt Group
+ * A    6       4Bit    Yes     1
+ * B    7       4Bit    Yes     1
+ * C    8       4Bit    Yes     2
+ * F    2       2Bit    Yes     4 [1]
+ * G    7       4Bit    Yes     5
+ * H    10      4Bit[2] Yes     6
+ * I    16      2Bit    Yes     None
+ * J    12      2Bit    Yes     None
+ * N    16      2Bit    No      IRQ_EINT
+ * P    8       2Bit    Yes     8
+ * R    15      4Bit[2] Yes     8
+ *
+ * [1] BANKF pins 14,15 do not form part of the external interrupt sources
+ * [2] BANK has two control registers, GPxCON0 and GPxCON1
+ */
+
+static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
+                                             unsigned int offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        void __iomem *regcon = base;
+        unsigned long con;
+        unsigned long flags;
+
+        switch (offset) {
+        case 6:
+                offset += 1;
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+                regcon -= 4;
+                break;
+        default:
+                offset -= 7;
+                break;
+        }
+
+        s3c_gpio_lock(ourchip, flags);
+
+        con = __raw_readl(regcon);
+        con &= ~(0xf << con_4bit_shift(offset));
+        __raw_writel(con, regcon);
+
+        s3c_gpio_unlock(ourchip, flags);
+
+        return 0;
+}
+
+static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
+                                              unsigned int offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        void __iomem *regcon = base;
+        unsigned long con;
+        unsigned long dat;
+        unsigned long flags;
+        unsigned con_offset  = offset;
+
+        switch (con_offset) {
+        case 6:
+                con_offset += 1;
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+                regcon -= 4;
+                break;
+        default:
+                con_offset -= 7;
+                break;
+        }
+
+        s3c_gpio_lock(ourchip, flags);
+
+        con = __raw_readl(regcon);
+        con &= ~(0xf << con_4bit_shift(con_offset));
+        con |= 0x1 << con_4bit_shift(con_offset);
+
+        dat = __raw_readl(base + GPIODAT_OFF);
+        if (value)
+                dat |= 1 << offset;
+        else
+                dat &= ~(1 << offset);
+
+        __raw_writel(con, regcon);
+        __raw_writel(dat, base + GPIODAT_OFF);
+
+        s3c_gpio_unlock(ourchip, flags);
+
+        return 0;
+}
+
+int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
+                                   unsigned int off, unsigned int cfg)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift;
+        u32 con;
+
+        switch (off) {
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+        case 5:
+                shift = (off & 7) * 4;
+                reg -= 4;
+                break;
+        case 6:
+                shift = ((off + 1) & 7) * 4;
+                reg -= 4;
+        default:
+                shift = ((off + 1) & 7) * 4;
+                break;
+        }
+
+        if (s3c_gpio_is_cfg_special(cfg)) {
+                cfg &= 0xf;
+                cfg <<= shift;
+        }
+
+        con = __raw_readl(reg);
+        con &= ~(0xf << shift);
+        con |= cfg;
+        __raw_writel(con, reg);
+
+        return 0;
+}
+
+static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
+        {
+                .cfg_eint       = 0,
+        }, {
+                .cfg_eint       = 7,
+        }, {
+                .cfg_eint       = 3,
+                .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
+        }, {
+                .cfg_eint       = 0,
+                .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
+        }, {
+                .cfg_eint       = 2,
+                .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
+        }, {
+                .cfg_eint       = 3,
+                .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
+        },
+};
+
+static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
+        {
+                .base   = S5P6440_GPA_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6440_GPA(0),
+                        .ngpio  = S5P6440_GPIO_A_NR,
+                        .label  = "GPA",
+                },
+        }, {
+                .base   = S5P6440_GPB_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6440_GPB(0),
+                        .ngpio  = S5P6440_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .base   = S5P6440_GPC_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6440_GPC(0),
+                        .ngpio  = S5P6440_GPIO_C_NR,
+                        .label  = "GPC",
+                },
+        }, {
+                .base   = S5P6440_GPG_BASE,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6440_GPG(0),
+                        .ngpio  = S5P6440_GPIO_G_NR,
+                        .label  = "GPG",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
+        {
+                .base   = S5P6440_GPH_BASE + 0x4,
+                .config = &s5p64x0_gpio_cfgs[1],
+                .chip   = {
+                        .base   = S5P6440_GPH(0),
+                        .ngpio  = S5P6440_GPIO_H_NR,
+                        .label  = "GPH",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
+        {
+                .base   = S5P6440_GPR_BASE + 0x4,
+                .config = &s5p64x0_gpio_cfgs[2],
+                .chip   = {
+                        .base   = S5P6440_GPR(0),
+                        .ngpio  = S5P6440_GPIO_R_NR,
+                        .label  = "GPR",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
+        {
+                .base   = S5P6440_GPF_BASE,
+                .config = &s5p64x0_gpio_cfgs[5],
+                .chip   = {
+                        .base   = S5P6440_GPF(0),
+                        .ngpio  = S5P6440_GPIO_F_NR,
+                        .label  = "GPF",
+                },
+        }, {
+                .base   = S5P6440_GPI_BASE,
+                .config = &s5p64x0_gpio_cfgs[3],
+                .chip   = {
+                        .base   = S5P6440_GPI(0),
+                        .ngpio  = S5P6440_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .base   = S5P6440_GPJ_BASE,
+                .config = &s5p64x0_gpio_cfgs[3],
+                .chip   = {
+                        .base   = S5P6440_GPJ(0),
+                        .ngpio  = S5P6440_GPIO_J_NR,
+                        .label  = "GPJ",
+                },
+        }, {
+                .base   = S5P6440_GPN_BASE,
+                .config = &s5p64x0_gpio_cfgs[4],
+                .chip   = {
+                        .base   = S5P6440_GPN(0),
+                        .ngpio  = S5P6440_GPIO_N_NR,
+                        .label  = "GPN",
+                },
+        }, {
+                .base   = S5P6440_GPP_BASE,
+                .config = &s5p64x0_gpio_cfgs[5],
+                .chip   = {
+                        .base   = S5P6440_GPP(0),
+                        .ngpio  = S5P6440_GPIO_P_NR,
+                        .label  = "GPP",
+                },
+        },
+};
+
+void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
+{
+        for (; nr_chips > 0; nr_chips--, chipcfg++) {
+                if (!chipcfg->set_config)
+                        chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
+                if (!chipcfg->get_config)
+                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
+                if (!chipcfg->set_pull)
+                        chipcfg->set_pull       = s3c_gpio_setpull_updown;
+                if (!chipcfg->get_pull)
+                        chipcfg->get_pull       = s3c_gpio_getpull_updown;
+        }
+}
+
+static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
+                                                int nr_chips)
+{
+        for (; nr_chips > 0; nr_chips--, chip++) {
+                chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
+                chip->chip.direction_output =
+                                        s5p64x0_gpiolib_rbank_4bit2_output;
+                s3c_gpiolib_add(chip);
+        }
+}
+
+static int __init s5p6440_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
+        int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
+
+        s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
+                                ARRAY_SIZE(s5p64x0_gpio_cfgs));
+
+        for (; nr_chips > 0; nr_chips--, chips++)
+                s3c_gpiolib_add(chips);
+
+        samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
+                                ARRAY_SIZE(s5p6440_gpio_4bit));
+
+        samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
+                                ARRAY_SIZE(s5p6440_gpio_4bit2));
+
+        s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
+                                ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
+
+        return 0;
+}
+arch_initcall(s5p6440_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79b04e6a6f8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#include <plat/regs-serial.h>
+
+        .macro addruart, rp, rv
+                mov     \rp, #0xE0000000
+                orr     \rp, \rp, #0x00100000
+                ldr     \rp, [\rp, #0x118 ]
+                and     \rp, \rp, #0xff000
+                teq     \rp, #0x50000           @@ S5P6450
+                ldreq   \rp, =0xEC800000
+                movne   \rp, #0xEC000000        @@ S5P6440
+                ldrne   \rv, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
+                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
+        .endm
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
new file mode 100644
index 000000000000..81209eb1409b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
new file mode 100644
index 000000000000..10b62b4f8211
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Low-level IRQ helper macros for the Samsung S5P64X0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/map.h>
+#include <plat/irqs.h>
+
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+/* GPIO bank sizes */
+
+#define S5P6440_GPIO_A_NR       (6)
+#define S5P6440_GPIO_B_NR       (7)
+#define S5P6440_GPIO_C_NR       (8)
+#define S5P6440_GPIO_F_NR       (2)
+#define S5P6440_GPIO_G_NR       (7)
+#define S5P6440_GPIO_H_NR       (10)
+#define S5P6440_GPIO_I_NR       (16)
+#define S5P6440_GPIO_J_NR       (12)
+#define S5P6440_GPIO_N_NR       (16)
+#define S5P6440_GPIO_P_NR       (8)
+#define S5P6440_GPIO_R_NR       (15)
+
+#define S5P6450_GPIO_A_NR       (6)
+#define S5P6450_GPIO_B_NR       (7)
+#define S5P6450_GPIO_C_NR       (8)
+#define S5P6450_GPIO_D_NR       (8)
+#define S5P6450_GPIO_F_NR       (2)
+#define S5P6450_GPIO_G_NR       (14)
+#define S5P6450_GPIO_H_NR       (10)
+#define S5P6450_GPIO_I_NR       (16)
+#define S5P6450_GPIO_J_NR       (12)
+#define S5P6450_GPIO_K_NR       (5)
+#define S5P6450_GPIO_N_NR       (16)
+#define S5P6450_GPIO_P_NR       (11)
+#define S5P6450_GPIO_Q_NR       (14)
+#define S5P6450_GPIO_R_NR       (15)
+#define S5P6450_GPIO_S_NR       (8)
+
+/* GPIO bank numbers */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S5P64X0_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p6440_gpio_number {
+        S5P6440_GPIO_A_START    = 0,
+        S5P6440_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
+        S5P6440_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
+        S5P6440_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
+        S5P6440_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
+        S5P6440_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
+        S5P6440_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
+        S5P6440_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
+        S5P6440_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
+        S5P6440_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
+        S5P6440_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
+};
+
+enum s5p6450_gpio_number {
+        S5P6450_GPIO_A_START    = 0,
+        S5P6450_GPIO_B_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
+        S5P6450_GPIO_C_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
+        S5P6450_GPIO_D_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
+        S5P6450_GPIO_F_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
+        S5P6450_GPIO_G_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
+        S5P6450_GPIO_H_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
+        S5P6450_GPIO_I_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
+        S5P6450_GPIO_J_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
+        S5P6450_GPIO_K_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
+        S5P6450_GPIO_N_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
+        S5P6450_GPIO_P_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
+        S5P6450_GPIO_Q_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
+        S5P6450_GPIO_R_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
+        S5P6450_GPIO_S_START    = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
+};
+
+/* GPIO number definitions */
+
+#define S5P6440_GPA(_nr)        (S5P6440_GPIO_A_START + (_nr))
+#define S5P6440_GPB(_nr)        (S5P6440_GPIO_B_START + (_nr))
+#define S5P6440_GPC(_nr)        (S5P6440_GPIO_C_START + (_nr))
+#define S5P6440_GPF(_nr)        (S5P6440_GPIO_F_START + (_nr))
+#define S5P6440_GPG(_nr)        (S5P6440_GPIO_G_START + (_nr))
+#define S5P6440_GPH(_nr)        (S5P6440_GPIO_H_START + (_nr))
+#define S5P6440_GPI(_nr)        (S5P6440_GPIO_I_START + (_nr))
+#define S5P6440_GPJ(_nr)        (S5P6440_GPIO_J_START + (_nr))
+#define S5P6440_GPN(_nr)        (S5P6440_GPIO_N_START + (_nr))
+#define S5P6440_GPP(_nr)        (S5P6440_GPIO_P_START + (_nr))
+#define S5P6440_GPR(_nr)        (S5P6440_GPIO_R_START + (_nr))
+
+#define S5P6450_GPA(_nr)        (S5P6450_GPIO_A_START + (_nr))
+#define S5P6450_GPB(_nr)        (S5P6450_GPIO_B_START + (_nr))
+#define S5P6450_GPC(_nr)        (S5P6450_GPIO_C_START + (_nr))
+#define S5P6450_GPD(_nr)        (S5P6450_GPIO_D_START + (_nr))
+#define S5P6450_GPF(_nr)        (S5P6450_GPIO_F_START + (_nr))
+#define S5P6450_GPG(_nr)        (S5P6450_GPIO_G_START + (_nr))
+#define S5P6450_GPH(_nr)        (S5P6450_GPIO_H_START + (_nr))
+#define S5P6450_GPI(_nr)        (S5P6450_GPIO_I_START + (_nr))
+#define S5P6450_GPJ(_nr)        (S5P6450_GPIO_J_START + (_nr))
+#define S5P6450_GPK(_nr)        (S5P6450_GPIO_K_START + (_nr))
+#define S5P6450_GPN(_nr)        (S5P6450_GPIO_N_START + (_nr))
+#define S5P6450_GPP(_nr)        (S5P6450_GPIO_P_START + (_nr))
+#define S5P6450_GPQ(_nr)        (S5P6450_GPIO_Q_START + (_nr))
+#define S5P6450_GPR(_nr)        (S5P6450_GPIO_R_START + (_nr))
+#define S5P6450_GPS(_nr)        (S5P6450_GPIO_S_START + (_nr))
+
+/* the end of the S5P64X0 specific gpios */
+
+#define S5P6440_GPIO_END        (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
+#define S5P6450_GPIO_END        (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
+
+#define S5P64X0_GPIO_END        (S5P6440_GPIO_END > S5P6450_GPIO_END ?  \
+                                 S5P6440_GPIO_END : S5P6450_GPIO_END)
+
+#define S3C_GPIO_END            S5P64X0_GPIO_END
+
+/* define the number of gpios we need to the one after the last GPIO range */
+
+#define ARCH_NR_GPIOS           (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
new file mode 100644
index 000000000000..d3e87996dd9a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Hardware support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/include/mach/i2c.h
new file mode 100644
index 000000000000..887d25209e8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/i2c.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 I2C configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
+
+extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
new file mode 100644
index 000000000000..a3e095c02fb5
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/io.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben-linux@fluff.org>
+ *
+ * Default IO routines for S5P64X0 based
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
new file mode 100644
index 000000000000..513abffc7604
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -0,0 +1,142 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
+ *
+ * Copyright 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#include <plat/irqs.h>
+
+/* VIC0 */
+
+#define IRQ_EINT0_3             S5P_IRQ_VIC0(0)
+#define IRQ_EINT4_11            S5P_IRQ_VIC0(1)
+#define IRQ_RTC_TIC             S5P_IRQ_VIC0(2)
+#define IRQ_IIS1                S5P_IRQ_VIC0(3) /* for only S5P6450 */
+#define IRQ_IIS2                S5P_IRQ_VIC0(4) /* for only S5P6450 */
+#define IRQ_IIC1                S5P_IRQ_VIC0(5)
+#define IRQ_I2SV40              S5P_IRQ_VIC0(6)
+#define IRQ_GPS                 S5P_IRQ_VIC0(7) /* for only S5P6450 */
+
+#define IRQ_2D                  S5P_IRQ_VIC0(11)
+#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(23)
+#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(24)
+#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(25)
+#define IRQ_WDT                 S5P_IRQ_VIC0(26)
+#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(27)
+#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(28)
+#define IRQ_DISPCON0            S5P_IRQ_VIC0(29)
+#define IRQ_DISPCON1            S5P_IRQ_VIC0(30)
+#define IRQ_DISPCON2            S5P_IRQ_VIC0(31)
+
+/* VIC1 */
+
+#define IRQ_EINT12_15           S5P_IRQ_VIC1(0)
+#define IRQ_PCM0                S5P_IRQ_VIC1(2)
+#define IRQ_PCM1                S5P_IRQ_VIC1(3) /* for only S5P6450 */
+#define IRQ_PCM2                S5P_IRQ_VIC1(4) /* for only S5P6450 */
+#define IRQ_UART0               S5P_IRQ_VIC1(5)
+#define IRQ_UART1               S5P_IRQ_VIC1(6)
+#define IRQ_UART2               S5P_IRQ_VIC1(7)
+#define IRQ_UART3               S5P_IRQ_VIC1(8)
+#define IRQ_DMA0                S5P_IRQ_VIC1(9)
+#define IRQ_UART4               S5P_IRQ_VIC1(10)        /* S5P6450 */
+#define IRQ_UART5               S5P_IRQ_VIC1(11)        /* S5P6450 */
+#define IRQ_NFC                 S5P_IRQ_VIC1(13)
+#define IRQ_USI                 S5P_IRQ_VIC1(15)        /* S5P6450 */
+#define IRQ_SPI0                S5P_IRQ_VIC1(16)
+#define IRQ_SPI1                S5P_IRQ_VIC1(17)
+#define IRQ_HSMMC2              S5P_IRQ_VIC1(17)        /* Shared */
+#define IRQ_IIC                 S5P_IRQ_VIC1(18)
+#define IRQ_DISPCON3            S5P_IRQ_VIC1(19)
+#define IRQ_EINT_GROUPS         S5P_IRQ_VIC1(21)
+#define IRQ_PMU                 S5P_IRQ_VIC1(23)        /* S5P6440 */
+#define IRQ_HSMMC0              S5P_IRQ_VIC1(24)
+#define IRQ_HSMMC1              S5P_IRQ_VIC1(25)
+#define IRQ_OTG                 S5P_IRQ_VIC1(26)
+#define IRQ_DSI                 S5P_IRQ_VIC1(27)
+#define IRQ_RTC_ALARM           S5P_IRQ_VIC1(28)
+#define IRQ_TSI                 S5P_IRQ_VIC1(29)
+#define IRQ_PENDN               S5P_IRQ_VIC1(30)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_ADC                 S5P_IRQ_VIC1(31)
+
+/* UART interrupts, S5P6450 has 5 UARTs */
+#define IRQ_S5P_UART_BASE4      (96)
+#define IRQ_S5P_UART_BASE5      (100)
+
+#define IRQ_S5P_UART_RX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX4        (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR4       (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX5        (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR5       (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
+
+/* S3C compatibilty defines */
+#define IRQ_S3CUART_RX4         IRQ_S5P_UART_RX4
+#define IRQ_S3CUART_RX5         IRQ_S5P_UART_RX5
+
+/* S5P6450 EINT feature will be added */
+
+/*
+ * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
+ * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
+ * after the pair of VICs.
+ */
+
+#define S5P_IRQ_EINT_BASE       (S5P_IRQ_VIC1(31) + 6)
+
+#define S5P_EINT(x)             ((x) + S5P_IRQ_EINT_BASE)
+
+#define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE)
+/*
+ * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
+ * to wake up from sleep. If request is beyond this range, by mistake, a large
+ * return value for an irq number should be indication of something amiss.
+ */
+#define S5P_EINT_BASE2          (0xf0000000)
+
+/*
+ * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
+
+/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
+#define IRQ_EINT_GROUP1_NR      (15)
+#define IRQ_EINT_GROUP2_NR      (8)
+#define IRQ_EINT_GROUP5_NR      (7)
+#define IRQ_EINT_GROUP6_NR      (10)
+/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
+#define IRQ_EINT_GROUP8_NR      (11)
+
+#define IRQ_EINT_GROUP_BASE     S5P_EINT(16)
+#define IRQ_EINT_GROUP1_BASE    (IRQ_EINT_GROUP_BASE + 0)
+#define IRQ_EINT_GROUP2_BASE    (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP5_BASE    (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP6_BASE    (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP8_BASE    (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+
+#define IRQ_EINT_GROUP(grp, x)  (IRQ_EINT_GROUP##grp##_BASE + (x))
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
new file mode 100644
index 000000000000..31e534156e06
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -0,0 +1,83 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+#include <plat/map-s5p.h>
+
+#define S5P64X0_PA_SDRAM        (0x20000000)
+
+#define S5P64X0_PA_CHIPID       (0xE0000000)
+#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
+
+#define S5P64X0_PA_SYSCON       (0xE0100000)
+#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
+
+#define S5P64X0_PA_GPIO         (0xE0308000)
+
+#define S5P64X0_PA_VIC0         (0xE4000000)
+#define S5P64X0_PA_VIC1         (0xE4100000)
+
+#define S5P64X0_PA_PDMA         (0xE9000000)
+
+#define S5P64X0_PA_TIMER        (0xEA000000)
+#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+
+#define S5P64X0_PA_RTC          (0xEA100000)
+
+#define S5P64X0_PA_WDT          (0xEA200000)
+
+#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0            S5P6450_PA_UART(0)
+#define S5P_PA_UART1            S5P6450_PA_UART(1)
+#define S5P_PA_UART2            S5P6450_PA_UART(2)
+#define S5P_PA_UART3            S5P6450_PA_UART(3)
+#define S5P_PA_UART4            S5P6450_PA_UART(4)
+#define S5P_PA_UART5            S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART             SZ_256
+
+#define S5P6440_PA_IIC0         (0xEC104000)
+#define S5P6440_PA_IIC1         (0xEC20F000)
+#define S5P6450_PA_IIC0         (0xEC100000)
+#define S5P6450_PA_IIC1         (0xEC200000)
+
+#define S5P64X0_PA_SPI0         (0xEC400000)
+#define S5P64X0_PA_SPI1         (0xEC500000)
+
+#define S5P64X0_PA_HSOTG        (0xED100000)
+
+#define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+
+#define S5P64X0_PA_I2S          (0xF2000000)
+
+#define S5P64X0_PA_PCM          (0xF2100000)
+
+#define S5P64X0_PA_ADC          (0xF3000000)
+
+/* compatibiltiy defines. */
+
+#define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
+#define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
+#define S3C_PA_HSMMC2           S5P64X0_PA_HSMMC(2)
+#define S3C_PA_IIC              S5P6440_PA_IIC0
+#define S3C_PA_IIC1             S5P6440_PA_IIC1
+#define S3C_PA_RTC              S5P64X0_PA_RTC
+#define S3C_PA_WDT              S5P64X0_PA_WDT
+
+#define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
new file mode 100644
index 000000000000..1b036b0a24ce
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Memory definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
+
+#define PHYS_OFFSET             UL(0x20000000)
+#define CONSISTENT_DMA_SIZE     SZ_8M
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..19fff8b701c0
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
@@ -0,0 +1,68 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S5P64X0 - pwm clock and timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PWMCLK_H
+#define __ASM_ARCH_PWMCLK_H __FILE__
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+        return 0;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+        return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+        return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK 0
+
+#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 000000000000..58e1bc813804
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
+
+#define S5P64X0_APLL_CON                S5P_CLKREG(0x0C)
+#define S5P64X0_MPLL_CON                S5P_CLKREG(0x10)
+#define S5P64X0_EPLL_CON                S5P_CLKREG(0x14)
+#define S5P64X0_EPLL_CON_K              S5P_CLKREG(0x18)
+
+#define S5P64X0_CLK_SRC0                S5P_CLKREG(0x1C)
+
+#define S5P64X0_CLK_DIV0                S5P_CLKREG(0x20)
+#define S5P64X0_CLK_DIV1                S5P_CLKREG(0x24)
+#define S5P64X0_CLK_DIV2                S5P_CLKREG(0x28)
+
+#define S5P64X0_CLK_GATE_HCLK0          S5P_CLKREG(0x30)
+#define S5P64X0_CLK_GATE_PCLK           S5P_CLKREG(0x34)
+#define S5P64X0_CLK_GATE_SCLK0          S5P_CLKREG(0x38)
+#define S5P64X0_CLK_GATE_MEM0           S5P_CLKREG(0x3C)
+
+#define S5P64X0_CLK_DIV3                S5P_CLKREG(0x40)
+
+#define S5P64X0_CLK_GATE_HCLK1          S5P_CLKREG(0x44)
+#define S5P64X0_CLK_GATE_SCLK1          S5P_CLKREG(0x48)
+
+#define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
+#define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
+
+#define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
+
+#define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
+#define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
+
+#define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+
+#define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
+#define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
+
+#define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
+
+/* Compatibility defines */
+
+#define ARM_CLK_DIV                     S5P64X0_CLK_DIV0
+#define ARM_DIV_RATIO_SHIFT             0
+#define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..85f448e20a8b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -0,0 +1,62 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - GPIO register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+
+/* Will be implemented S5P6442 GPIOlib */
+
+/* Base addresses for each of the banks */
+
+#define S5P6440_GPA_BASE                (S5P_VA_GPIO + 0x0000)
+#define S5P6440_GPB_BASE                (S5P_VA_GPIO + 0x0020)
+#define S5P6440_GPC_BASE                (S5P_VA_GPIO + 0x0040)
+#define S5P6440_GPF_BASE                (S5P_VA_GPIO + 0x00A0)
+#define S5P6440_GPG_BASE                (S5P_VA_GPIO + 0x00C0)
+#define S5P6440_GPH_BASE                (S5P_VA_GPIO + 0x00E0)
+#define S5P6440_GPI_BASE                (S5P_VA_GPIO + 0x0100)
+#define S5P6440_GPJ_BASE                (S5P_VA_GPIO + 0x0120)
+#define S5P6440_GPN_BASE                (S5P_VA_GPIO + 0x0830)
+#define S5P6440_GPP_BASE                (S5P_VA_GPIO + 0x0160)
+#define S5P6440_GPR_BASE                (S5P_VA_GPIO + 0x0290)
+
+#define S5P6440_EINT0CON0               (S5P_VA_GPIO + 0x900)
+#define S5P6440_EINT0FLTCON0            (S5P_VA_GPIO + 0x910)
+#define S5P6440_EINT0FLTCON1            (S5P_VA_GPIO + 0x914)
+#define S5P6440_EINT0MASK               (S5P_VA_GPIO + 0x920)
+#define S5P6440_EINT0PEND               (S5P_VA_GPIO + 0x924)
+
+/* for LCD */
+
+#define S5P6440_SPCON_LCD_SEL_RGB       (1 << 0)
+#define S5P6440_SPCON_LCD_SEL_MASK      (3 << 0)
+
+/*
+ * These set of macros are not really useful for the
+ * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
+ */
+
+#define S5P6440_GPIO_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
+#define S5P6440_GPIO_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
+#define S5P6440_GPIO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
+
+/*
+ * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
+ */
+
+#define S5P6440_GPIO2_CONMASK(__gpio)   (0x3 << ((__gpio) * 2))
+#define S5P6440_GPIO2_INPUT(__gpio)     (0x0 << ((__gpio) * 2))
+#define S5P6440_GPIO2_OUTPUT(__gpio)    (0x1 << ((__gpio) * 2))
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
new file mode 100644
index 000000000000..4aaebdace55f
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 000000000000..ff85b4b6e8d9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p64x0 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk clk_mout_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_mout_epll;
+
+extern int s5p64x0_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
+
+extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
+extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
+extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
+
+extern struct clk_ops s5p64x0_clkarm_ops;
+
+extern struct clksrc_clk clk_armclk;
+extern struct clksrc_clk clk_dout_mpll;
+
+extern struct clk *clkset_hclk_low_list[];
+extern struct clksrc_sources clkset_hclk_low;
+
+extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
+
+extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..170a20a9643a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+
+#define S5P64X0_SPI_SRCCLK_PCLK         0
+#define S5P64X0_SPI_SRCCLK_SCLK         1
+
+#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
new file mode 100644
index 000000000000..60f57532c970
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -0,0 +1,23 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - system support header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <plat/system-reset.h>
+
+static void arch_idle(void)
+{
+        /* nothing here yet */
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
new file mode 100644
index 000000000000..00aa7f1d8e51
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/tick.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S5P64X0 - Timer tick support definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TICK_H
+#define __ASM_ARCH_TICK_H __FILE__
+
+static inline u32 s3c24xx_ostimer_pending(void)
+{
+        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
+        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
+}
+
+#define TICK_MAX        (0xffffffff)
+
+#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
new file mode 100644
index 000000000000..4b91faa195a8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/timex.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S5P64X0 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
new file mode 100644
index 000000000000..c65b229aab23
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -0,0 +1,212 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+
+/*
+ * cannot use commonly <plat/uncompress.h>
+ * because uart base of S5P6440 and S5P6450 is different
+ */
+
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+
+/* uart setup */
+
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+
+/* forward declerations */
+
+static void arch_detect_cpu(void);
+
+/* defines for UART registers */
+
+#include <plat/regs-serial.h>
+#include <plat/regs-watchdog.h>
+
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+static unsigned long uart_base;
+
+static __inline__ void get_uart_base(void)
+{
+        unsigned int chipid;
+
+        chipid = *(const volatile unsigned int __force *) 0xE0100118;
+
+        uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
+
+        if ((chipid & 0xff000) == 0x50000)
+                uart_base += 0xEC800000;
+        else
+                uart_base += 0xEC000000;
+}
+
+static __inline__ void uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        get_uart_base();
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+/*
+ * we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+ */
+
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+
+                        if (level < fifo_max)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static inline void flush(void)
+{
+}
+
+#define __raw_writel(d, ad)                     \
+        do {                                                    \
+                *((volatile unsigned int __force *)(ad)) = (d); \
+        } while (0)
+
+/*
+ * CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+ */
+
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+
+        while(1);
+}
+
+#define arch_error arch_decomp_error
+#endif
+
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+        u32 fifocon = uart_rd(S3C2410_UFCON);
+
+        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+                fifocon |= S3C2410_UFCON_RESETBOTH;
+                uart_wr(S3C2410_UFCON, fifocon);
+
+                /* wait for fifo reset to complete */
+                while (1) {
+                        fifocon = uart_rd(S3C2410_UFCON);
+                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+                                break;
+                }
+        }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+static void arch_decomp_setup(void)
+{
+        /*
+         * we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+
+        /*
+         * Enable the UART FIFOs if they where not enabled and our
+         * configuration says we should turn them on.
+         */
+
+        arch_enable_uart_fifo();
+}
+
+
+
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
new file mode 100644
index 000000000000..97a9df38f1cf
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C6400 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     0xE0000000UL
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
new file mode 100644
index 000000000000..79833caf8165
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -0,0 +1,73 @@
+/* linux/arch/arm/mach-s5p64x0/init.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Init support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
+        [0] = {
+                .name           = "pclk_low",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+        [1] = {
+                .name           = "uclk1",
+                .divisor        = 1,
+                .min_baud       = 0,
+                .max_baud       = 0,
+        },
+};
+
+/* uart registration process */
+
+void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        struct s3c2410_uartcfg *tcfg = cfg;
+        u32 ucnt;
+
+        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+                if (!tcfg->clocks) {
+                        tcfg->clocks = s5p64x0_serial_clocks;
+                        tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
+                }
+        }
+}
+
+void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        int uart;
+
+        for (uart = 0; uart < no; uart++) {
+                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
+                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
+        }
+
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+
+void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s5p64x0_common_init_uarts(cfg, no);
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
new file mode 100644
index 000000000000..28de0a57208c
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -0,0 +1,163 @@
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
+
+#include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p6440.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+#include <plat/pll.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+
+#define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |         \
+                                S3C2410_UCON_TXIRQMODE |        \
+                                S3C2410_UCON_RXIRQMODE |        \
+                                S3C2410_UCON_RXFIFO_TOI |       \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK6440_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDK6440_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                S3C2440_UFCON_TXTRIG16 |        \
+                                S3C2410_UFCON_RXTRIG8)
+
+static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6440_UCON_DEFAULT,
+                .ulcon          = SMDK6440_ULCON_DEFAULT,
+                .ufcon          = SMDK6440_UFCON_DEFAULT,
+        },
+};
+
+static struct platform_device *smdk6440_devices[] __initdata = {
+        &s3c_device_adc,
+        &s3c_device_rtc,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+        &s5p6440_device_iis,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6440_i2c1_cfg_gpio,
+};
+
+static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("24c08", 0x50), },
+};
+
+static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
+        /* To be populated */
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
+static void __init smdk6440_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
+}
+
+static void __init smdk6440_machine_init(void)
+{
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+        s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
+        i2c_register_board_info(0, smdk6440_i2c_devs0,
+                        ARRAY_SIZE(smdk6440_i2c_devs0));
+        i2c_register_board_info(1, smdk6440_i2c_devs1,
+                        ARRAY_SIZE(smdk6440_i2c_devs1));
+
+        platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
+}
+
+MACHINE_START(SMDK6440, "SMDK6440")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .phys_io        = S5P6440_PA_UART(0) & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+
+        .init_irq       = s5p6440_init_irq,
+        .map_io         = smdk6440_map_io,
+        .init_machine   = smdk6440_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
new file mode 100644
index 000000000000..8e982171418b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -0,0 +1,182 @@
+/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/i2c.h>
+
+#include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s5p6450.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+#include <plat/pll.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
+
+#define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |         \
+                                S3C2410_UCON_TXIRQMODE |        \
+                                S3C2410_UCON_RXIRQMODE |        \
+                                S3C2410_UCON_RXFIFO_TOI |       \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK6450_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDK6450_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                S3C2440_UFCON_TXTRIG16 |        \
+                                S3C2410_UFCON_RXTRIG8)
+
+static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [4] = {
+                .hwport         = 4,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [5] = {
+                .hwport         = 5,
+                .flags          = 0,
+                .ucon           = SMDK6450_UCON_DEFAULT,
+                .ulcon          = SMDK6450_ULCON_DEFAULT,
+                .ufcon          = SMDK6450_UFCON_DEFAULT,
+        },
+#endif
+};
+
+static struct platform_device *smdk6450_devices[] __initdata = {
+        &s3c_device_adc,
+        &s3c_device_rtc,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_ts,
+        &s3c_device_wdt,
+        &s5p6450_device_iis0,
+        /* s5p6450_device_spi0 will be added */
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c0_cfg_gpio,
+};
+
+static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 1,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+        .cfg_gpio       = s5p6450_i2c1_cfg_gpio,
+};
+
+static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
+        { I2C_BOARD_INFO("24c08", 0x50), },     /* Samsung KS24C080C EEPROM */
+};
+
+static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
+        { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
+static void __init smdk6450_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s3c24xx_init_clocks(19200000);
+        s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
+}
+
+static void __init smdk6450_machine_init(void)
+{
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+        s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
+        s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
+        i2c_register_board_info(0, smdk6450_i2c_devs0,
+                        ARRAY_SIZE(smdk6450_i2c_devs0));
+        i2c_register_board_info(1, smdk6450_i2c_devs1,
+                        ARRAY_SIZE(smdk6450_i2c_devs1));
+
+        platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
+}
+
+MACHINE_START(SMDK6450, "SMDK6450")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .phys_io        = S5P6450_PA_UART(0) & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5P64X0_PA_SDRAM + 0x100,
+
+        .init_irq       = s5p6450_init_irq,
+        .map_io         = smdk6450_map_io,
+        .init_machine   = smdk6450_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
new file mode 100644
index 000000000000..dc4cc65a5019
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * I2C0 GPIO configuration.
+ *
+ * Based on plat-s3c64x0/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+
+#include <mach/i2c.h>
+
+void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
+}
+
+void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
new file mode 100644
index 000000000000..2edd7912f8e4
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * I2C1 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+
+#include <mach/i2c.h>
+
+void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
+}
+
+void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
+        s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
+}
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }