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-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c4
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c4
-rw-r--r--arch/arm/mach-s5p64x0/clock.c18
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-clock.h2
4 files changed, 6 insertions, 22 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index f93dcd8b4d6a..cfccdff744d2 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -85,7 +85,7 @@ static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
85} 85}
86 86
87static struct clk_ops s5p6440_epll_ops = { 87static struct clk_ops s5p6440_epll_ops = {
88 .get_rate = s5p64x0_epll_get_rate, 88 .get_rate = s5p_epll_get_rate,
89 .set_rate = s5p6440_epll_set_rate, 89 .set_rate = s5p6440_epll_set_rate,
90}; 90};
91 91
@@ -548,7 +548,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
548 548
549 /* Set S5P6440 functions for clk_fout_epll */ 549 /* Set S5P6440 functions for clk_fout_epll */
550 550
551 clk_fout_epll.enable = s5p64x0_epll_enable; 551 clk_fout_epll.enable = s5p_epll_enable;
552 clk_fout_epll.ops = &s5p6440_epll_ops; 552 clk_fout_epll.ops = &s5p6440_epll_ops;
553 553
554 clk_48m.enable = s5p64x0_clk48m_ctrl; 554 clk_48m.enable = s5p64x0_clk48m_ctrl;
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index f9afb05b217c..f1498d35111b 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -86,7 +86,7 @@ static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
86} 86}
87 87
88static struct clk_ops s5p6450_epll_ops = { 88static struct clk_ops s5p6450_epll_ops = {
89 .get_rate = s5p64x0_epll_get_rate, 89 .get_rate = s5p_epll_get_rate,
90 .set_rate = s5p6450_epll_set_rate, 90 .set_rate = s5p6450_epll_set_rate,
91}; 91};
92 92
@@ -581,7 +581,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
581 581
582 /* Set S5P6450 functions for clk_fout_epll */ 582 /* Set S5P6450 functions for clk_fout_epll */
583 583
584 clk_fout_epll.enable = s5p64x0_epll_enable; 584 clk_fout_epll.enable = s5p_epll_enable;
585 clk_fout_epll.ops = &s5p6450_epll_ops; 585 clk_fout_epll.ops = &s5p6450_epll_ops;
586 586
587 clk_48m.enable = s5p64x0_clk48m_ctrl; 587 clk_48m.enable = s5p64x0_clk48m_ctrl;
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 523ba8039ac2..b52c6e2f37a6 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,24 +73,6 @@ static const u32 clock_table[][3] = {
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, 73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74}; 74};
75 75
76int s5p64x0_epll_enable(struct clk *clk, int enable)
77{
78 unsigned int ctrlbit = clk->ctrlbit;
79 unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
80
81 if (enable)
82 __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
83 else
84 __raw_writel(epll_con, S5P64X0_EPLL_CON);
85
86 return 0;
87}
88
89unsigned long s5p64x0_epll_get_rate(struct clk *clk)
90{
91 return clk->rate;
92}
93
94unsigned long s5p64x0_armclk_get_rate(struct clk *clk) 76unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
95{ 77{
96 unsigned long rate = clk_get_rate(clk->parent); 78 unsigned long rate = clk_get_rate(clk->parent);
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index 58e1bc813804..a133f22fa155 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -60,4 +60,6 @@
60#define ARM_DIV_RATIO_SHIFT 0 60#define ARM_DIV_RATIO_SHIFT 0
61#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT) 61#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
62 62
63#define S5P_EPLL_CON S5P64X0_EPLL_CON
64
63#endif /* __ASM_ARCH_REGS_CLOCK_H */ 65#endif /* __ASM_ARCH_REGS_CLOCK_H */